Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7252908 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5084378 |
1 |
|
|
T36 |
33 |
|
T40 |
18815 |
|
T41 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2227622 |
1 |
|
|
T36 |
3 |
|
T40 |
8442 |
|
T41 |
10 |
| auto[1] |
auto[0] |
auto[1] |
322008 |
1 |
|
|
T40 |
1106 |
|
T51 |
8 |
|
T113 |
116 |
| auto[1] |
auto[1] |
auto[0] |
2213713 |
1 |
|
|
T36 |
29 |
|
T40 |
8183 |
|
T41 |
18 |
| auto[1] |
auto[1] |
auto[1] |
321035 |
1 |
|
|
T36 |
1 |
|
T40 |
1084 |
|
T51 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |