Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7252535 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5084751 |
1 |
|
|
T36 |
48 |
|
T40 |
19501 |
|
T41 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10229709 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
2107577 |
1 |
|
|
T36 |
10 |
|
T40 |
7387 |
|
T41 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7247412 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5089874 |
1 |
|
|
T36 |
41 |
|
T40 |
18823 |
|
T41 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1498159 |
1 |
|
|
T36 |
8 |
|
T40 |
5195 |
|
T41 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1061601 |
1 |
|
|
T36 |
8 |
|
T40 |
3551 |
|
T41 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1484138 |
1 |
|
|
T36 |
23 |
|
T40 |
6241 |
|
T51 |
98 |
| auto[1] |
auto[1] |
auto[1] |
1045976 |
1 |
|
|
T36 |
2 |
|
T40 |
3836 |
|
T51 |
373 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |