Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7246939 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5090347 |
1 |
|
|
T36 |
85 |
|
T40 |
20495 |
|
T41 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10219493 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
2117793 |
1 |
|
|
T36 |
31 |
|
T40 |
7439 |
|
T51 |
582 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7237183 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5100103 |
1 |
|
|
T36 |
57 |
|
T40 |
19697 |
|
T41 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1493186 |
1 |
|
|
T36 |
3 |
|
T40 |
5919 |
|
T41 |
10 |
| auto[1] |
auto[0] |
auto[1] |
1065188 |
1 |
|
|
T36 |
6 |
|
T40 |
3477 |
|
T51 |
345 |
| auto[1] |
auto[1] |
auto[0] |
1489124 |
1 |
|
|
T36 |
23 |
|
T40 |
6339 |
|
T41 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1052605 |
1 |
|
|
T36 |
25 |
|
T40 |
3962 |
|
T51 |
237 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |