Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7215297 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5121989 |
1 |
|
|
T36 |
54 |
|
T40 |
18009 |
|
T41 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10221589 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
2115697 |
1 |
|
|
T36 |
27 |
|
T40 |
7461 |
|
T41 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7223760 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5113526 |
1 |
|
|
T36 |
54 |
|
T40 |
19181 |
|
T41 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1500404 |
1 |
|
|
T36 |
16 |
|
T40 |
5889 |
|
T41 |
1 |
| auto[1] |
auto[0] |
auto[1] |
1058190 |
1 |
|
|
T36 |
11 |
|
T40 |
3965 |
|
T41 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1497425 |
1 |
|
|
T36 |
11 |
|
T40 |
5831 |
|
T51 |
90 |
| auto[1] |
auto[1] |
auto[1] |
1057507 |
1 |
|
|
T36 |
16 |
|
T40 |
3496 |
|
T41 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |