Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7252546 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5084740 |
1 |
|
|
T36 |
37 |
|
T40 |
18392 |
|
T41 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10227688 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
2109598 |
1 |
|
|
T36 |
32 |
|
T40 |
6952 |
|
T41 |
10 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7242639 |
1 |
|
|
T31 |
529 |
|
T32 |
408 |
|
T33 |
79 |
| auto[1] |
5094647 |
1 |
|
|
T36 |
52 |
|
T40 |
18547 |
|
T41 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1503982 |
1 |
|
|
T36 |
16 |
|
T40 |
6032 |
|
T51 |
118 |
| auto[1] |
auto[0] |
auto[1] |
1060545 |
1 |
|
|
T36 |
21 |
|
T40 |
3538 |
|
T41 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1481067 |
1 |
|
|
T36 |
4 |
|
T40 |
5563 |
|
T51 |
128 |
| auto[1] |
auto[1] |
auto[1] |
1049053 |
1 |
|
|
T36 |
11 |
|
T40 |
3414 |
|
T41 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |