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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 938
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T89 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2480063162 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:01 PM PDT 24 36470108 ps
T56 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.375703212 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:16 PM PDT 24 139686175 ps
T767 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3614186513 Jul 05 04:27:47 PM PDT 24 Jul 05 04:27:52 PM PDT 24 12546174 ps
T54 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1024595235 Jul 05 04:27:49 PM PDT 24 Jul 05 04:27:55 PM PDT 24 83091729 ps
T57 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2570993907 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:01 PM PDT 24 381972185 ps
T90 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.329021028 Jul 05 04:27:34 PM PDT 24 Jul 05 04:27:38 PM PDT 24 138757226 ps
T768 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2380581227 Jul 05 04:28:07 PM PDT 24 Jul 05 04:28:19 PM PDT 24 161217169 ps
T110 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2261087752 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:04 PM PDT 24 120558922 ps
T769 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1596825430 Jul 05 04:27:50 PM PDT 24 Jul 05 04:27:56 PM PDT 24 270091221 ps
T770 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3198152756 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:41 PM PDT 24 112574085 ps
T771 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3953836821 Jul 05 04:27:34 PM PDT 24 Jul 05 04:27:37 PM PDT 24 180936068 ps
T772 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3871972660 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:07 PM PDT 24 90739294 ps
T773 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2930164058 Jul 05 04:27:53 PM PDT 24 Jul 05 04:27:58 PM PDT 24 111598408 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4285322847 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:46 PM PDT 24 32668972 ps
T775 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.21513681 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:15 PM PDT 24 103414424 ps
T776 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1412243655 Jul 05 04:27:57 PM PDT 24 Jul 05 04:28:02 PM PDT 24 25718032 ps
T777 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1504401313 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:05 PM PDT 24 332798188 ps
T778 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.798747533 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:08 PM PDT 24 17824772 ps
T779 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1211930014 Jul 05 04:27:30 PM PDT 24 Jul 05 04:27:33 PM PDT 24 164283897 ps
T780 /workspace/coverage/cover_reg_top/42.gpio_intr_test.4294002839 Jul 05 04:28:05 PM PDT 24 Jul 05 04:28:13 PM PDT 24 57492727 ps
T91 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3237872497 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:00 PM PDT 24 14875996 ps
T781 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1457901420 Jul 05 04:27:55 PM PDT 24 Jul 05 04:28:00 PM PDT 24 57757483 ps
T782 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3948751698 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:47 PM PDT 24 46067235 ps
T783 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2751408612 Jul 05 04:27:50 PM PDT 24 Jul 05 04:27:56 PM PDT 24 18058713 ps
T784 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.12008426 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:08 PM PDT 24 45119378 ps
T785 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.857764818 Jul 05 04:27:33 PM PDT 24 Jul 05 04:27:35 PM PDT 24 38874553 ps
T786 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2425019972 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:16 PM PDT 24 15488578 ps
T787 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3535939606 Jul 05 04:27:46 PM PDT 24 Jul 05 04:27:51 PM PDT 24 38260634 ps
T788 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3579510252 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:14 PM PDT 24 96332389 ps
T789 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3260016322 Jul 05 04:27:56 PM PDT 24 Jul 05 04:28:00 PM PDT 24 22315038 ps
T790 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1988094876 Jul 05 04:28:03 PM PDT 24 Jul 05 04:28:10 PM PDT 24 12004865 ps
T791 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.413341601 Jul 05 04:28:06 PM PDT 24 Jul 05 04:28:16 PM PDT 24 27177183 ps
T792 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2207583825 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:08 PM PDT 24 320754439 ps
T793 /workspace/coverage/cover_reg_top/27.gpio_intr_test.635241359 Jul 05 04:27:57 PM PDT 24 Jul 05 04:28:02 PM PDT 24 29159569 ps
T794 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3254571827 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:49 PM PDT 24 1813606486 ps
T795 /workspace/coverage/cover_reg_top/32.gpio_intr_test.564492624 Jul 05 04:27:48 PM PDT 24 Jul 05 04:27:54 PM PDT 24 30230788 ps
T796 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3708306807 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:46 PM PDT 24 19735986 ps
T797 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1891930761 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:03 PM PDT 24 43778551 ps
T798 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2801514514 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:21 PM PDT 24 27194113 ps
T799 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.267076974 Jul 05 04:27:53 PM PDT 24 Jul 05 04:27:58 PM PDT 24 28079670 ps
T94 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2330480223 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:40 PM PDT 24 12436860 ps
T800 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1441909340 Jul 05 04:27:51 PM PDT 24 Jul 05 04:27:57 PM PDT 24 57106226 ps
T801 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1642121643 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:57 PM PDT 24 17685407 ps
T802 /workspace/coverage/cover_reg_top/22.gpio_intr_test.30938605 Jul 05 04:27:57 PM PDT 24 Jul 05 04:28:02 PM PDT 24 13697135 ps
T803 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2441464830 Jul 05 04:28:15 PM PDT 24 Jul 05 04:28:28 PM PDT 24 18130854 ps
T804 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1281024048 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:08 PM PDT 24 161780677 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.901214918 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:06 PM PDT 24 124603319 ps
T805 /workspace/coverage/cover_reg_top/19.gpio_intr_test.770786260 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:07 PM PDT 24 37344536 ps
T806 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2431438715 Jul 05 04:27:39 PM PDT 24 Jul 05 04:27:42 PM PDT 24 11193989 ps
T92 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2920612059 Jul 05 04:28:02 PM PDT 24 Jul 05 04:28:09 PM PDT 24 36393304 ps
T807 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4253448802 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:05 PM PDT 24 24213965 ps
T111 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.765538410 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:39 PM PDT 24 83458348 ps
T808 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.419877111 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:41 PM PDT 24 367109127 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1989226525 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:38 PM PDT 24 39242509 ps
T810 /workspace/coverage/cover_reg_top/21.gpio_intr_test.3115232035 Jul 05 04:28:01 PM PDT 24 Jul 05 04:28:08 PM PDT 24 81035714 ps
T811 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2277348596 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:04 PM PDT 24 23496148 ps
T812 /workspace/coverage/cover_reg_top/35.gpio_intr_test.670200808 Jul 05 04:28:03 PM PDT 24 Jul 05 04:28:11 PM PDT 24 98171271 ps
T813 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3146630906 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:13 PM PDT 24 121809765 ps
T814 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3799479592 Jul 05 04:28:09 PM PDT 24 Jul 05 04:28:20 PM PDT 24 14969350 ps
T815 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2613954123 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:07 PM PDT 24 65644050 ps
T816 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1876544546 Jul 05 04:27:35 PM PDT 24 Jul 05 04:27:38 PM PDT 24 137038625 ps
T817 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1988232928 Jul 05 04:28:00 PM PDT 24 Jul 05 04:28:07 PM PDT 24 37747774 ps
T818 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2497867742 Jul 05 04:28:37 PM PDT 24 Jul 05 04:28:50 PM PDT 24 54514173 ps
T819 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1506993085 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:07 PM PDT 24 95614401 ps
T820 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3729312531 Jul 05 04:27:26 PM PDT 24 Jul 05 04:27:28 PM PDT 24 435645158 ps
T821 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.577760890 Jul 05 04:27:45 PM PDT 24 Jul 05 04:27:50 PM PDT 24 765549008 ps
T822 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2535044628 Jul 05 04:27:45 PM PDT 24 Jul 05 04:27:50 PM PDT 24 52259269 ps
T823 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1352191328 Jul 05 04:28:17 PM PDT 24 Jul 05 04:28:30 PM PDT 24 15030144 ps
T96 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3173162351 Jul 05 04:27:36 PM PDT 24 Jul 05 04:27:39 PM PDT 24 25203072 ps
T97 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2391786069 Jul 05 04:27:53 PM PDT 24 Jul 05 04:28:00 PM PDT 24 340761667 ps
T93 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2812323993 Jul 05 04:27:39 PM PDT 24 Jul 05 04:27:44 PM PDT 24 996288609 ps
T824 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2737272817 Jul 05 04:27:58 PM PDT 24 Jul 05 04:28:03 PM PDT 24 334543349 ps
T825 /workspace/coverage/cover_reg_top/18.gpio_intr_test.665486965 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:57 PM PDT 24 13663624 ps
T826 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2845691355 Jul 05 04:27:46 PM PDT 24 Jul 05 04:27:51 PM PDT 24 25531011 ps
T827 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2921144846 Jul 05 04:28:17 PM PDT 24 Jul 05 04:28:31 PM PDT 24 109816167 ps
T828 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3331861796 Jul 05 04:27:37 PM PDT 24 Jul 05 04:27:40 PM PDT 24 427018916 ps
T829 /workspace/coverage/cover_reg_top/2.gpio_intr_test.638539749 Jul 05 04:27:40 PM PDT 24 Jul 05 04:27:44 PM PDT 24 45061061 ps
T830 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4284900694 Jul 05 04:28:03 PM PDT 24 Jul 05 04:28:11 PM PDT 24 99201487 ps
T831 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2143274022 Jul 05 04:27:52 PM PDT 24 Jul 05 04:27:57 PM PDT 24 26787370 ps
T112 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1418462292 Jul 05 04:27:57 PM PDT 24 Jul 05 04:28:03 PM PDT 24 349487748 ps
T832 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1665766502 Jul 05 04:27:46 PM PDT 24 Jul 05 04:27:51 PM PDT 24 11619857 ps
T833 /workspace/coverage/cover_reg_top/15.gpio_intr_test.795490045 Jul 05 04:27:59 PM PDT 24 Jul 05 04:28:05 PM PDT 24 53902623 ps
T834 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2901550567 Jul 05 04:27:49 PM PDT 24 Jul 05 04:27:54 PM PDT 24 124387927 ps
T835 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3133034489 Jul 05 04:27:49 PM PDT 24 Jul 05 04:27:54 PM PDT 24 48001016 ps
T98 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1613706321 Jul 05 04:27:47 PM PDT 24 Jul 05 04:27:52 PM PDT 24 44963888 ps
T836 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2600261731 Jul 05 04:27:42 PM PDT 24 Jul 05 04:27:46 PM PDT 24 56940834 ps
T837 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1312640810 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:12 PM PDT 24 18468804 ps
T838 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3702629228 Jul 05 04:28:04 PM PDT 24 Jul 05 04:28:12 PM PDT 24 23041406 ps
T839 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3594393905 Jul 05 04:18:29 PM PDT 24 Jul 05 04:18:31 PM PDT 24 47710745 ps
T840 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.361179110 Jul 05 04:22:42 PM PDT 24 Jul 05 04:22:44 PM PDT 24 46555746 ps
T841 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3833799842 Jul 05 04:20:40 PM PDT 24 Jul 05 04:20:42 PM PDT 24 80974805 ps
T842 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1637754765 Jul 05 04:22:40 PM PDT 24 Jul 05 04:22:43 PM PDT 24 92897116 ps
T843 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3785271752 Jul 05 04:22:17 PM PDT 24 Jul 05 04:22:18 PM PDT 24 23997817 ps
T844 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3351905428 Jul 05 04:22:31 PM PDT 24 Jul 05 04:22:33 PM PDT 24 52260336 ps
T845 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3512223984 Jul 05 04:22:14 PM PDT 24 Jul 05 04:22:16 PM PDT 24 186592420 ps
T846 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703702559 Jul 05 04:18:42 PM PDT 24 Jul 05 04:18:44 PM PDT 24 55092579 ps
T847 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1831517923 Jul 05 04:22:49 PM PDT 24 Jul 05 04:22:51 PM PDT 24 70701455 ps
T848 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4278906779 Jul 05 04:22:19 PM PDT 24 Jul 05 04:22:20 PM PDT 24 471216689 ps
T849 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2893276895 Jul 05 04:21:17 PM PDT 24 Jul 05 04:21:18 PM PDT 24 38371390 ps
T850 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172401188 Jul 05 04:22:06 PM PDT 24 Jul 05 04:22:08 PM PDT 24 186752601 ps
T851 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2667403895 Jul 05 04:19:09 PM PDT 24 Jul 05 04:19:10 PM PDT 24 50720860 ps
T852 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.35372903 Jul 05 04:18:27 PM PDT 24 Jul 05 04:18:29 PM PDT 24 356823876 ps
T853 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2335101030 Jul 05 04:22:41 PM PDT 24 Jul 05 04:22:43 PM PDT 24 204572592 ps
T854 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.231703855 Jul 05 04:22:02 PM PDT 24 Jul 05 04:22:04 PM PDT 24 38083717 ps
T855 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3453400577 Jul 05 04:22:46 PM PDT 24 Jul 05 04:22:47 PM PDT 24 66339562 ps
T856 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.680935383 Jul 05 04:22:27 PM PDT 24 Jul 05 04:22:29 PM PDT 24 167125381 ps
T857 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3789529239 Jul 05 04:21:06 PM PDT 24 Jul 05 04:21:08 PM PDT 24 80095292 ps
T858 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3169108542 Jul 05 04:20:15 PM PDT 24 Jul 05 04:20:18 PM PDT 24 254069149 ps
T859 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.150719531 Jul 05 04:23:18 PM PDT 24 Jul 05 04:23:20 PM PDT 24 428636006 ps
T860 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3586840426 Jul 05 04:22:47 PM PDT 24 Jul 05 04:22:49 PM PDT 24 128341929 ps
T861 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.348019866 Jul 05 04:22:31 PM PDT 24 Jul 05 04:22:33 PM PDT 24 45698078 ps
T862 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3668522789 Jul 05 04:23:03 PM PDT 24 Jul 05 04:23:04 PM PDT 24 675662298 ps
T863 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3697298657 Jul 05 04:22:47 PM PDT 24 Jul 05 04:22:49 PM PDT 24 23998615 ps
T864 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.992562874 Jul 05 04:22:35 PM PDT 24 Jul 05 04:22:38 PM PDT 24 77279944 ps
T865 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2111279563 Jul 05 04:19:13 PM PDT 24 Jul 05 04:19:15 PM PDT 24 110165637 ps
T866 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.771582104 Jul 05 04:22:36 PM PDT 24 Jul 05 04:22:39 PM PDT 24 145177369 ps
T867 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587736425 Jul 05 04:20:46 PM PDT 24 Jul 05 04:20:47 PM PDT 24 121746714 ps
T868 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3425353126 Jul 05 04:22:10 PM PDT 24 Jul 05 04:22:12 PM PDT 24 355508200 ps
T869 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3639511822 Jul 05 04:17:42 PM PDT 24 Jul 05 04:17:43 PM PDT 24 53756876 ps
T870 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4158996008 Jul 05 04:22:12 PM PDT 24 Jul 05 04:22:13 PM PDT 24 40498354 ps
T871 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2237087245 Jul 05 04:22:04 PM PDT 24 Jul 05 04:22:07 PM PDT 24 87992219 ps
T872 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.160816485 Jul 05 04:21:26 PM PDT 24 Jul 05 04:21:27 PM PDT 24 444504729 ps
T873 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.42118335 Jul 05 04:23:05 PM PDT 24 Jul 05 04:23:08 PM PDT 24 99326575 ps
T874 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.187693324 Jul 05 04:21:05 PM PDT 24 Jul 05 04:21:06 PM PDT 24 75216720 ps
T875 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4094174506 Jul 05 04:20:22 PM PDT 24 Jul 05 04:20:24 PM PDT 24 53397775 ps
T876 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.698104634 Jul 05 04:19:04 PM PDT 24 Jul 05 04:19:05 PM PDT 24 114707167 ps
T877 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1045691798 Jul 05 04:23:05 PM PDT 24 Jul 05 04:23:08 PM PDT 24 71236782 ps
T878 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.191381543 Jul 05 04:19:05 PM PDT 24 Jul 05 04:19:06 PM PDT 24 47907828 ps
T879 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1950194881 Jul 05 04:21:57 PM PDT 24 Jul 05 04:21:59 PM PDT 24 151912820 ps
T880 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.736849993 Jul 05 04:18:36 PM PDT 24 Jul 05 04:18:38 PM PDT 24 32515375 ps
T881 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3856784728 Jul 05 04:18:49 PM PDT 24 Jul 05 04:18:51 PM PDT 24 290078604 ps
T882 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.996647554 Jul 05 04:22:41 PM PDT 24 Jul 05 04:22:42 PM PDT 24 294848674 ps
T883 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3560041451 Jul 05 04:22:30 PM PDT 24 Jul 05 04:22:31 PM PDT 24 257073143 ps
T884 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1632828577 Jul 05 04:18:29 PM PDT 24 Jul 05 04:18:31 PM PDT 24 122993576 ps
T885 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1938663576 Jul 05 04:19:15 PM PDT 24 Jul 05 04:19:16 PM PDT 24 383745970 ps
T886 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2457683163 Jul 05 04:18:58 PM PDT 24 Jul 05 04:18:59 PM PDT 24 33373187 ps
T887 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2858716690 Jul 05 04:21:10 PM PDT 24 Jul 05 04:21:12 PM PDT 24 127363720 ps
T888 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3810093032 Jul 05 04:22:02 PM PDT 24 Jul 05 04:22:04 PM PDT 24 44546759 ps
T889 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926653380 Jul 05 04:20:55 PM PDT 24 Jul 05 04:20:57 PM PDT 24 51632262 ps
T890 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3624302893 Jul 05 04:20:06 PM PDT 24 Jul 05 04:20:07 PM PDT 24 28661165 ps
T891 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618792021 Jul 05 04:21:04 PM PDT 24 Jul 05 04:21:06 PM PDT 24 107072114 ps
T892 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885892045 Jul 05 04:22:27 PM PDT 24 Jul 05 04:22:29 PM PDT 24 85832762 ps
T893 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1844282991 Jul 05 04:22:18 PM PDT 24 Jul 05 04:22:20 PM PDT 24 26742438 ps
T894 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.177171264 Jul 05 04:20:40 PM PDT 24 Jul 05 04:20:42 PM PDT 24 48777489 ps
T895 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1573726120 Jul 05 04:22:20 PM PDT 24 Jul 05 04:22:22 PM PDT 24 49213756 ps
T896 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2911447371 Jul 05 04:21:04 PM PDT 24 Jul 05 04:21:06 PM PDT 24 83798700 ps
T897 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2016608331 Jul 05 04:23:13 PM PDT 24 Jul 05 04:23:21 PM PDT 24 37815909 ps
T898 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1677778720 Jul 05 04:22:47 PM PDT 24 Jul 05 04:22:48 PM PDT 24 125248642 ps
T899 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3193288362 Jul 05 04:22:34 PM PDT 24 Jul 05 04:22:35 PM PDT 24 23285607 ps
T900 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1555103389 Jul 05 04:20:19 PM PDT 24 Jul 05 04:20:23 PM PDT 24 68453053 ps
T901 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2699431455 Jul 05 04:22:25 PM PDT 24 Jul 05 04:22:27 PM PDT 24 35761297 ps
T902 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744169316 Jul 05 04:22:14 PM PDT 24 Jul 05 04:22:16 PM PDT 24 160822462 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2903163844 Jul 05 04:23:08 PM PDT 24 Jul 05 04:23:10 PM PDT 24 75907292 ps
T904 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3544904451 Jul 05 04:23:02 PM PDT 24 Jul 05 04:23:04 PM PDT 24 103421412 ps
T905 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1326896306 Jul 05 04:22:14 PM PDT 24 Jul 05 04:22:16 PM PDT 24 73562996 ps
T906 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1349313702 Jul 05 04:22:40 PM PDT 24 Jul 05 04:22:42 PM PDT 24 284164713 ps
T907 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3507029714 Jul 05 04:22:02 PM PDT 24 Jul 05 04:22:04 PM PDT 24 719510968 ps
T908 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1036608343 Jul 05 04:22:13 PM PDT 24 Jul 05 04:22:15 PM PDT 24 30411637 ps
T909 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1362651212 Jul 05 04:19:15 PM PDT 24 Jul 05 04:19:16 PM PDT 24 115388921 ps
T910 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.478714766 Jul 05 04:22:28 PM PDT 24 Jul 05 04:22:31 PM PDT 24 171568546 ps
T911 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2129042078 Jul 05 04:22:15 PM PDT 24 Jul 05 04:22:17 PM PDT 24 246662513 ps
T912 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4268101786 Jul 05 04:20:06 PM PDT 24 Jul 05 04:20:08 PM PDT 24 300585179 ps
T913 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4257957842 Jul 05 04:22:40 PM PDT 24 Jul 05 04:22:42 PM PDT 24 392559977 ps
T914 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1594180025 Jul 05 04:22:43 PM PDT 24 Jul 05 04:22:44 PM PDT 24 97239307 ps
T915 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2552310678 Jul 05 04:22:04 PM PDT 24 Jul 05 04:22:07 PM PDT 24 61246469 ps
T916 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3279527307 Jul 05 04:22:49 PM PDT 24 Jul 05 04:22:51 PM PDT 24 186814569 ps
T917 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884880604 Jul 05 04:22:12 PM PDT 24 Jul 05 04:22:14 PM PDT 24 48522736 ps
T918 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2403207609 Jul 05 04:22:02 PM PDT 24 Jul 05 04:22:04 PM PDT 24 56453433 ps
T919 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3112907537 Jul 05 04:19:22 PM PDT 24 Jul 05 04:19:23 PM PDT 24 147580325 ps
T920 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623880753 Jul 05 04:22:28 PM PDT 24 Jul 05 04:22:30 PM PDT 24 573862573 ps
T921 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2302222384 Jul 05 04:22:28 PM PDT 24 Jul 05 04:22:30 PM PDT 24 212470457 ps
T922 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.462950662 Jul 05 04:20:38 PM PDT 24 Jul 05 04:20:39 PM PDT 24 76121843 ps
T923 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4162855355 Jul 05 04:22:33 PM PDT 24 Jul 05 04:22:35 PM PDT 24 208168525 ps
T924 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1146947369 Jul 05 04:23:02 PM PDT 24 Jul 05 04:23:04 PM PDT 24 122935517 ps
T925 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1255227619 Jul 05 04:23:08 PM PDT 24 Jul 05 04:23:10 PM PDT 24 176896161 ps
T926 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3657390799 Jul 05 04:22:27 PM PDT 24 Jul 05 04:22:28 PM PDT 24 139358087 ps
T927 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.705040634 Jul 05 04:20:19 PM PDT 24 Jul 05 04:20:23 PM PDT 24 37414900 ps
T928 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3844265973 Jul 05 04:22:16 PM PDT 24 Jul 05 04:22:18 PM PDT 24 188002119 ps
T929 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2961920227 Jul 05 04:19:48 PM PDT 24 Jul 05 04:19:50 PM PDT 24 190925468 ps
T930 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3033574575 Jul 05 04:23:18 PM PDT 24 Jul 05 04:23:19 PM PDT 24 60521058 ps
T931 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2758304411 Jul 05 04:22:10 PM PDT 24 Jul 05 04:22:12 PM PDT 24 67807577 ps
T932 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.306032772 Jul 05 04:17:34 PM PDT 24 Jul 05 04:17:35 PM PDT 24 36778907 ps
T933 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2009489462 Jul 05 04:22:03 PM PDT 24 Jul 05 04:22:06 PM PDT 24 46255342 ps
T934 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4211655190 Jul 05 04:21:47 PM PDT 24 Jul 05 04:21:49 PM PDT 24 552390760 ps
T935 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23490032 Jul 05 04:20:08 PM PDT 24 Jul 05 04:20:10 PM PDT 24 240623675 ps
T936 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2402643461 Jul 05 04:22:23 PM PDT 24 Jul 05 04:22:25 PM PDT 24 57684709 ps
T937 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3952611829 Jul 05 04:22:18 PM PDT 24 Jul 05 04:22:20 PM PDT 24 814324942 ps
T938 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3974545626 Jul 05 04:20:37 PM PDT 24 Jul 05 04:20:39 PM PDT 24 1563669119 ps

Test location /workspace/coverage/default/46.gpio_stress_all.1288518577
Short name T40
Test name
Test status
Simulation time 18120517952 ps
CPU time 65.04 seconds
Started Jul 05 04:37:16 PM PDT 24
Finished Jul 05 04:38:27 PM PDT 24
Peak memory 198716 kb
Host smart-36f38e65-4d2f-480b-9a7d-e1dba15af0e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288518577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1288518577
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.783942833
Short name T32
Test name
Test status
Simulation time 160711227 ps
CPU time 1.3 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:45 PM PDT 24
Peak memory 198792 kb
Host smart-e79f7efe-a9a5-4df6-9488-b3fabb7febf1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783942833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.783942833
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.4289781324
Short name T42
Test name
Test status
Simulation time 20249456601 ps
CPU time 643.28 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:47:06 PM PDT 24
Peak memory 198872 kb
Host smart-7926a6a4-8610-4da6-949f-ab465c5def7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4289781324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.4289781324
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3991301284
Short name T48
Test name
Test status
Simulation time 65543459 ps
CPU time 0.89 seconds
Started Jul 05 04:35:39 PM PDT 24
Finished Jul 05 04:35:40 PM PDT 24
Peak memory 214288 kb
Host smart-d34b6f36-cb60-4125-9af4-86a1b4ab690c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991301284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3991301284
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1508689081
Short name T6
Test name
Test status
Simulation time 26683297666 ps
CPU time 68.65 seconds
Started Jul 05 04:35:33 PM PDT 24
Finished Jul 05 04:36:43 PM PDT 24
Peak memory 198812 kb
Host smart-191a2a61-18b8-426f-b5d3-68a92e0da7f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508689081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1508689081
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3953836821
Short name T771
Test name
Test status
Simulation time 180936068 ps
CPU time 1.36 seconds
Started Jul 05 04:27:34 PM PDT 24
Finished Jul 05 04:27:37 PM PDT 24
Peak memory 198572 kb
Host smart-f10b7d65-9ed0-4639-9a33-e6a1952c3463
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953836821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3953836821
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3478871492
Short name T27
Test name
Test status
Simulation time 41763907 ps
CPU time 0.56 seconds
Started Jul 05 04:35:38 PM PDT 24
Finished Jul 05 04:35:40 PM PDT 24
Peak memory 194884 kb
Host smart-389fd231-e7f4-4692-abc1-b07d6372a771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478871492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3478871492
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2480063162
Short name T89
Test name
Test status
Simulation time 36470108 ps
CPU time 0.85 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:01 PM PDT 24
Peak memory 196252 kb
Host smart-0164bd57-54c8-4a9a-92ee-72392a4bfeaa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480063162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2480063162
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1676061257
Short name T82
Test name
Test status
Simulation time 58247145 ps
CPU time 0.65 seconds
Started Jul 05 04:27:25 PM PDT 24
Finished Jul 05 04:27:27 PM PDT 24
Peak memory 196148 kb
Host smart-48b25660-39f6-4c7b-a7d2-9378c77094db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676061257 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1676061257
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2207583825
Short name T792
Test name
Test status
Simulation time 320754439 ps
CPU time 1.38 seconds
Started Jul 05 04:28:01 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 198584 kb
Host smart-5cd08386-c61b-4617-af12-f1e935aea008
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207583825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2207583825
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1380792274
Short name T44
Test name
Test status
Simulation time 95152574 ps
CPU time 1.14 seconds
Started Jul 05 04:27:51 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 198584 kb
Host smart-3f74305e-0edb-4c5b-af9d-745b0aab03ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380792274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1380792274
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1557164755
Short name T733
Test name
Test status
Simulation time 30927521 ps
CPU time 0.87 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:02 PM PDT 24
Peak memory 196728 kb
Host smart-1939ae3c-f97c-4c7e-9fc8-26732e6acd60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557164755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1557164755
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2812323993
Short name T93
Test name
Test status
Simulation time 996288609 ps
CPU time 2.51 seconds
Started Jul 05 04:27:39 PM PDT 24
Finished Jul 05 04:27:44 PM PDT 24
Peak memory 197612 kb
Host smart-8e357ec2-e040-44e2-af2f-f17341c635a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812323993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2812323993
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3237872497
Short name T91
Test name
Test status
Simulation time 14875996 ps
CPU time 0.64 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:00 PM PDT 24
Peak memory 195524 kb
Host smart-8542b8a4-3564-4efa-9ac8-0f0b7276d369
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237872497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3237872497
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1989226525
Short name T809
Test name
Test status
Simulation time 39242509 ps
CPU time 0.99 seconds
Started Jul 05 04:27:35 PM PDT 24
Finished Jul 05 04:27:38 PM PDT 24
Peak memory 198400 kb
Host smart-12da9af7-9f3a-4b8b-929b-93055883cb4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989226525 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1989226525
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.265599336
Short name T108
Test name
Test status
Simulation time 16267741 ps
CPU time 0.63 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:11 PM PDT 24
Peak memory 196168 kb
Host smart-35c8c7ab-6322-402d-b2b1-89840b559408
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265599336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.265599336
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2606551713
Short name T725
Test name
Test status
Simulation time 15111809 ps
CPU time 0.61 seconds
Started Jul 05 04:27:39 PM PDT 24
Finished Jul 05 04:27:42 PM PDT 24
Peak memory 194192 kb
Host smart-699a1c34-3bcc-425d-8c7a-db9d11e91993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606551713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2606551713
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1637720302
Short name T751
Test name
Test status
Simulation time 24565622 ps
CPU time 0.69 seconds
Started Jul 05 04:27:33 PM PDT 24
Finished Jul 05 04:27:35 PM PDT 24
Peak memory 196000 kb
Host smart-2e627c68-c777-42d9-9250-6ef567813957
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637720302 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1637720302
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.181845178
Short name T766
Test name
Test status
Simulation time 131114132 ps
CPU time 1.2 seconds
Started Jul 05 04:27:27 PM PDT 24
Finished Jul 05 04:27:29 PM PDT 24
Peak memory 198592 kb
Host smart-265d22e4-7d3e-4134-a5e8-c12fac52bd02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181845178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.181845178
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.765538410
Short name T111
Test name
Test status
Simulation time 83458348 ps
CPU time 1.11 seconds
Started Jul 05 04:27:36 PM PDT 24
Finished Jul 05 04:27:39 PM PDT 24
Peak memory 198596 kb
Host smart-9b9d7707-4b04-44af-9c75-38bc8e60884e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765538410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.765538410
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.329021028
Short name T90
Test name
Test status
Simulation time 138757226 ps
CPU time 1.49 seconds
Started Jul 05 04:27:34 PM PDT 24
Finished Jul 05 04:27:38 PM PDT 24
Peak memory 198544 kb
Host smart-a89cf651-658f-4eda-a211-9fde938ef2bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329021028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.329021028
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2535044628
Short name T822
Test name
Test status
Simulation time 52259269 ps
CPU time 0.68 seconds
Started Jul 05 04:27:45 PM PDT 24
Finished Jul 05 04:27:50 PM PDT 24
Peak memory 196208 kb
Host smart-bb1c6a11-5ee4-4b1a-9961-c937b0a06fd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535044628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2535044628
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1996904922
Short name T743
Test name
Test status
Simulation time 34486582 ps
CPU time 1.62 seconds
Started Jul 05 04:27:51 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 198548 kb
Host smart-75d2b991-6555-49c0-9857-5a1a882716da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996904922 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1996904922
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.4285322847
Short name T774
Test name
Test status
Simulation time 32668972 ps
CPU time 0.62 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:46 PM PDT 24
Peak memory 195308 kb
Host smart-d0d9c24a-35da-4905-ab64-5903d42c1b73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285322847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.4285322847
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2431438715
Short name T806
Test name
Test status
Simulation time 11193989 ps
CPU time 0.56 seconds
Started Jul 05 04:27:39 PM PDT 24
Finished Jul 05 04:27:42 PM PDT 24
Peak memory 195244 kb
Host smart-546a7565-21b9-4097-b04f-8096f13b2c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431438715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2431438715
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.419877111
Short name T808
Test name
Test status
Simulation time 367109127 ps
CPU time 2.08 seconds
Started Jul 05 04:27:37 PM PDT 24
Finished Jul 05 04:27:41 PM PDT 24
Peak memory 198592 kb
Host smart-288656d6-3645-4d19-a3a6-63069e09b324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419877111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.419877111
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1876544546
Short name T816
Test name
Test status
Simulation time 137038625 ps
CPU time 1.12 seconds
Started Jul 05 04:27:35 PM PDT 24
Finished Jul 05 04:27:38 PM PDT 24
Peak memory 198588 kb
Host smart-6be5ee11-c105-4c90-ac0e-aa8e6b78e81c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876544546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1876544546
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2600261731
Short name T836
Test name
Test status
Simulation time 56940834 ps
CPU time 0.74 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:46 PM PDT 24
Peak memory 198452 kb
Host smart-c8039acc-26a7-4828-911e-739f32df8a65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600261731 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2600261731
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1776240610
Short name T109
Test name
Test status
Simulation time 121135676 ps
CPU time 0.64 seconds
Started Jul 05 04:27:49 PM PDT 24
Finished Jul 05 04:27:54 PM PDT 24
Peak memory 195352 kb
Host smart-376c9484-fc5f-427e-8d76-eec33b6ae41c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776240610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1776240610
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3133034489
Short name T835
Test name
Test status
Simulation time 48001016 ps
CPU time 0.57 seconds
Started Jul 05 04:27:49 PM PDT 24
Finished Jul 05 04:27:54 PM PDT 24
Peak memory 194848 kb
Host smart-c2dddada-7257-4d6a-a16b-b396262fac29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133034489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3133034489
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3146630906
Short name T813
Test name
Test status
Simulation time 121809765 ps
CPU time 0.75 seconds
Started Jul 05 04:28:04 PM PDT 24
Finished Jul 05 04:28:13 PM PDT 24
Peak memory 196704 kb
Host smart-440614ad-3f00-401e-8110-ad45f4dbbe53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146630906 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3146630906
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3579510252
Short name T788
Test name
Test status
Simulation time 96332389 ps
CPU time 1.73 seconds
Started Jul 05 04:28:04 PM PDT 24
Finished Jul 05 04:28:14 PM PDT 24
Peak memory 198604 kb
Host smart-3d13f02c-3886-40a2-b305-ec11fd74dca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579510252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3579510252
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2570993907
Short name T57
Test name
Test status
Simulation time 381972185 ps
CPU time 1.42 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:01 PM PDT 24
Peak memory 198520 kb
Host smart-4d624296-137b-487a-95d1-bb828e31a2a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570993907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2570993907
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3535939606
Short name T787
Test name
Test status
Simulation time 38260634 ps
CPU time 0.92 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 198484 kb
Host smart-7bf4bc63-ac32-4c7c-87bd-48834a4bfba0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535939606 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3535939606
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1344409067
Short name T79
Test name
Test status
Simulation time 14711727 ps
CPU time 0.63 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:02 PM PDT 24
Peak memory 195480 kb
Host smart-fc3e7ea5-bdc4-46a1-8bf7-529fad9ea2d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344409067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1344409067
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.185601295
Short name T730
Test name
Test status
Simulation time 49311528 ps
CPU time 0.59 seconds
Started Jul 05 04:27:53 PM PDT 24
Finished Jul 05 04:27:58 PM PDT 24
Peak memory 194900 kb
Host smart-e74cbf22-f94d-4f96-ba53-42832cee22df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185601295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.185601295
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.429375053
Short name T84
Test name
Test status
Simulation time 32990819 ps
CPU time 0.78 seconds
Started Jul 05 04:27:51 PM PDT 24
Finished Jul 05 04:27:56 PM PDT 24
Peak memory 196940 kb
Host smart-c26ec411-919d-4b56-95b8-ab534f42b4b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429375053 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.429375053
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2921144846
Short name T827
Test name
Test status
Simulation time 109816167 ps
CPU time 1.66 seconds
Started Jul 05 04:28:17 PM PDT 24
Finished Jul 05 04:28:31 PM PDT 24
Peak memory 198624 kb
Host smart-f0e9d485-21a7-492b-87a8-84cc57e41b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921144846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2921144846
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2261087752
Short name T110
Test name
Test status
Simulation time 120558922 ps
CPU time 1.31 seconds
Started Jul 05 04:27:58 PM PDT 24
Finished Jul 05 04:28:04 PM PDT 24
Peak memory 198568 kb
Host smart-166c1e9c-c50e-4920-af6b-23d364bbf249
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261087752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2261087752
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3708306807
Short name T796
Test name
Test status
Simulation time 19735986 ps
CPU time 0.72 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:46 PM PDT 24
Peak memory 198432 kb
Host smart-0909ee46-65df-41ca-870f-90e1bc39d36e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708306807 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3708306807
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2502881499
Short name T81
Test name
Test status
Simulation time 12854947 ps
CPU time 0.59 seconds
Started Jul 05 04:27:44 PM PDT 24
Finished Jul 05 04:27:49 PM PDT 24
Peak memory 195252 kb
Host smart-7349b0b5-ef1d-47dd-bd15-3a906aa7f6b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502881499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2502881499
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3799479592
Short name T814
Test name
Test status
Simulation time 14969350 ps
CPU time 0.59 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:20 PM PDT 24
Peak memory 194824 kb
Host smart-657a43dc-3b08-4985-a681-1c790d194309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799479592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3799479592
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1441909340
Short name T800
Test name
Test status
Simulation time 57106226 ps
CPU time 0.65 seconds
Started Jul 05 04:27:51 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 196216 kb
Host smart-e72ecbfc-4ddf-46e2-9e76-183a25446874
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441909340 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1441909340
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.4284900694
Short name T830
Test name
Test status
Simulation time 99201487 ps
CPU time 1.76 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:11 PM PDT 24
Peak memory 198580 kb
Host smart-69f90db7-9d1d-497f-af16-32fe1bda714a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284900694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.4284900694
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.12008426
Short name T784
Test name
Test status
Simulation time 45119378 ps
CPU time 0.78 seconds
Started Jul 05 04:28:00 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 198460 kb
Host smart-34e8cc07-8e8e-45b2-85de-2ddfaf16a4a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12008426 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.12008426
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2845691355
Short name T826
Test name
Test status
Simulation time 25531011 ps
CPU time 0.62 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 195420 kb
Host smart-e42a70ff-8664-498f-80a2-baf6d9a7e46e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845691355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2845691355
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1630336833
Short name T726
Test name
Test status
Simulation time 23102053 ps
CPU time 0.59 seconds
Started Jul 05 04:28:01 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 194232 kb
Host smart-30616a0c-85f2-4f3c-812d-33964ca6dd30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630336833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1630336833
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1745246539
Short name T752
Test name
Test status
Simulation time 90074601 ps
CPU time 0.63 seconds
Started Jul 05 04:27:50 PM PDT 24
Finished Jul 05 04:27:55 PM PDT 24
Peak memory 195748 kb
Host smart-9c0eb440-4345-4846-b491-215ab9bce7f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745246539 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1745246539
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.79356836
Short name T724
Test name
Test status
Simulation time 62454829 ps
CPU time 1.66 seconds
Started Jul 05 04:28:05 PM PDT 24
Finished Jul 05 04:28:14 PM PDT 24
Peak memory 198516 kb
Host smart-aa0abd1e-2d85-4f32-9b7c-9be631f5d43a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79356836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.79356836
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1418462292
Short name T112
Test name
Test status
Simulation time 349487748 ps
CPU time 1.34 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:03 PM PDT 24
Peak memory 198576 kb
Host smart-001c0adb-8490-4e94-9459-02bbd1ae7057
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418462292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1418462292
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2117504329
Short name T723
Test name
Test status
Simulation time 40215784 ps
CPU time 0.85 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:02 PM PDT 24
Peak memory 198896 kb
Host smart-4a84bfe3-4f8f-489e-a805-c867c5ac51b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117504329 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2117504329
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4253448802
Short name T807
Test name
Test status
Simulation time 24213965 ps
CPU time 0.57 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:05 PM PDT 24
Peak memory 194472 kb
Host smart-b820f48d-b1bf-491d-be01-1dc23f81391e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253448802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4253448802
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.397773618
Short name T741
Test name
Test status
Simulation time 34379534 ps
CPU time 0.55 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:11 PM PDT 24
Peak memory 194156 kb
Host smart-fdef9f46-c666-4f52-9a67-7816739dde72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397773618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.397773618
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3331861796
Short name T828
Test name
Test status
Simulation time 427018916 ps
CPU time 0.83 seconds
Started Jul 05 04:27:37 PM PDT 24
Finished Jul 05 04:27:40 PM PDT 24
Peak memory 196892 kb
Host smart-18e095fb-3d0c-4d4b-b668-4f42ed67d0d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331861796 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3331861796
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3801729841
Short name T762
Test name
Test status
Simulation time 389826619 ps
CPU time 3.36 seconds
Started Jul 05 04:27:49 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 198556 kb
Host smart-f5ac2604-93ed-42ef-8a5c-7288bca8fc64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801729841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3801729841
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.577760890
Short name T821
Test name
Test status
Simulation time 765549008 ps
CPU time 1.11 seconds
Started Jul 05 04:27:45 PM PDT 24
Finished Jul 05 04:27:50 PM PDT 24
Peak memory 198596 kb
Host smart-47d0ab5c-cb44-435c-b862-5b0409f1abde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577760890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.577760890
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1457901420
Short name T781
Test name
Test status
Simulation time 57757483 ps
CPU time 1.05 seconds
Started Jul 05 04:27:55 PM PDT 24
Finished Jul 05 04:28:00 PM PDT 24
Peak memory 198468 kb
Host smart-ed3afa5e-d493-4601-9e59-2bd85ce1cbaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457901420 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1457901420
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.937106158
Short name T764
Test name
Test status
Simulation time 42753668 ps
CPU time 0.6 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 195240 kb
Host smart-0907da33-5598-4200-9d7e-d6c0b847db87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937106158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.937106158
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.795490045
Short name T833
Test name
Test status
Simulation time 53902623 ps
CPU time 0.6 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:05 PM PDT 24
Peak memory 194156 kb
Host smart-4270599b-4308-4f85-a478-f6ccbe1c2fe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795490045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.795490045
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1475566826
Short name T104
Test name
Test status
Simulation time 62224580 ps
CPU time 0.85 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 196820 kb
Host smart-e650b6ee-1695-4aff-927b-6dda29a54852
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475566826 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1475566826
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3376537334
Short name T734
Test name
Test status
Simulation time 208082842 ps
CPU time 1.44 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:01 PM PDT 24
Peak memory 198560 kb
Host smart-6d188658-3c27-43dc-a9df-d40c359c517e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376537334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3376537334
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1504401313
Short name T777
Test name
Test status
Simulation time 332798188 ps
CPU time 1.08 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:05 PM PDT 24
Peak memory 198616 kb
Host smart-977d9b23-9105-423c-a101-3afdea2473d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504401313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1504401313
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2585247135
Short name T749
Test name
Test status
Simulation time 103547150 ps
CPU time 1.24 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:10 PM PDT 24
Peak memory 198680 kb
Host smart-b384d67b-ba97-4b27-a3c0-50670fa7b5da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585247135 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2585247135
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1613706321
Short name T98
Test name
Test status
Simulation time 44963888 ps
CPU time 0.6 seconds
Started Jul 05 04:27:47 PM PDT 24
Finished Jul 05 04:27:52 PM PDT 24
Peak memory 195004 kb
Host smart-e3a576fd-287d-4fb7-bd82-860c2c16a8e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613706321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1613706321
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3860434460
Short name T719
Test name
Test status
Simulation time 11303428 ps
CPU time 0.6 seconds
Started Jul 05 04:28:14 PM PDT 24
Finished Jul 05 04:28:28 PM PDT 24
Peak memory 194892 kb
Host smart-6180ea90-e5c9-4985-bab5-d414c245e4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860434460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3860434460
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2613954123
Short name T815
Test name
Test status
Simulation time 65644050 ps
CPU time 0.76 seconds
Started Jul 05 04:28:00 PM PDT 24
Finished Jul 05 04:28:07 PM PDT 24
Peak memory 196504 kb
Host smart-0fffbb22-2575-4e60-a318-420b09395521
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613954123 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2613954123
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2380581227
Short name T768
Test name
Test status
Simulation time 161217169 ps
CPU time 2.56 seconds
Started Jul 05 04:28:07 PM PDT 24
Finished Jul 05 04:28:19 PM PDT 24
Peak memory 198628 kb
Host smart-85a83608-9700-4871-b8e4-cc7c10d05fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380581227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2380581227
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.970113745
Short name T46
Test name
Test status
Simulation time 123766822 ps
CPU time 1.42 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:17 PM PDT 24
Peak memory 198396 kb
Host smart-8ce53c2d-6242-4f27-87f5-2c5abbf15db2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970113745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.970113745
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.494036276
Short name T721
Test name
Test status
Simulation time 19069824 ps
CPU time 0.67 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:05 PM PDT 24
Peak memory 197784 kb
Host smart-f8874929-87c8-460e-aebe-805f140d9132
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494036276 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.494036276
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.511676291
Short name T88
Test name
Test status
Simulation time 37134700 ps
CPU time 0.58 seconds
Started Jul 05 04:28:29 PM PDT 24
Finished Jul 05 04:28:42 PM PDT 24
Peak memory 194128 kb
Host smart-2ed4ad43-e678-404b-9f91-012d748e2896
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511676291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.511676291
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3702629228
Short name T838
Test name
Test status
Simulation time 23041406 ps
CPU time 0.6 seconds
Started Jul 05 04:28:04 PM PDT 24
Finished Jul 05 04:28:12 PM PDT 24
Peak memory 194168 kb
Host smart-4ace2fc8-4d43-4732-a23b-8792d48f6b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702629228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3702629228
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.125454105
Short name T100
Test name
Test status
Simulation time 34734803 ps
CPU time 0.82 seconds
Started Jul 05 04:28:00 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 196884 kb
Host smart-9734eee7-ff81-4a68-9dd9-4698486c3b95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125454105 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.125454105
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2037366077
Short name T716
Test name
Test status
Simulation time 64912130 ps
CPU time 1.03 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 198412 kb
Host smart-06a6d802-fb2b-4f6c-bded-15ea92d434cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037366077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2037366077
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2901550567
Short name T834
Test name
Test status
Simulation time 124387927 ps
CPU time 1.03 seconds
Started Jul 05 04:27:49 PM PDT 24
Finished Jul 05 04:27:54 PM PDT 24
Peak memory 198536 kb
Host smart-f9b294be-2eaa-4485-8bab-ef4df381cf7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901550567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2901550567
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3260016322
Short name T789
Test name
Test status
Simulation time 22315038 ps
CPU time 0.75 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:00 PM PDT 24
Peak memory 198424 kb
Host smart-6777425a-ea47-45fa-a55f-ee7b663ad9ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260016322 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3260016322
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.198528622
Short name T83
Test name
Test status
Simulation time 11851666 ps
CPU time 0.58 seconds
Started Jul 05 04:28:04 PM PDT 24
Finished Jul 05 04:28:12 PM PDT 24
Peak memory 193744 kb
Host smart-ebd4aad3-60eb-4026-89df-f2f53438e5c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198528622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.198528622
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.665486965
Short name T825
Test name
Test status
Simulation time 13663624 ps
CPU time 0.58 seconds
Started Jul 05 04:27:52 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 194168 kb
Host smart-b5d610df-1470-4da3-914b-3b6c1a33b574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665486965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.665486965
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2441464830
Short name T803
Test name
Test status
Simulation time 18130854 ps
CPU time 0.64 seconds
Started Jul 05 04:28:15 PM PDT 24
Finished Jul 05 04:28:28 PM PDT 24
Peak memory 195164 kb
Host smart-9c9bddbc-52e2-4114-bae5-8bdc100edd40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441464830 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2441464830
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3254571827
Short name T794
Test name
Test status
Simulation time 1813606486 ps
CPU time 2.87 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:49 PM PDT 24
Peak memory 198624 kb
Host smart-2e4be761-bc33-4e62-bc9b-c3744843ef5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254571827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3254571827
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2737272817
Short name T824
Test name
Test status
Simulation time 334543349 ps
CPU time 1.05 seconds
Started Jul 05 04:27:58 PM PDT 24
Finished Jul 05 04:28:03 PM PDT 24
Peak memory 197488 kb
Host smart-a05b7b96-fd68-46ac-b1fe-c9ddc04a5dc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737272817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2737272817
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1891930761
Short name T797
Test name
Test status
Simulation time 43778551 ps
CPU time 0.79 seconds
Started Jul 05 04:27:58 PM PDT 24
Finished Jul 05 04:28:03 PM PDT 24
Peak memory 198428 kb
Host smart-b248ccf3-b953-4cf9-ade3-e06510e68f71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891930761 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1891930761
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.267076974
Short name T799
Test name
Test status
Simulation time 28079670 ps
CPU time 0.62 seconds
Started Jul 05 04:27:53 PM PDT 24
Finished Jul 05 04:27:58 PM PDT 24
Peak memory 195940 kb
Host smart-cde6317e-e4a0-48bc-98b0-e5aca6550455
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267076974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.267076974
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.770786260
Short name T805
Test name
Test status
Simulation time 37344536 ps
CPU time 0.59 seconds
Started Jul 05 04:28:01 PM PDT 24
Finished Jul 05 04:28:07 PM PDT 24
Peak memory 194828 kb
Host smart-83f8ffeb-71b1-4a63-b0f5-c09459218527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770786260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.770786260
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.798747533
Short name T778
Test name
Test status
Simulation time 17824772 ps
CPU time 0.73 seconds
Started Jul 05 04:28:01 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 197400 kb
Host smart-736ebbeb-8b1e-431b-9c17-8767a92f8c38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798747533 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.798747533
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3899661964
Short name T740
Test name
Test status
Simulation time 130400674 ps
CPU time 1.52 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:03 PM PDT 24
Peak memory 198516 kb
Host smart-5e891d3b-0deb-40fd-ae34-0ddd3ebe8ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899661964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3899661964
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3118579625
Short name T55
Test name
Test status
Simulation time 57830349 ps
CPU time 0.86 seconds
Started Jul 05 04:27:34 PM PDT 24
Finished Jul 05 04:27:37 PM PDT 24
Peak memory 197792 kb
Host smart-7fde212a-c0a2-4af2-aeaf-e61df7fdd81e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118579625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3118579625
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2080862969
Short name T87
Test name
Test status
Simulation time 162791991 ps
CPU time 0.89 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:01 PM PDT 24
Peak memory 197100 kb
Host smart-b3da091b-fc15-4db2-bb29-7de25604b6d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080862969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2080862969
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2391786069
Short name T97
Test name
Test status
Simulation time 340761667 ps
CPU time 3.43 seconds
Started Jul 05 04:27:53 PM PDT 24
Finished Jul 05 04:28:00 PM PDT 24
Peak memory 198512 kb
Host smart-67d203b3-7152-4876-9d4b-0a3eca9d6f98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391786069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2391786069
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.2330480223
Short name T94
Test name
Test status
Simulation time 12436860 ps
CPU time 0.59 seconds
Started Jul 05 04:27:37 PM PDT 24
Finished Jul 05 04:27:40 PM PDT 24
Peak memory 195840 kb
Host smart-293440f8-74c6-4a57-869d-a65a244ab9f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330480223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.2330480223
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1432150283
Short name T759
Test name
Test status
Simulation time 123956864 ps
CPU time 0.87 seconds
Started Jul 05 04:27:54 PM PDT 24
Finished Jul 05 04:27:59 PM PDT 24
Peak memory 198456 kb
Host smart-242bd55f-1087-45ac-8232-1b9fc9c9e83a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432150283 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1432150283
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.585399263
Short name T755
Test name
Test status
Simulation time 12592175 ps
CPU time 0.58 seconds
Started Jul 05 04:27:51 PM PDT 24
Finished Jul 05 04:27:56 PM PDT 24
Peak memory 194960 kb
Host smart-e4501992-6c8b-483a-9577-30845bea4b93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585399263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.585399263
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.638539749
Short name T829
Test name
Test status
Simulation time 45061061 ps
CPU time 0.61 seconds
Started Jul 05 04:27:40 PM PDT 24
Finished Jul 05 04:27:44 PM PDT 24
Peak memory 194316 kb
Host smart-3d01083f-4e04-45a0-b04b-c458165b13b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638539749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.638539749
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2405221353
Short name T763
Test name
Test status
Simulation time 21381164 ps
CPU time 0.64 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:46 PM PDT 24
Peak memory 194808 kb
Host smart-4e57e575-dab9-416d-a0f0-63877adf48c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405221353 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2405221353
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.72933580
Short name T728
Test name
Test status
Simulation time 167799133 ps
CPU time 2.68 seconds
Started Jul 05 04:27:31 PM PDT 24
Finished Jul 05 04:27:35 PM PDT 24
Peak memory 198548 kb
Host smart-5fb95b3f-deae-48bb-a813-0ffd1cc5e83c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72933580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.72933580
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3729312531
Short name T820
Test name
Test status
Simulation time 435645158 ps
CPU time 0.83 seconds
Started Jul 05 04:27:26 PM PDT 24
Finished Jul 05 04:27:28 PM PDT 24
Peak memory 197752 kb
Host smart-716957a1-cf3e-4198-824c-a29bcfb9b590
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729312531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3729312531
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1510244803
Short name T765
Test name
Test status
Simulation time 87101692 ps
CPU time 0.57 seconds
Started Jul 05 04:27:55 PM PDT 24
Finished Jul 05 04:28:00 PM PDT 24
Peak memory 194232 kb
Host smart-55a424ee-ed30-4c56-a390-f5f38d13b1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510244803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1510244803
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3115232035
Short name T810
Test name
Test status
Simulation time 81035714 ps
CPU time 0.57 seconds
Started Jul 05 04:28:01 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 194196 kb
Host smart-b7b78941-0834-41d2-b662-496d645e4abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115232035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3115232035
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.30938605
Short name T802
Test name
Test status
Simulation time 13697135 ps
CPU time 0.55 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:02 PM PDT 24
Peak memory 194168 kb
Host smart-5e6259d8-d67d-44a1-916e-f1161ec3b580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30938605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.30938605
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2652316323
Short name T747
Test name
Test status
Simulation time 16058445 ps
CPU time 0.58 seconds
Started Jul 05 04:28:05 PM PDT 24
Finished Jul 05 04:28:14 PM PDT 24
Peak memory 194232 kb
Host smart-95037e30-fba0-48ae-8f99-8903c12dab4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652316323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2652316323
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.710393937
Short name T753
Test name
Test status
Simulation time 108799772 ps
CPU time 0.59 seconds
Started Jul 05 04:28:10 PM PDT 24
Finished Jul 05 04:28:23 PM PDT 24
Peak memory 194204 kb
Host smart-98c0c40b-ef03-4a18-bd5c-a30bfe8c220e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710393937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.710393937
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.845767538
Short name T761
Test name
Test status
Simulation time 34106555 ps
CPU time 0.58 seconds
Started Jul 05 04:27:49 PM PDT 24
Finished Jul 05 04:27:54 PM PDT 24
Peak memory 194172 kb
Host smart-5780c0c8-2e23-46bf-8c44-2048a070fe41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845767538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.845767538
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1988094876
Short name T790
Test name
Test status
Simulation time 12004865 ps
CPU time 0.56 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:10 PM PDT 24
Peak memory 194808 kb
Host smart-8623912d-bcf8-4150-83ce-712fca95de7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988094876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1988094876
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.635241359
Short name T793
Test name
Test status
Simulation time 29159569 ps
CPU time 0.59 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:02 PM PDT 24
Peak memory 194212 kb
Host smart-747a493f-42e9-40d5-960c-bad50d5c37c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635241359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.635241359
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.13445231
Short name T744
Test name
Test status
Simulation time 17712664 ps
CPU time 0.61 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:22 PM PDT 24
Peak memory 194220 kb
Host smart-eeda036e-dd59-42a4-93d0-b3923fbf53c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13445231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.13445231
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1665766502
Short name T832
Test name
Test status
Simulation time 11619857 ps
CPU time 0.62 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 194236 kb
Host smart-50906a2c-14bd-4304-b62c-03d4f2030e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665766502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1665766502
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2231613266
Short name T86
Test name
Test status
Simulation time 47474106 ps
CPU time 0.74 seconds
Started Jul 05 04:27:36 PM PDT 24
Finished Jul 05 04:27:39 PM PDT 24
Peak memory 196452 kb
Host smart-0b7ff662-9ebc-4eec-b103-4b18df2f7c5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231613266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2231613266
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.750241994
Short name T78
Test name
Test status
Simulation time 1149711948 ps
CPU time 1.46 seconds
Started Jul 05 04:27:58 PM PDT 24
Finished Jul 05 04:28:04 PM PDT 24
Peak memory 198512 kb
Host smart-3311e0ff-bcbe-40db-9010-91f8080afca8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750241994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.750241994
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2920612059
Short name T92
Test name
Test status
Simulation time 36393304 ps
CPU time 0.58 seconds
Started Jul 05 04:28:02 PM PDT 24
Finished Jul 05 04:28:09 PM PDT 24
Peak memory 195604 kb
Host smart-2b1ce149-ad07-43fe-9b32-21e1121c2a59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920612059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2920612059
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3198152756
Short name T770
Test name
Test status
Simulation time 112574085 ps
CPU time 0.63 seconds
Started Jul 05 04:27:37 PM PDT 24
Finished Jul 05 04:27:41 PM PDT 24
Peak memory 198244 kb
Host smart-d1fa432a-7128-4bc7-9727-7560c58e7146
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198152756 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3198152756
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2143198763
Short name T757
Test name
Test status
Simulation time 24916568 ps
CPU time 0.61 seconds
Started Jul 05 04:27:33 PM PDT 24
Finished Jul 05 04:27:35 PM PDT 24
Peak memory 193688 kb
Host smart-392ce0aa-5819-4287-8b4c-f215ee5aaf91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143198763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2143198763
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2930164058
Short name T773
Test name
Test status
Simulation time 111598408 ps
CPU time 0.61 seconds
Started Jul 05 04:27:53 PM PDT 24
Finished Jul 05 04:27:58 PM PDT 24
Peak memory 194848 kb
Host smart-0a1e8408-6ff4-4e82-aa42-1775b318231e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930164058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2930164058
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3556299557
Short name T99
Test name
Test status
Simulation time 40659046 ps
CPU time 0.84 seconds
Started Jul 05 04:27:33 PM PDT 24
Finished Jul 05 04:27:41 PM PDT 24
Peak memory 196652 kb
Host smart-314d6efa-808f-4ac5-bde3-8f109014fff6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556299557 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3556299557
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1506993085
Short name T819
Test name
Test status
Simulation time 95614401 ps
CPU time 1.99 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:07 PM PDT 24
Peak memory 198584 kb
Host smart-67df29ad-2a10-45d9-95b4-c4a993ce6980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506993085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1506993085
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3654448487
Short name T47
Test name
Test status
Simulation time 50803228 ps
CPU time 0.83 seconds
Started Jul 05 04:27:38 PM PDT 24
Finished Jul 05 04:27:42 PM PDT 24
Peak memory 198416 kb
Host smart-c15db833-79ba-4b8d-ae38-aebfacdadc14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654448487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3654448487
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2242668856
Short name T758
Test name
Test status
Simulation time 16311975 ps
CPU time 0.58 seconds
Started Jul 05 04:27:47 PM PDT 24
Finished Jul 05 04:27:52 PM PDT 24
Peak memory 194204 kb
Host smart-e0cb04d5-955c-4e29-8798-ae8ca6416e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242668856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2242668856
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.785122827
Short name T727
Test name
Test status
Simulation time 15070374 ps
CPU time 0.64 seconds
Started Jul 05 04:28:04 PM PDT 24
Finished Jul 05 04:28:12 PM PDT 24
Peak memory 194272 kb
Host smart-c3db2410-4501-4984-b859-cd931d95469e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785122827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.785122827
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.564492624
Short name T795
Test name
Test status
Simulation time 30230788 ps
CPU time 0.55 seconds
Started Jul 05 04:27:48 PM PDT 24
Finished Jul 05 04:27:54 PM PDT 24
Peak memory 194144 kb
Host smart-1c7433b9-0bc4-4f4c-a77f-9f3fd50f23cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564492624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.564492624
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2730713469
Short name T718
Test name
Test status
Simulation time 12411717 ps
CPU time 0.63 seconds
Started Jul 05 04:27:52 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 194328 kb
Host smart-24d3094a-59c8-498b-8f25-2f5f6345fe90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730713469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2730713469
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2364488822
Short name T756
Test name
Test status
Simulation time 13629284 ps
CPU time 0.59 seconds
Started Jul 05 04:27:52 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 194836 kb
Host smart-4858e71d-ab14-4b2e-aa6e-d1c6f781979a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364488822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2364488822
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.670200808
Short name T812
Test name
Test status
Simulation time 98171271 ps
CPU time 0.58 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:11 PM PDT 24
Peak memory 194952 kb
Host smart-d543d4ee-85a2-439f-a9fd-f2ba0125d405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670200808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.670200808
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.631877368
Short name T736
Test name
Test status
Simulation time 19298970 ps
CPU time 0.61 seconds
Started Jul 05 04:28:00 PM PDT 24
Finished Jul 05 04:28:07 PM PDT 24
Peak memory 194268 kb
Host smart-2e4cb112-2d76-4c0f-aea6-ce370a9f6b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631877368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.631877368
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2143274022
Short name T831
Test name
Test status
Simulation time 26787370 ps
CPU time 0.58 seconds
Started Jul 05 04:27:52 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 194844 kb
Host smart-d6579de1-0342-4fee-a83f-2ac5232d4af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143274022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2143274022
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1327212589
Short name T722
Test name
Test status
Simulation time 60947662 ps
CPU time 0.63 seconds
Started Jul 05 04:28:00 PM PDT 24
Finished Jul 05 04:28:06 PM PDT 24
Peak memory 194796 kb
Host smart-a70b8dab-5e85-4381-9bf7-90311515dd83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327212589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1327212589
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1642121643
Short name T801
Test name
Test status
Simulation time 17685407 ps
CPU time 0.61 seconds
Started Jul 05 04:27:52 PM PDT 24
Finished Jul 05 04:27:57 PM PDT 24
Peak memory 194224 kb
Host smart-900f61f6-88b4-4332-b1b5-ebaf2f4953ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642121643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1642121643
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.413341601
Short name T791
Test name
Test status
Simulation time 27177183 ps
CPU time 0.75 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:16 PM PDT 24
Peak memory 196256 kb
Host smart-aa822fae-7922-4c68-aabc-07717c31d6fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413341601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.413341601
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.901214918
Short name T95
Test name
Test status
Simulation time 124603319 ps
CPU time 1.33 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:06 PM PDT 24
Peak memory 198548 kb
Host smart-b3d6bd58-8ca2-46da-a9c6-eb6340e04324
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901214918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.901214918
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3336207005
Short name T748
Test name
Test status
Simulation time 39172663 ps
CPU time 0.6 seconds
Started Jul 05 04:27:29 PM PDT 24
Finished Jul 05 04:27:32 PM PDT 24
Peak memory 195604 kb
Host smart-7be483ee-398b-4542-b264-d0182e2d159c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336207005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3336207005
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.537075878
Short name T717
Test name
Test status
Simulation time 26655249 ps
CPU time 0.69 seconds
Started Jul 05 04:27:28 PM PDT 24
Finished Jul 05 04:27:31 PM PDT 24
Peak memory 198320 kb
Host smart-67050fb4-cec1-497b-a1c0-d23ccdb7086e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537075878 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.537075878
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.857764818
Short name T785
Test name
Test status
Simulation time 38874553 ps
CPU time 0.61 seconds
Started Jul 05 04:27:33 PM PDT 24
Finished Jul 05 04:27:35 PM PDT 24
Peak memory 195472 kb
Host smart-31594cb5-7bb8-46e7-ae55-8267ba2bde4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857764818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.857764818
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1348430972
Short name T735
Test name
Test status
Simulation time 14627678 ps
CPU time 0.6 seconds
Started Jul 05 04:27:29 PM PDT 24
Finished Jul 05 04:27:32 PM PDT 24
Peak memory 194280 kb
Host smart-87c20c39-e86f-40bd-b4dc-5d771b156582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348430972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1348430972
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4290195632
Short name T103
Test name
Test status
Simulation time 15959049 ps
CPU time 0.75 seconds
Started Jul 05 04:27:44 PM PDT 24
Finished Jul 05 04:27:49 PM PDT 24
Peak memory 197076 kb
Host smart-626b06d1-cd43-4a77-b650-90adf9dd8cfb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290195632 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4290195632
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2987584754
Short name T738
Test name
Test status
Simulation time 166130990 ps
CPU time 3.07 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:04 PM PDT 24
Peak memory 198528 kb
Host smart-246e24cd-c8af-4de3-acd8-3c71d1e98b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987584754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2987584754
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2751408612
Short name T783
Test name
Test status
Simulation time 18058713 ps
CPU time 0.57 seconds
Started Jul 05 04:27:50 PM PDT 24
Finished Jul 05 04:27:56 PM PDT 24
Peak memory 194232 kb
Host smart-10322fc1-933a-4975-8269-fdb33a9b06cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751408612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2751408612
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3293063562
Short name T760
Test name
Test status
Simulation time 11533038 ps
CPU time 0.56 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:16 PM PDT 24
Peak memory 194136 kb
Host smart-020d6249-db2d-4fd4-903b-ffc1b20bbc8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293063562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3293063562
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.4294002839
Short name T780
Test name
Test status
Simulation time 57492727 ps
CPU time 0.57 seconds
Started Jul 05 04:28:05 PM PDT 24
Finished Jul 05 04:28:13 PM PDT 24
Peak memory 194860 kb
Host smart-61877de6-c6cf-4cb2-bb81-7498e4d79893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294002839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.4294002839
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2595979954
Short name T720
Test name
Test status
Simulation time 49330545 ps
CPU time 0.56 seconds
Started Jul 05 04:28:40 PM PDT 24
Finished Jul 05 04:28:52 PM PDT 24
Peak memory 194160 kb
Host smart-cbd676b3-7a30-4720-8519-ef683803a009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595979954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2595979954
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.565099660
Short name T746
Test name
Test status
Simulation time 15441139 ps
CPU time 0.6 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:06 PM PDT 24
Peak memory 194852 kb
Host smart-69db2fe7-ea93-49d6-8e91-83f475fc7140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565099660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.565099660
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1104256480
Short name T742
Test name
Test status
Simulation time 18350210 ps
CPU time 0.59 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:17 PM PDT 24
Peak memory 194276 kb
Host smart-642d3bfe-e588-4ce5-97ea-2e7e1ef53a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104256480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1104256480
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2610583157
Short name T732
Test name
Test status
Simulation time 33845495 ps
CPU time 0.56 seconds
Started Jul 05 04:28:21 PM PDT 24
Finished Jul 05 04:28:35 PM PDT 24
Peak memory 194836 kb
Host smart-06d8d939-5f21-4da3-bd7e-57f9230e18b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610583157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2610583157
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2519462594
Short name T739
Test name
Test status
Simulation time 13476480 ps
CPU time 0.58 seconds
Started Jul 05 04:27:53 PM PDT 24
Finished Jul 05 04:27:58 PM PDT 24
Peak memory 194872 kb
Host smart-1be261ef-35c9-4168-b51b-12838d04a94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519462594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2519462594
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2106654834
Short name T715
Test name
Test status
Simulation time 12373983 ps
CPU time 0.59 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:01 PM PDT 24
Peak memory 194112 kb
Host smart-989c9031-5312-4cd5-8223-262cd6f71d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106654834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2106654834
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3871972660
Short name T772
Test name
Test status
Simulation time 90739294 ps
CPU time 0.55 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:07 PM PDT 24
Peak memory 194184 kb
Host smart-5fbf6120-db12-4375-aa2f-26bdf04fa852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871972660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3871972660
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3195203969
Short name T737
Test name
Test status
Simulation time 31245618 ps
CPU time 0.81 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:01 PM PDT 24
Peak memory 198428 kb
Host smart-9cc8eb80-8af1-4ad2-b4bc-1c3e0cba1c9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195203969 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3195203969
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2277348596
Short name T811
Test name
Test status
Simulation time 23496148 ps
CPU time 0.61 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:04 PM PDT 24
Peak memory 196052 kb
Host smart-c8b55a82-4a6d-4a7d-a539-a40fc8174f99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277348596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2277348596
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2186282728
Short name T729
Test name
Test status
Simulation time 45251830 ps
CPU time 0.6 seconds
Started Jul 05 04:27:28 PM PDT 24
Finished Jul 05 04:27:30 PM PDT 24
Peak memory 194240 kb
Host smart-cb6bc75d-4d96-4807-a96c-a3fe8e549dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186282728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2186282728
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3004832256
Short name T102
Test name
Test status
Simulation time 92154635 ps
CPU time 0.74 seconds
Started Jul 05 04:27:34 PM PDT 24
Finished Jul 05 04:27:49 PM PDT 24
Peak memory 195308 kb
Host smart-f536d21f-e9e4-4a2c-91a8-fdf3eeeb28fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004832256 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3004832256
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3948751698
Short name T782
Test name
Test status
Simulation time 46067235 ps
CPU time 1.27 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:47 PM PDT 24
Peak memory 198576 kb
Host smart-ec53451c-a087-452c-a089-7345c5481d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948751698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3948751698
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3319675707
Short name T45
Test name
Test status
Simulation time 166964483 ps
CPU time 0.86 seconds
Started Jul 05 04:27:46 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 197744 kb
Host smart-035aca12-6178-49e4-a2e2-8c460a8e0a3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319675707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3319675707
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1412243655
Short name T776
Test name
Test status
Simulation time 25718032 ps
CPU time 0.62 seconds
Started Jul 05 04:27:57 PM PDT 24
Finished Jul 05 04:28:02 PM PDT 24
Peak memory 196904 kb
Host smart-8f73c186-3ed4-4a53-b976-84c7cdeed53d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412243655 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1412243655
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.694793465
Short name T754
Test name
Test status
Simulation time 23793538 ps
CPU time 0.6 seconds
Started Jul 05 04:27:56 PM PDT 24
Finished Jul 05 04:28:00 PM PDT 24
Peak memory 193856 kb
Host smart-3829a18c-1e0c-4910-bd5c-b2bd0b0b5be6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694793465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.694793465
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1988232928
Short name T817
Test name
Test status
Simulation time 37747774 ps
CPU time 0.63 seconds
Started Jul 05 04:28:00 PM PDT 24
Finished Jul 05 04:28:07 PM PDT 24
Peak memory 194252 kb
Host smart-2da39f6d-3cff-4a43-9f66-3a7461a608ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988232928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1988232928
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2291608774
Short name T80
Test name
Test status
Simulation time 67711930 ps
CPU time 0.86 seconds
Started Jul 05 04:27:29 PM PDT 24
Finished Jul 05 04:27:31 PM PDT 24
Peak memory 198128 kb
Host smart-8dd3e112-6be7-433d-8c1e-19a5f0ab0854
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291608774 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2291608774
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2497867742
Short name T818
Test name
Test status
Simulation time 54514173 ps
CPU time 1.21 seconds
Started Jul 05 04:28:37 PM PDT 24
Finished Jul 05 04:28:50 PM PDT 24
Peak memory 198556 kb
Host smart-87616638-2e2e-43eb-8207-9b4a8c2213db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497867742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2497867742
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.375703212
Short name T56
Test name
Test status
Simulation time 139686175 ps
CPU time 1.32 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:16 PM PDT 24
Peak memory 198592 kb
Host smart-7d59c248-879b-4a61-a136-81089ea9439b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375703212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.375703212
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.21513681
Short name T775
Test name
Test status
Simulation time 103414424 ps
CPU time 0.78 seconds
Started Jul 05 04:28:05 PM PDT 24
Finished Jul 05 04:28:15 PM PDT 24
Peak memory 198456 kb
Host smart-a8968c19-a1e5-4765-a094-e5f7bf3bc354
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21513681 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.21513681
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3390403124
Short name T85
Test name
Test status
Simulation time 59534878 ps
CPU time 0.58 seconds
Started Jul 05 04:28:07 PM PDT 24
Finished Jul 05 04:28:18 PM PDT 24
Peak memory 194964 kb
Host smart-62d4329b-c42d-459d-bf09-02d3b825dbde
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390403124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3390403124
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2425019972
Short name T786
Test name
Test status
Simulation time 15488578 ps
CPU time 0.59 seconds
Started Jul 05 04:28:06 PM PDT 24
Finished Jul 05 04:28:16 PM PDT 24
Peak memory 194212 kb
Host smart-e10c963a-92c9-40f1-aba8-b39fb0856676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425019972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2425019972
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.962962119
Short name T105
Test name
Test status
Simulation time 26833959 ps
CPU time 0.75 seconds
Started Jul 05 04:27:36 PM PDT 24
Finished Jul 05 04:27:39 PM PDT 24
Peak memory 196604 kb
Host smart-c3979059-69fc-44b2-a0b6-a9cce7833a7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962962119 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.962962119
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1596825430
Short name T769
Test name
Test status
Simulation time 270091221 ps
CPU time 1.69 seconds
Started Jul 05 04:27:50 PM PDT 24
Finished Jul 05 04:27:56 PM PDT 24
Peak memory 198992 kb
Host smart-b2c99c6c-caad-4df3-9e95-5a7006f3beea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596825430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1596825430
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1211930014
Short name T779
Test name
Test status
Simulation time 164283897 ps
CPU time 0.86 seconds
Started Jul 05 04:27:30 PM PDT 24
Finished Jul 05 04:27:33 PM PDT 24
Peak memory 198156 kb
Host smart-f3e11119-b436-4fbc-9c42-48a1f13c3eef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211930014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1211930014
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1312640810
Short name T837
Test name
Test status
Simulation time 18468804 ps
CPU time 0.75 seconds
Started Jul 05 04:28:04 PM PDT 24
Finished Jul 05 04:28:12 PM PDT 24
Peak memory 198456 kb
Host smart-2195f5e8-ad2b-45b1-8247-0d450ec515f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312640810 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1312640810
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.888781872
Short name T745
Test name
Test status
Simulation time 29210327 ps
CPU time 0.56 seconds
Started Jul 05 04:27:42 PM PDT 24
Finished Jul 05 04:27:47 PM PDT 24
Peak memory 194444 kb
Host smart-2a898b2a-252b-460a-8b4d-a17e5cb58eba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888781872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.888781872
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3614186513
Short name T767
Test name
Test status
Simulation time 12546174 ps
CPU time 0.59 seconds
Started Jul 05 04:27:47 PM PDT 24
Finished Jul 05 04:27:52 PM PDT 24
Peak memory 194196 kb
Host smart-1fd3544e-80f9-46d1-95ae-f82210ff68d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614186513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3614186513
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2801514514
Short name T798
Test name
Test status
Simulation time 27194113 ps
CPU time 0.78 seconds
Started Jul 05 04:28:09 PM PDT 24
Finished Jul 05 04:28:21 PM PDT 24
Peak memory 196612 kb
Host smart-3fbf75a5-bf5f-4cef-ae10-2c908b9dac57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801514514 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2801514514
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2224209967
Short name T750
Test name
Test status
Simulation time 81317844 ps
CPU time 1.75 seconds
Started Jul 05 04:27:45 PM PDT 24
Finished Jul 05 04:27:51 PM PDT 24
Peak memory 198556 kb
Host smart-16a60a77-4deb-4b60-912b-688c773edc9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224209967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2224209967
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1024595235
Short name T54
Test name
Test status
Simulation time 83091729 ps
CPU time 1.11 seconds
Started Jul 05 04:27:49 PM PDT 24
Finished Jul 05 04:27:55 PM PDT 24
Peak memory 198616 kb
Host smart-872fdf35-4512-47da-952a-2f1a54fda5a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024595235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1024595235
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.382999268
Short name T731
Test name
Test status
Simulation time 36228509 ps
CPU time 0.94 seconds
Started Jul 05 04:27:38 PM PDT 24
Finished Jul 05 04:27:42 PM PDT 24
Peak memory 198368 kb
Host smart-7dea2b02-64ea-446c-a11e-c54cfedd64ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382999268 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.382999268
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3173162351
Short name T96
Test name
Test status
Simulation time 25203072 ps
CPU time 0.6 seconds
Started Jul 05 04:27:36 PM PDT 24
Finished Jul 05 04:27:39 PM PDT 24
Peak memory 196060 kb
Host smart-e3b7f098-ede2-4c79-8de7-af63dede94df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173162351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3173162351
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1352191328
Short name T823
Test name
Test status
Simulation time 15030144 ps
CPU time 0.61 seconds
Started Jul 05 04:28:17 PM PDT 24
Finished Jul 05 04:28:30 PM PDT 24
Peak memory 194936 kb
Host smart-7aceecc3-a4af-41fd-a288-8a83b1c1ca26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352191328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1352191328
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2338124401
Short name T101
Test name
Test status
Simulation time 23424872 ps
CPU time 0.83 seconds
Started Jul 05 04:28:03 PM PDT 24
Finished Jul 05 04:28:11 PM PDT 24
Peak memory 197664 kb
Host smart-635f7906-ebc9-4a46-af0e-b8a54d4b228d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338124401 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2338124401
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1281024048
Short name T804
Test name
Test status
Simulation time 161780677 ps
CPU time 2.72 seconds
Started Jul 05 04:27:59 PM PDT 24
Finished Jul 05 04:28:08 PM PDT 24
Peak memory 198512 kb
Host smart-1f074e19-1ffb-4057-a7fa-ec3985a4f233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281024048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1281024048
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3860827925
Short name T196
Test name
Test status
Simulation time 27865307 ps
CPU time 0.57 seconds
Started Jul 05 04:35:42 PM PDT 24
Finished Jul 05 04:35:43 PM PDT 24
Peak memory 194600 kb
Host smart-9ecb7b08-0292-434b-a944-70d2834ccfb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860827925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3860827925
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2330165661
Short name T693
Test name
Test status
Simulation time 30368951 ps
CPU time 0.87 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 196276 kb
Host smart-b8d56d9f-1166-477e-a00c-accb1713f852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330165661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2330165661
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1427182673
Short name T250
Test name
Test status
Simulation time 1004681042 ps
CPU time 27.74 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:36:23 PM PDT 24
Peak memory 197704 kb
Host smart-57405317-c459-4dfd-b403-c8c091c5a915
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427182673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1427182673
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3115288050
Short name T640
Test name
Test status
Simulation time 60737928 ps
CPU time 0.61 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 195712 kb
Host smart-a1bc4a4f-56f8-49a3-86b4-5eff9c272f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115288050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3115288050
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1293874886
Short name T477
Test name
Test status
Simulation time 154637301 ps
CPU time 1.3 seconds
Started Jul 05 04:35:33 PM PDT 24
Finished Jul 05 04:35:35 PM PDT 24
Peak memory 196576 kb
Host smart-bdc5cec8-6de8-4f7d-a373-c357a30b9826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293874886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1293874886
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1959345659
Short name T562
Test name
Test status
Simulation time 22027092 ps
CPU time 0.94 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:35:59 PM PDT 24
Peak memory 196552 kb
Host smart-a13eb9d4-780b-4950-a7ea-a54e74ec1787
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959345659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1959345659
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2666434509
Short name T235
Test name
Test status
Simulation time 148323895 ps
CPU time 1.78 seconds
Started Jul 05 04:35:42 PM PDT 24
Finished Jul 05 04:35:44 PM PDT 24
Peak memory 196748 kb
Host smart-f4325349-b187-4dd8-bb1f-9f3579fe7b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666434509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2666434509
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2019311173
Short name T114
Test name
Test status
Simulation time 131509282 ps
CPU time 1.22 seconds
Started Jul 05 04:35:29 PM PDT 24
Finished Jul 05 04:35:31 PM PDT 24
Peak memory 197596 kb
Host smart-cf239c45-057e-47d7-9e0d-c72b28aa986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019311173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2019311173
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1852668350
Short name T543
Test name
Test status
Simulation time 118670835 ps
CPU time 1.07 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 196572 kb
Host smart-ca317e45-9d0c-46cf-8fed-7da35478aa01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852668350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1852668350
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1998853332
Short name T485
Test name
Test status
Simulation time 227155761 ps
CPU time 3.17 seconds
Started Jul 05 04:35:35 PM PDT 24
Finished Jul 05 04:35:39 PM PDT 24
Peak memory 198708 kb
Host smart-adc2b2fc-3ba0-43e3-a241-33af7a8156cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998853332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1998853332
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3547741798
Short name T59
Test name
Test status
Simulation time 66521965 ps
CPU time 0.87 seconds
Started Jul 05 04:35:33 PM PDT 24
Finished Jul 05 04:35:35 PM PDT 24
Peak memory 214376 kb
Host smart-9ba2a7fa-aaa4-4ce9-b1a7-fe9172228dd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547741798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3547741798
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3708592369
Short name T540
Test name
Test status
Simulation time 41661108 ps
CPU time 1.25 seconds
Started Jul 05 04:35:38 PM PDT 24
Finished Jul 05 04:35:40 PM PDT 24
Peak memory 196936 kb
Host smart-e0059b25-50ce-4c53-8c1d-4061495d8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708592369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3708592369
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2278883106
Short name T478
Test name
Test status
Simulation time 41561782 ps
CPU time 0.95 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 196048 kb
Host smart-9dd6617d-efd4-4d13-ae84-a462ec8a6680
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278883106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2278883106
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.538141052
Short name T397
Test name
Test status
Simulation time 37683304 ps
CPU time 0.68 seconds
Started Jul 05 04:35:41 PM PDT 24
Finished Jul 05 04:35:42 PM PDT 24
Peak memory 194792 kb
Host smart-00311ee4-ee61-43c7-9ef4-d51bf29caa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538141052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.538141052
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4059451724
Short name T642
Test name
Test status
Simulation time 293532245 ps
CPU time 4.88 seconds
Started Jul 05 04:35:47 PM PDT 24
Finished Jul 05 04:35:53 PM PDT 24
Peak memory 198588 kb
Host smart-f9a81bdd-b680-402e-b886-c9dfd50242e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059451724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4059451724
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.558102494
Short name T666
Test name
Test status
Simulation time 135981482 ps
CPU time 0.78 seconds
Started Jul 05 04:35:39 PM PDT 24
Finished Jul 05 04:35:40 PM PDT 24
Peak memory 196588 kb
Host smart-9ff6c7b7-8f5c-4149-8134-32514dcef9c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558102494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.558102494
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1760182828
Short name T641
Test name
Test status
Simulation time 163241632 ps
CPU time 0.91 seconds
Started Jul 05 04:35:39 PM PDT 24
Finished Jul 05 04:35:40 PM PDT 24
Peak memory 197412 kb
Host smart-6d077718-2e84-4831-95ca-92ccb4e9925e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760182828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1760182828
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1277514720
Short name T390
Test name
Test status
Simulation time 67747626 ps
CPU time 1.61 seconds
Started Jul 05 04:35:48 PM PDT 24
Finished Jul 05 04:35:51 PM PDT 24
Peak memory 196656 kb
Host smart-fc364ac2-e0f9-44fb-bd6f-d5324618e5ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277514720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1277514720
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.443596272
Short name T571
Test name
Test status
Simulation time 171520165 ps
CPU time 1.23 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 197268 kb
Host smart-87069066-9b14-4df5-b7a4-fec0b5f06c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443596272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.443596272
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1342955482
Short name T262
Test name
Test status
Simulation time 72843898 ps
CPU time 1.22 seconds
Started Jul 05 04:35:50 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 197660 kb
Host smart-06fe53e3-d2df-489a-ba03-f74bb3722169
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342955482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1342955482
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3367969034
Short name T7
Test name
Test status
Simulation time 2549307642 ps
CPU time 4.47 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:03 PM PDT 24
Peak memory 198644 kb
Host smart-9a46a83d-1ce0-4b51-8387-88ba4c6f7b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367969034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3367969034
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.1122319734
Short name T326
Test name
Test status
Simulation time 37770015 ps
CPU time 1.03 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:46 PM PDT 24
Peak memory 196400 kb
Host smart-7d4abff3-fa26-4fb4-95ba-a245d8c4d037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122319734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1122319734
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3873951732
Short name T193
Test name
Test status
Simulation time 125420279 ps
CPU time 1.11 seconds
Started Jul 05 04:35:50 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 196408 kb
Host smart-f4a8649e-5d9e-4914-9629-90b4284941d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873951732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3873951732
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.592411991
Short name T239
Test name
Test status
Simulation time 2568429293 ps
CPU time 63.17 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 198796 kb
Host smart-a175be77-ad40-47c8-8fe4-d2c419f3cf86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592411991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.592411991
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2084690146
Short name T583
Test name
Test status
Simulation time 15381898 ps
CPU time 0.62 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 196260 kb
Host smart-4e7c56b0-fa5b-4683-96e0-6c9200d661a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084690146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2084690146
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2959777678
Short name T506
Test name
Test status
Simulation time 34986697 ps
CPU time 0.63 seconds
Started Jul 05 04:35:52 PM PDT 24
Finished Jul 05 04:35:53 PM PDT 24
Peak memory 194660 kb
Host smart-64384603-d41d-40fc-bc89-2584cf7ea982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959777678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2959777678
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3579903024
Short name T115
Test name
Test status
Simulation time 801124914 ps
CPU time 8.62 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 196140 kb
Host smart-f3b234f1-3d08-47b4-83a7-19e653702852
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579903024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3579903024
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1239039133
Short name T372
Test name
Test status
Simulation time 361046586 ps
CPU time 0.79 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 197192 kb
Host smart-ddd1436a-a830-446c-83d7-9ad38b00249a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239039133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1239039133
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1710941238
Short name T199
Test name
Test status
Simulation time 119381133 ps
CPU time 0.82 seconds
Started Jul 05 04:35:51 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 196188 kb
Host smart-0d171ffa-d0b0-48e1-9f76-0d83e4d6ae7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710941238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1710941238
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.905661601
Short name T304
Test name
Test status
Simulation time 81076342 ps
CPU time 3.03 seconds
Started Jul 05 04:35:53 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 197024 kb
Host smart-2afd7fab-e8ad-448a-8228-e9630b23ca00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905661601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.905661601
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3091399968
Short name T276
Test name
Test status
Simulation time 222368249 ps
CPU time 1.45 seconds
Started Jul 05 04:35:52 PM PDT 24
Finished Jul 05 04:35:54 PM PDT 24
Peak memory 197180 kb
Host smart-f4930e12-7dea-4b4c-80e0-c38132e058cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091399968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3091399968
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3564386009
Short name T129
Test name
Test status
Simulation time 60446031 ps
CPU time 1.06 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 196636 kb
Host smart-3cc982ec-2752-434c-a93c-c258055a7030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564386009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3564386009
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.119906085
Short name T269
Test name
Test status
Simulation time 83645561 ps
CPU time 0.95 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 197236 kb
Host smart-fd67c703-3bb5-4588-ac9d-1e796d808607
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119906085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.119906085
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.710862158
Short name T205
Test name
Test status
Simulation time 295084752 ps
CPU time 1.52 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 198692 kb
Host smart-02c55292-1042-4083-95f3-7f24641f73e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710862158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.710862158
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.80166550
Short name T334
Test name
Test status
Simulation time 60698217 ps
CPU time 0.93 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 196816 kb
Host smart-883c9e32-cf34-4a9b-b5ec-5bddde77ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80166550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.80166550
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3339026039
Short name T183
Test name
Test status
Simulation time 61131232 ps
CPU time 0.88 seconds
Started Jul 05 04:36:05 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 196068 kb
Host smart-2767c700-a5da-442b-a1c0-dbc0453ccda7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339026039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3339026039
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3838982232
Short name T327
Test name
Test status
Simulation time 28201836788 ps
CPU time 87.15 seconds
Started Jul 05 04:35:53 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 198756 kb
Host smart-afe0ea69-6d09-47bd-a2d1-35da324d27d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838982232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3838982232
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.68319377
Short name T72
Test name
Test status
Simulation time 329438926052 ps
CPU time 1994.13 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 05:09:15 PM PDT 24
Peak memory 198864 kb
Host smart-e8beb10c-ad86-487d-bae4-7fb0f898e1df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=68319377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.68319377
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1350793748
Short name T515
Test name
Test status
Simulation time 23283836 ps
CPU time 0.61 seconds
Started Jul 05 04:36:08 PM PDT 24
Finished Jul 05 04:36:10 PM PDT 24
Peak memory 194684 kb
Host smart-e31ce0d6-cd95-4d9b-87db-fc3269661741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350793748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1350793748
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.735954590
Short name T311
Test name
Test status
Simulation time 28741041 ps
CPU time 0.85 seconds
Started Jul 05 04:36:04 PM PDT 24
Finished Jul 05 04:36:06 PM PDT 24
Peak memory 196536 kb
Host smart-470d1c86-fb87-4f6a-a25f-adebb0655c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735954590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.735954590
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2682120455
Short name T191
Test name
Test status
Simulation time 1221988154 ps
CPU time 9.53 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 197652 kb
Host smart-3b4bfc85-a61a-44bd-8e8b-efbc5ed72e2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682120455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2682120455
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2027751106
Short name T656
Test name
Test status
Simulation time 395234260 ps
CPU time 1.12 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 198500 kb
Host smart-dcb265cf-29e6-4ca6-ad3e-29f065f20357
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027751106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2027751106
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2865199656
Short name T427
Test name
Test status
Simulation time 157045799 ps
CPU time 1.22 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:14 PM PDT 24
Peak memory 197960 kb
Host smart-07df1178-091b-4462-b1f8-ef66404f623d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865199656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2865199656
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3608611839
Short name T375
Test name
Test status
Simulation time 45433288 ps
CPU time 1.89 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 198760 kb
Host smart-16952067-78fa-4b23-b706-ff9a9fb38530
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608611839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3608611839
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3254205836
Short name T113
Test name
Test status
Simulation time 110518089 ps
CPU time 2.31 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 197760 kb
Host smart-5e48122f-bc9c-492d-8107-95da5c48ab79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254205836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3254205836
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4195998814
Short name T24
Test name
Test status
Simulation time 64689969 ps
CPU time 0.72 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 196144 kb
Host smart-ba784ad3-bb6e-429d-8ac0-29d7f16fa1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195998814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4195998814
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1358233868
Short name T677
Test name
Test status
Simulation time 16622938 ps
CPU time 0.67 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 194876 kb
Host smart-fc70cf90-e3bb-4c70-b9f7-3b219bced2cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358233868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1358233868
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1871777764
Short name T206
Test name
Test status
Simulation time 107128180 ps
CPU time 4.9 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:08 PM PDT 24
Peak memory 198636 kb
Host smart-8764e8c2-6226-4274-9c4b-b688ab9554ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871777764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1871777764
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.4153190287
Short name T138
Test name
Test status
Simulation time 32885262 ps
CPU time 0.89 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 195932 kb
Host smart-19257393-0abd-4cc7-84a9-e8fddfc5cb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153190287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.4153190287
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3202839614
Short name T127
Test name
Test status
Simulation time 45342459 ps
CPU time 1.36 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:59 PM PDT 24
Peak memory 197500 kb
Host smart-9cad3344-f120-4501-97b9-f33f4e63acef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202839614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3202839614
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2950433674
Short name T526
Test name
Test status
Simulation time 10707060173 ps
CPU time 151.82 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:38:35 PM PDT 24
Peak memory 198880 kb
Host smart-1cb3b2c1-5862-454f-9a96-f558a4b70f5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950433674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2950433674
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.645637288
Short name T122
Test name
Test status
Simulation time 46454679 ps
CPU time 0.58 seconds
Started Jul 05 04:36:06 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 194648 kb
Host smart-60571dc6-2e88-417c-b1c5-5804daacfe74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645637288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.645637288
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1472699538
Short name T231
Test name
Test status
Simulation time 56367900 ps
CPU time 0.92 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:03 PM PDT 24
Peak memory 197264 kb
Host smart-be509b2d-4a3a-45de-a89f-a7502fd736cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472699538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1472699538
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3548986421
Short name T570
Test name
Test status
Simulation time 431096543 ps
CPU time 4.97 seconds
Started Jul 05 04:36:10 PM PDT 24
Finished Jul 05 04:36:15 PM PDT 24
Peak memory 197376 kb
Host smart-633f703d-9ab5-40db-90e4-91c4ad72fab8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548986421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3548986421
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3434100378
Short name T555
Test name
Test status
Simulation time 240371182 ps
CPU time 0.89 seconds
Started Jul 05 04:36:07 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 196732 kb
Host smart-e5426fa1-e16c-4576-b9c4-b79d52f746b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434100378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3434100378
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.522466617
Short name T296
Test name
Test status
Simulation time 51213428 ps
CPU time 0.97 seconds
Started Jul 05 04:36:05 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 197404 kb
Host smart-52fc590e-678f-4ac6-86d5-ec4768c6c4ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522466617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.522466617
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1938834168
Short name T706
Test name
Test status
Simulation time 60310314 ps
CPU time 2.28 seconds
Started Jul 05 04:36:04 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 197948 kb
Host smart-dc730be7-8bd9-412f-bfd8-dca8c527de26
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938834168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1938834168
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.956634971
Short name T598
Test name
Test status
Simulation time 171156488 ps
CPU time 2.1 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 196876 kb
Host smart-148db401-2957-48b5-999c-8d6974080e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956634971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
956634971
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.24398711
Short name T274
Test name
Test status
Simulation time 187195303 ps
CPU time 1.35 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 196532 kb
Host smart-8b310f29-783d-44f9-8c56-db95a2604ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24398711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.24398711
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2610106713
Short name T470
Test name
Test status
Simulation time 82747863 ps
CPU time 0.83 seconds
Started Jul 05 04:38:05 PM PDT 24
Finished Jul 05 04:38:10 PM PDT 24
Peak memory 197024 kb
Host smart-5a97c681-af78-485c-9f81-d9d079719e59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610106713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2610106713
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3007177872
Short name T712
Test name
Test status
Simulation time 1148944317 ps
CPU time 4.75 seconds
Started Jul 05 04:36:02 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 198620 kb
Host smart-59f7e357-a7bb-4c90-a1c6-ecf5ed0c1f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007177872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3007177872
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.491051578
Short name T586
Test name
Test status
Simulation time 404834377 ps
CPU time 1.38 seconds
Started Jul 05 04:36:09 PM PDT 24
Finished Jul 05 04:36:11 PM PDT 24
Peak memory 197328 kb
Host smart-2ab27387-36ac-4911-8dc8-b68c86f0409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491051578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.491051578
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3281414410
Short name T362
Test name
Test status
Simulation time 102324323 ps
CPU time 0.95 seconds
Started Jul 05 04:36:07 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 197124 kb
Host smart-a4c0b193-1640-4597-9b4e-b1abbc997347
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281414410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3281414410
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1215896851
Short name T151
Test name
Test status
Simulation time 7619447604 ps
CPU time 187.65 seconds
Started Jul 05 04:36:04 PM PDT 24
Finished Jul 05 04:39:13 PM PDT 24
Peak memory 198792 kb
Host smart-5f20b1be-646f-4435-8bd5-ad3d44287e73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215896851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1215896851
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.37451047
Short name T11
Test name
Test status
Simulation time 32521192 ps
CPU time 0.58 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:16 PM PDT 24
Peak memory 194660 kb
Host smart-5e079283-bbb3-4268-bb83-4ff714f29d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37451047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.37451047
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1742617636
Short name T559
Test name
Test status
Simulation time 23003364 ps
CPU time 0.75 seconds
Started Jul 05 04:36:03 PM PDT 24
Finished Jul 05 04:36:06 PM PDT 24
Peak memory 195884 kb
Host smart-09000ed4-962b-48db-b04f-3de60fdb4c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742617636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1742617636
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2748360680
Short name T137
Test name
Test status
Simulation time 698791206 ps
CPU time 24.11 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 196196 kb
Host smart-8f32f270-0749-4672-b485-b8e9bd1e1b39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748360680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2748360680
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2675006937
Short name T135
Test name
Test status
Simulation time 42751937 ps
CPU time 0.76 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:16 PM PDT 24
Peak memory 196472 kb
Host smart-2a57cd8b-b1b6-40b5-b265-f240ce77f145
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675006937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2675006937
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2860241195
Short name T471
Test name
Test status
Simulation time 39397052 ps
CPU time 0.88 seconds
Started Jul 05 04:36:12 PM PDT 24
Finished Jul 05 04:36:15 PM PDT 24
Peak memory 197396 kb
Host smart-f6e9f47d-7e51-49a0-b1bc-e4103cc3f913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860241195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2860241195
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.210770893
Short name T558
Test name
Test status
Simulation time 42333455 ps
CPU time 1.73 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:18 PM PDT 24
Peak memory 197344 kb
Host smart-d8ba0cf6-1ab1-47c5-adf0-7c3f3164eaf7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210770893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.210770893
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1227277497
Short name T286
Test name
Test status
Simulation time 209693976 ps
CPU time 2.25 seconds
Started Jul 05 04:36:15 PM PDT 24
Finished Jul 05 04:36:19 PM PDT 24
Peak memory 198724 kb
Host smart-b82abb70-7aa6-4e73-98ca-886ec7c3df2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227277497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1227277497
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.471250715
Short name T451
Test name
Test status
Simulation time 107686628 ps
CPU time 0.7 seconds
Started Jul 05 04:36:08 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 196828 kb
Host smart-4ed79662-2f6c-4ec1-a059-7d6f71d6194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471250715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.471250715
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3459098045
Short name T340
Test name
Test status
Simulation time 388913357 ps
CPU time 0.97 seconds
Started Jul 05 04:36:05 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 197288 kb
Host smart-145a8579-ce07-42e9-8225-cb2996a3d082
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459098045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3459098045
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2691248817
Short name T439
Test name
Test status
Simulation time 583534199 ps
CPU time 4.18 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:21 PM PDT 24
Peak memory 198688 kb
Host smart-ec86202e-81d8-43d7-98f0-5c0f91d6895d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691248817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2691248817
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.614088980
Short name T403
Test name
Test status
Simulation time 112136351 ps
CPU time 1.19 seconds
Started Jul 05 04:36:08 PM PDT 24
Finished Jul 05 04:36:09 PM PDT 24
Peak memory 196500 kb
Host smart-d1d8909c-1c61-447c-aa45-9cdd82101c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614088980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.614088980
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2133031240
Short name T592
Test name
Test status
Simulation time 116251541 ps
CPU time 0.95 seconds
Started Jul 05 04:36:05 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 196376 kb
Host smart-a511b972-a868-4b64-8b4a-1a397273276a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133031240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2133031240
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2587684409
Short name T121
Test name
Test status
Simulation time 30941395465 ps
CPU time 109.19 seconds
Started Jul 05 04:36:16 PM PDT 24
Finished Jul 05 04:38:07 PM PDT 24
Peak memory 198760 kb
Host smart-37d1ab13-6a61-4b66-8174-3c117c451472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587684409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2587684409
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3553479817
Short name T561
Test name
Test status
Simulation time 41672898 ps
CPU time 0.61 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:16 PM PDT 24
Peak memory 194916 kb
Host smart-703c130c-09aa-4820-b1f7-6de16e287677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553479817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3553479817
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4161767162
Short name T154
Test name
Test status
Simulation time 41935660 ps
CPU time 0.69 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:17 PM PDT 24
Peak memory 195436 kb
Host smart-7d38015e-18d3-43f1-a692-5b0b4d32ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161767162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4161767162
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.906218534
Short name T238
Test name
Test status
Simulation time 710644350 ps
CPU time 23.96 seconds
Started Jul 05 04:36:15 PM PDT 24
Finished Jul 05 04:36:41 PM PDT 24
Peak memory 197512 kb
Host smart-b8635595-4133-455f-9d0c-4219f5f1c121
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906218534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.906218534
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2682678356
Short name T446
Test name
Test status
Simulation time 130163241 ps
CPU time 0.97 seconds
Started Jul 05 04:36:18 PM PDT 24
Finished Jul 05 04:36:20 PM PDT 24
Peak memory 197256 kb
Host smart-7023e3d6-5fa8-4ba8-a249-bf414c36da26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682678356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2682678356
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1144723434
Short name T120
Test name
Test status
Simulation time 30617935 ps
CPU time 0.74 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:16 PM PDT 24
Peak memory 196756 kb
Host smart-8452aaa3-15b9-4765-9b40-f92c9d06c684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144723434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1144723434
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2340854110
Short name T169
Test name
Test status
Simulation time 148693243 ps
CPU time 2.57 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:26 PM PDT 24
Peak memory 197116 kb
Host smart-afb26792-9b0e-49b9-8982-d99a631b8b79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340854110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2340854110
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.4183699765
Short name T673
Test name
Test status
Simulation time 68002617 ps
CPU time 1.43 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:14 PM PDT 24
Peak memory 197076 kb
Host smart-cad3cd6c-11c7-401b-aa89-ea1914f6d45b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183699765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.4183699765
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1710774072
Short name T535
Test name
Test status
Simulation time 30346098 ps
CPU time 1.02 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:17 PM PDT 24
Peak memory 196632 kb
Host smart-db8e5d32-8fdc-494c-b403-f41f88471cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710774072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1710774072
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.148796922
Short name T408
Test name
Test status
Simulation time 145343260 ps
CPU time 0.86 seconds
Started Jul 05 04:36:12 PM PDT 24
Finished Jul 05 04:36:15 PM PDT 24
Peak memory 197212 kb
Host smart-84d10968-ffae-4aaf-8cb4-3917682e52c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148796922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.148796922
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3470828374
Short name T310
Test name
Test status
Simulation time 250036810 ps
CPU time 1.77 seconds
Started Jul 05 04:36:12 PM PDT 24
Finished Jul 05 04:36:16 PM PDT 24
Peak memory 198540 kb
Host smart-dc479b5f-ddbb-4990-8cf9-55a04c201644
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470828374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3470828374
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2477981677
Short name T285
Test name
Test status
Simulation time 287738640 ps
CPU time 1.37 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:18 PM PDT 24
Peak memory 196224 kb
Host smart-45e9b73d-00c1-4c45-9a74-74716f5ddbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477981677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2477981677
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1884628123
Short name T483
Test name
Test status
Simulation time 24935084 ps
CPU time 0.82 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:17 PM PDT 24
Peak memory 196484 kb
Host smart-596db178-da3b-4394-aacd-2e70b0fc9fbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884628123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1884628123
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.196567088
Short name T431
Test name
Test status
Simulation time 107640076141 ps
CPU time 152.44 seconds
Started Jul 05 04:36:12 PM PDT 24
Finished Jul 05 04:38:46 PM PDT 24
Peak memory 198784 kb
Host smart-ca359c13-3567-4ba1-939a-0e3521dc4104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196567088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.196567088
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2347961707
Short name T225
Test name
Test status
Simulation time 35377794 ps
CPU time 0.59 seconds
Started Jul 05 04:36:23 PM PDT 24
Finished Jul 05 04:36:25 PM PDT 24
Peak memory 194900 kb
Host smart-cc7aa62f-f241-4a43-88c1-27f5b8629513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347961707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2347961707
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.481162601
Short name T453
Test name
Test status
Simulation time 47536360 ps
CPU time 0.89 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:16 PM PDT 24
Peak memory 197132 kb
Host smart-7443f24c-eb17-427e-a5ba-506f18fa0b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481162601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.481162601
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3080837468
Short name T364
Test name
Test status
Simulation time 974099203 ps
CPU time 27.54 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:43 PM PDT 24
Peak memory 198700 kb
Host smart-e69306a3-cb9a-4f98-b924-0f56485f8a99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080837468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3080837468
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2039994419
Short name T655
Test name
Test status
Simulation time 67704650 ps
CPU time 0.97 seconds
Started Jul 05 04:36:21 PM PDT 24
Finished Jul 05 04:36:22 PM PDT 24
Peak memory 197092 kb
Host smart-84ea36d6-e1e2-499d-ad00-7a67c6c63e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039994419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2039994419
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.744061007
Short name T500
Test name
Test status
Simulation time 63637269 ps
CPU time 1.08 seconds
Started Jul 05 04:36:13 PM PDT 24
Finished Jul 05 04:36:17 PM PDT 24
Peak memory 196712 kb
Host smart-e417f06c-e247-4bf4-9648-ff7b9926071a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744061007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.744061007
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2353587675
Short name T145
Test name
Test status
Simulation time 111383955 ps
CPU time 1.38 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 197028 kb
Host smart-c74ccc77-5d22-4cbc-84bb-e197d08a8a5a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353587675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2353587675
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2884296945
Short name T134
Test name
Test status
Simulation time 120992581 ps
CPU time 2.49 seconds
Started Jul 05 04:36:14 PM PDT 24
Finished Jul 05 04:36:19 PM PDT 24
Peak memory 198752 kb
Host smart-cb592d92-fb00-46d0-a6ab-f8fb453e50d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884296945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2884296945
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1748091895
Short name T660
Test name
Test status
Simulation time 103594330 ps
CPU time 1.04 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 196500 kb
Host smart-5b83659e-9771-49b1-8a74-27b7d2f18d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748091895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1748091895
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3544913691
Short name T605
Test name
Test status
Simulation time 20949070 ps
CPU time 0.8 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:30 PM PDT 24
Peak memory 196136 kb
Host smart-25f2401b-ca9e-4e68-a2bf-f5e4ab117d84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544913691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3544913691
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.275921466
Short name T227
Test name
Test status
Simulation time 715882023 ps
CPU time 2.94 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:26 PM PDT 24
Peak memory 198668 kb
Host smart-c2a9be86-92c0-4752-9d48-23a17aad72d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275921466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.275921466
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3469053089
Short name T273
Test name
Test status
Simulation time 253614802 ps
CPU time 1.22 seconds
Started Jul 05 04:36:11 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 196204 kb
Host smart-b77d6758-db8e-4ffe-943e-50e7a355141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469053089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3469053089
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3995437953
Short name T330
Test name
Test status
Simulation time 59209667 ps
CPU time 1.21 seconds
Started Jul 05 04:36:12 PM PDT 24
Finished Jul 05 04:36:14 PM PDT 24
Peak memory 197340 kb
Host smart-32ed5e1e-b1ed-4aa0-8956-47fec8efaa2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995437953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3995437953
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2716252242
Short name T445
Test name
Test status
Simulation time 56704194303 ps
CPU time 180.17 seconds
Started Jul 05 04:36:23 PM PDT 24
Finished Jul 05 04:39:25 PM PDT 24
Peak memory 198748 kb
Host smart-73abeac7-f81a-4f38-9340-023683293dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716252242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2716252242
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2062123128
Short name T473
Test name
Test status
Simulation time 50386881 ps
CPU time 0.58 seconds
Started Jul 05 04:36:24 PM PDT 24
Finished Jul 05 04:36:26 PM PDT 24
Peak memory 195268 kb
Host smart-026d3d5c-c935-4174-b13e-4598f5826a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062123128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2062123128
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1528976248
Short name T676
Test name
Test status
Simulation time 21754729 ps
CPU time 0.75 seconds
Started Jul 05 04:36:21 PM PDT 24
Finished Jul 05 04:36:23 PM PDT 24
Peak memory 195868 kb
Host smart-55f25f2c-660b-4e11-8058-cf8866b987e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528976248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1528976248
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1348436661
Short name T423
Test name
Test status
Simulation time 358302510 ps
CPU time 19.47 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:43 PM PDT 24
Peak memory 198600 kb
Host smart-23f93180-87dc-4134-8638-4ff7000b49ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348436661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1348436661
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1127579741
Short name T513
Test name
Test status
Simulation time 111110677 ps
CPU time 0.87 seconds
Started Jul 05 04:36:19 PM PDT 24
Finished Jul 05 04:36:20 PM PDT 24
Peak memory 197808 kb
Host smart-326ed453-7d33-42be-a10a-cfb08634d9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127579741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1127579741
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3129341566
Short name T618
Test name
Test status
Simulation time 51703527 ps
CPU time 0.78 seconds
Started Jul 05 04:36:23 PM PDT 24
Finished Jul 05 04:36:25 PM PDT 24
Peak memory 196848 kb
Host smart-ddaad4cc-247e-4949-8a74-966546bdcedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129341566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3129341566
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4132221254
Short name T283
Test name
Test status
Simulation time 58941709 ps
CPU time 1.28 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 197144 kb
Host smart-f042242f-a236-45dc-a085-f5330a2cf797
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132221254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4132221254
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1889966176
Short name T295
Test name
Test status
Simulation time 133330898 ps
CPU time 2.91 seconds
Started Jul 05 04:36:20 PM PDT 24
Finished Jul 05 04:36:23 PM PDT 24
Peak memory 198064 kb
Host smart-4da0c27f-e5d6-447f-915f-95ee73353247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889966176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1889966176
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.143863507
Short name T243
Test name
Test status
Simulation time 75741024 ps
CPU time 0.86 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 197240 kb
Host smart-0b2fbcc0-dd9c-465a-be49-7e4e52d57e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143863507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.143863507
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.549482002
Short name T251
Test name
Test status
Simulation time 27820054 ps
CPU time 0.98 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 197220 kb
Host smart-ca8d2d94-32bd-4918-9979-534c6c41a11b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549482002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.549482002
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1826833588
Short name T537
Test name
Test status
Simulation time 381325853 ps
CPU time 5.56 seconds
Started Jul 05 04:36:20 PM PDT 24
Finished Jul 05 04:36:26 PM PDT 24
Peak memory 198580 kb
Host smart-8379f44e-e6e2-4147-b9cf-fcae73bc064d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826833588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1826833588
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1009181596
Short name T494
Test name
Test status
Simulation time 39878585 ps
CPU time 1.25 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:24 PM PDT 24
Peak memory 197200 kb
Host smart-330980a0-2e57-4cc1-a272-ad73ad40edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009181596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1009181596
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1286376250
Short name T337
Test name
Test status
Simulation time 35147468 ps
CPU time 0.82 seconds
Started Jul 05 04:36:19 PM PDT 24
Finished Jul 05 04:36:21 PM PDT 24
Peak memory 195868 kb
Host smart-e6d2f6ab-d70b-454e-a427-d79b8f04d470
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286376250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1286376250
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.841146636
Short name T3
Test name
Test status
Simulation time 63432504885 ps
CPU time 35.28 seconds
Started Jul 05 04:36:20 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 198760 kb
Host smart-fd342ae7-57f7-462d-94c0-1bfc6a4d4b27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841146636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.841146636
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.2894862187
Short name T77
Test name
Test status
Simulation time 314557483646 ps
CPU time 1296.63 seconds
Started Jul 05 04:36:23 PM PDT 24
Finished Jul 05 04:58:01 PM PDT 24
Peak memory 198952 kb
Host smart-86ec085f-4651-4245-9759-37e7939b8033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2894862187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.2894862187
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2651338742
Short name T314
Test name
Test status
Simulation time 12829488 ps
CPU time 0.57 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 194684 kb
Host smart-774c93ef-01df-4712-b3b3-cf464f2a773a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651338742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2651338742
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1070882286
Short name T297
Test name
Test status
Simulation time 27143722 ps
CPU time 0.77 seconds
Started Jul 05 04:36:21 PM PDT 24
Finished Jul 05 04:36:22 PM PDT 24
Peak memory 196028 kb
Host smart-60c93fc4-e66d-497c-801b-90809a4c0b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070882286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1070882286
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1260013769
Short name T612
Test name
Test status
Simulation time 890345204 ps
CPU time 24.84 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:48 PM PDT 24
Peak memory 197472 kb
Host smart-c1f9eae3-adfa-4698-b0ab-80780cd7151f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260013769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1260013769
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2952355001
Short name T603
Test name
Test status
Simulation time 359397878 ps
CPU time 0.94 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:24 PM PDT 24
Peak memory 197392 kb
Host smart-e2a04ce5-e67e-4843-8546-91ca34a6c27c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952355001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2952355001
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1289922659
Short name T350
Test name
Test status
Simulation time 262764809 ps
CPU time 0.85 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:36:25 PM PDT 24
Peak memory 196096 kb
Host smart-bc32d04c-30ac-471e-8323-ce3fc0aa28d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289922659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1289922659
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1566777766
Short name T25
Test name
Test status
Simulation time 33325271 ps
CPU time 1.36 seconds
Started Jul 05 04:36:21 PM PDT 24
Finished Jul 05 04:36:23 PM PDT 24
Peak memory 197036 kb
Host smart-465b5c78-63ca-4b92-ba98-bd67887bdb06
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566777766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1566777766
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3280349424
Short name T613
Test name
Test status
Simulation time 430044907 ps
CPU time 3.14 seconds
Started Jul 05 04:36:21 PM PDT 24
Finished Jul 05 04:36:25 PM PDT 24
Peak memory 198672 kb
Host smart-161a0574-bd7d-430f-b392-879b52885178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280349424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3280349424
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.582637679
Short name T436
Test name
Test status
Simulation time 182869371 ps
CPU time 1 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:28 PM PDT 24
Peak memory 196632 kb
Host smart-fe239144-c385-43f0-812c-60889570ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582637679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.582637679
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4019478599
Short name T648
Test name
Test status
Simulation time 38770513 ps
CPU time 0.87 seconds
Started Jul 05 04:36:20 PM PDT 24
Finished Jul 05 04:36:21 PM PDT 24
Peak memory 197224 kb
Host smart-6d54c1b0-a89d-4a1b-9b56-4fd85b709196
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019478599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4019478599
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.682298624
Short name T51
Test name
Test status
Simulation time 471830605 ps
CPU time 5.33 seconds
Started Jul 05 04:36:21 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 198624 kb
Host smart-721aaf91-bc19-4400-9959-96f9113d059f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682298624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.682298624
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.233308865
Short name T544
Test name
Test status
Simulation time 133140186 ps
CPU time 1.14 seconds
Started Jul 05 04:36:23 PM PDT 24
Finished Jul 05 04:36:25 PM PDT 24
Peak memory 196220 kb
Host smart-4c107150-1dd1-4132-9206-02475734ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233308865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.233308865
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2102630478
Short name T396
Test name
Test status
Simulation time 282244013 ps
CPU time 1.12 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:28 PM PDT 24
Peak memory 196240 kb
Host smart-df9fe231-0432-4156-a2b5-231cb55f7a15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102630478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2102630478
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3128365981
Short name T634
Test name
Test status
Simulation time 11117640976 ps
CPU time 157.18 seconds
Started Jul 05 04:36:22 PM PDT 24
Finished Jul 05 04:39:01 PM PDT 24
Peak memory 198684 kb
Host smart-e5ee7413-5400-476f-bf0f-30bbac398eb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128365981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3128365981
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3299193720
Short name T22
Test name
Test status
Simulation time 147240818659 ps
CPU time 2991.48 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 05:26:24 PM PDT 24
Peak memory 198924 kb
Host smart-951a4586-419c-4106-afbb-dafee1122eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3299193720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3299193720
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1480129686
Short name T412
Test name
Test status
Simulation time 10970988 ps
CPU time 0.56 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:34 PM PDT 24
Peak memory 195272 kb
Host smart-b0d62118-463f-469a-a4d1-cba25991318d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480129686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1480129686
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2970474717
Short name T345
Test name
Test status
Simulation time 66888627 ps
CPU time 0.74 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 196676 kb
Host smart-c8c2165e-a2c6-4948-b7aa-dafde90b3fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970474717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2970474717
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1165826889
Short name T259
Test name
Test status
Simulation time 1617692781 ps
CPU time 22.37 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:51 PM PDT 24
Peak memory 196124 kb
Host smart-84d83fa0-e8ea-42bc-843a-bb49ac8f1181
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165826889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1165826889
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3063949528
Short name T378
Test name
Test status
Simulation time 62116346 ps
CPU time 0.86 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 197628 kb
Host smart-645ca2b1-a038-4492-bc82-f3ef988f1018
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063949528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3063949528
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1978226180
Short name T481
Test name
Test status
Simulation time 113693835 ps
CPU time 0.75 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:29 PM PDT 24
Peak memory 196200 kb
Host smart-08633196-ef1c-489e-990a-8fac370a52c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978226180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1978226180
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3842798376
Short name T551
Test name
Test status
Simulation time 227103763 ps
CPU time 2.39 seconds
Started Jul 05 04:36:23 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 197904 kb
Host smart-84ff2677-dd4d-4731-9227-3cc75dba5efa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842798376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3842798376
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.195567964
Short name T170
Test name
Test status
Simulation time 196106377 ps
CPU time 1.38 seconds
Started Jul 05 04:36:24 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 196768 kb
Host smart-5b6dcf95-e6c6-47a0-8fc9-d41ae4349579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195567964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
195567964
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.23287650
Short name T384
Test name
Test status
Simulation time 57529509 ps
CPU time 1.23 seconds
Started Jul 05 04:36:30 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 197388 kb
Host smart-028dd9af-8733-48fb-9390-dda4b2689c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23287650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.23287650
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1370300343
Short name T380
Test name
Test status
Simulation time 34237971 ps
CPU time 0.86 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:36 PM PDT 24
Peak memory 197416 kb
Host smart-a01dcd6d-fb62-42d0-b132-40b2ece75fb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370300343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1370300343
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2949209120
Short name T549
Test name
Test status
Simulation time 724319305 ps
CPU time 5.8 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 198684 kb
Host smart-7c077645-5443-475b-98e4-339afe1bd8f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949209120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2949209120
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.149242877
Short name T358
Test name
Test status
Simulation time 43758505 ps
CPU time 0.93 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 197236 kb
Host smart-837d4f7f-b937-4ff2-91eb-422cc78beb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149242877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.149242877
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2815907738
Short name T467
Test name
Test status
Simulation time 131245614 ps
CPU time 0.98 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 196452 kb
Host smart-747d5f8b-edba-405c-9151-5f0963fcf02b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815907738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2815907738
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3425925631
Short name T248
Test name
Test status
Simulation time 39446878337 ps
CPU time 137.57 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:38:46 PM PDT 24
Peak memory 198840 kb
Host smart-2d874fea-8da1-4f66-933e-b52b1f3168d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425925631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3425925631
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.315466534
Short name T373
Test name
Test status
Simulation time 14548826 ps
CPU time 0.56 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 194596 kb
Host smart-cbf293a0-aa71-470c-89da-283ad71c044d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315466534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.315466534
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3166972206
Short name T123
Test name
Test status
Simulation time 41009858 ps
CPU time 0.86 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:30 PM PDT 24
Peak memory 196056 kb
Host smart-f0b3e5bf-4c34-4e97-a3fc-28e9bce523cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166972206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3166972206
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2158381202
Short name T298
Test name
Test status
Simulation time 315075057 ps
CPU time 15.42 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:43 PM PDT 24
Peak memory 196996 kb
Host smart-059f0cd6-d7fe-4be0-a3f3-94b04d372b3e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158381202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2158381202
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.867611668
Short name T352
Test name
Test status
Simulation time 265896071 ps
CPU time 0.86 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:29 PM PDT 24
Peak memory 197440 kb
Host smart-e9cd7811-bb73-41f9-bba0-e9d162c65c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867611668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.867611668
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.281439562
Short name T392
Test name
Test status
Simulation time 79231705 ps
CPU time 1.19 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 197680 kb
Host smart-8fd07d4d-bfc9-43d5-bcc0-6ed5164a6cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281439562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.281439562
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.84865509
Short name T125
Test name
Test status
Simulation time 361839749 ps
CPU time 3.46 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 198712 kb
Host smart-f7983ee6-f8f7-43b7-a05f-8bb0f86f5645
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84865509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.gpio_intr_with_filter_rand_intr_event.84865509
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1865039670
Short name T317
Test name
Test status
Simulation time 70946166 ps
CPU time 2.17 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 198684 kb
Host smart-52ccad51-312e-4653-9cb2-64f21de1a746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865039670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1865039670
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4161628460
Short name T534
Test name
Test status
Simulation time 34764972 ps
CPU time 1.19 seconds
Started Jul 05 04:36:25 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 197524 kb
Host smart-c4e5dcab-055b-4e31-b87d-ebdc8ffdbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161628460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4161628460
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3620873137
Short name T187
Test name
Test status
Simulation time 103776498 ps
CPU time 1.13 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 198744 kb
Host smart-14b5ad5c-c283-4a49-88d9-004162b6d962
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620873137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3620873137
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1342667369
Short name T482
Test name
Test status
Simulation time 440620322 ps
CPU time 5.54 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 198628 kb
Host smart-41e43574-f37c-4588-9994-989bf4f330c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342667369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1342667369
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2565688313
Short name T136
Test name
Test status
Simulation time 48064929 ps
CPU time 1.41 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 197388 kb
Host smart-b9d84a3f-6747-4c47-89cc-3dff5618f646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565688313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2565688313
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2885498182
Short name T434
Test name
Test status
Simulation time 39258265 ps
CPU time 0.88 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:30 PM PDT 24
Peak memory 197228 kb
Host smart-327d19e2-98d4-43ad-a2c8-0721e9c191a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885498182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2885498182
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3833162721
Short name T278
Test name
Test status
Simulation time 3355190064 ps
CPU time 23.97 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 198784 kb
Host smart-691f47d5-1b8a-4be4-adb5-6e3e1b116322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833162721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3833162721
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.258478082
Short name T360
Test name
Test status
Simulation time 41070731 ps
CPU time 0.56 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 194692 kb
Host smart-2f6dc2a8-a5e4-4d24-8a1d-3d3a8a1e4c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258478082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.258478082
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.194044544
Short name T223
Test name
Test status
Simulation time 44355953 ps
CPU time 0.87 seconds
Started Jul 05 04:35:49 PM PDT 24
Finished Jul 05 04:35:51 PM PDT 24
Peak memory 197016 kb
Host smart-90238a14-c2d4-40a1-a522-a95326324123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194044544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.194044544
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2964831152
Short name T564
Test name
Test status
Simulation time 261110484 ps
CPU time 8.83 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:54 PM PDT 24
Peak memory 196860 kb
Host smart-77906834-73d8-44e9-b68f-50cd57469e2c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964831152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2964831152
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1892582445
Short name T620
Test name
Test status
Simulation time 141835256 ps
CPU time 0.82 seconds
Started Jul 05 04:35:38 PM PDT 24
Finished Jul 05 04:35:40 PM PDT 24
Peak memory 197364 kb
Host smart-d8593dde-f8ba-4db3-8ead-1ac04a03117f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892582445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1892582445
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3226903623
Short name T338
Test name
Test status
Simulation time 909776342 ps
CPU time 1.29 seconds
Started Jul 05 04:35:39 PM PDT 24
Finished Jul 05 04:35:41 PM PDT 24
Peak memory 196844 kb
Host smart-3294253e-c73d-4bc9-8022-385fd85c9bd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226903623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3226903623
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3194898377
Short name T667
Test name
Test status
Simulation time 521191871 ps
CPU time 3.44 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:49 PM PDT 24
Peak memory 198688 kb
Host smart-6b31b22e-45f1-4699-b2a3-bc8886d929d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194898377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3194898377
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3368044305
Short name T639
Test name
Test status
Simulation time 160190701 ps
CPU time 2.35 seconds
Started Jul 05 04:35:49 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 196424 kb
Host smart-77f85cbd-8ead-4ead-9355-204a985bbf85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368044305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3368044305
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1339769629
Short name T33
Test name
Test status
Simulation time 54650857 ps
CPU time 0.72 seconds
Started Jul 05 04:35:48 PM PDT 24
Finished Jul 05 04:35:49 PM PDT 24
Peak memory 196040 kb
Host smart-0c00bf9f-fec1-4cd6-b735-d8ed7dcbedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339769629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1339769629
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3340295645
Short name T664
Test name
Test status
Simulation time 163347193 ps
CPU time 0.94 seconds
Started Jul 05 04:35:38 PM PDT 24
Finished Jul 05 04:35:39 PM PDT 24
Peak memory 197388 kb
Host smart-ad807b01-5be9-45dd-a28e-b7f362e7daa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340295645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3340295645
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4043300520
Short name T379
Test name
Test status
Simulation time 118650786 ps
CPU time 2.08 seconds
Started Jul 05 04:35:47 PM PDT 24
Finished Jul 05 04:35:50 PM PDT 24
Peak memory 198628 kb
Host smart-811d81ed-139e-4c7c-87e5-d255c1edbda4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043300520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4043300520
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2630971525
Short name T58
Test name
Test status
Simulation time 153021916 ps
CPU time 0.86 seconds
Started Jul 05 04:35:49 PM PDT 24
Finished Jul 05 04:35:51 PM PDT 24
Peak memory 214168 kb
Host smart-2028d3f0-5e21-43d6-8dea-ce79d1f3c30c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630971525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2630971525
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3821380188
Short name T411
Test name
Test status
Simulation time 637941621 ps
CPU time 0.99 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:45 PM PDT 24
Peak memory 196520 kb
Host smart-fdb6bda9-13d8-42ec-9496-8bf4ac86f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821380188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3821380188
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4072567651
Short name T428
Test name
Test status
Simulation time 103018224 ps
CPU time 0.88 seconds
Started Jul 05 04:35:41 PM PDT 24
Finished Jul 05 04:35:42 PM PDT 24
Peak memory 197036 kb
Host smart-37384f75-29ce-4c12-9ec7-37043f3ecde0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072567651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4072567651
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1569893270
Short name T366
Test name
Test status
Simulation time 4377540010 ps
CPU time 102.15 seconds
Started Jul 05 04:35:50 PM PDT 24
Finished Jul 05 04:37:33 PM PDT 24
Peak memory 198664 kb
Host smart-de341e66-f348-4c14-adfa-c0e9ae141d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569893270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1569893270
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2819667560
Short name T162
Test name
Test status
Simulation time 36952199 ps
CPU time 0.6 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 194684 kb
Host smart-a105920d-26c4-4f2e-8a2e-340455dc9578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819667560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2819667560
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3226048791
Short name T164
Test name
Test status
Simulation time 68800253 ps
CPU time 0.7 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 194864 kb
Host smart-69a23dd3-629f-4d52-8f48-226df294943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226048791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3226048791
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1756024645
Short name T181
Test name
Test status
Simulation time 96845250 ps
CPU time 4.75 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 196924 kb
Host smart-8f63aa9f-f910-422f-835b-5f6432d1d3a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756024645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1756024645
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.135958721
Short name T635
Test name
Test status
Simulation time 108278063 ps
CPU time 1 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 198700 kb
Host smart-e202aff1-7051-4779-a1e6-bf7eb140b2a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135958721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.135958721
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3708356798
Short name T368
Test name
Test status
Simulation time 242877239 ps
CPU time 1.11 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 196520 kb
Host smart-7c8cad38-45e7-4ed3-b31c-1517ed5589f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708356798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3708356798
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.416010566
Short name T210
Test name
Test status
Simulation time 75062251 ps
CPU time 1.64 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 198712 kb
Host smart-27d820ef-da05-49cb-ae27-056cd3786eae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416010566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.416010566
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1309119328
Short name T704
Test name
Test status
Simulation time 469946555 ps
CPU time 2.81 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 197804 kb
Host smart-2952acba-9290-41fe-b0e3-e36784794c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309119328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1309119328
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.433076864
Short name T594
Test name
Test status
Simulation time 478263475 ps
CPU time 0.99 seconds
Started Jul 05 04:36:30 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 196520 kb
Host smart-84b22590-5286-4760-98dd-754631cc702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433076864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.433076864
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1669886397
Short name T604
Test name
Test status
Simulation time 75055478 ps
CPU time 1.34 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 197568 kb
Host smart-cb3b14ae-c043-40ab-b21e-50e9740e6bca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669886397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1669886397
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.453612557
Short name T359
Test name
Test status
Simulation time 353795367 ps
CPU time 2.95 seconds
Started Jul 05 04:36:30 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 198652 kb
Host smart-e91d73a7-5754-4280-9023-6858f7f32962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453612557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.453612557
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4060165097
Short name T62
Test name
Test status
Simulation time 157000364 ps
CPU time 1.27 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 198252 kb
Host smart-3de432f4-886d-435c-bf3d-0808ad86e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060165097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4060165097
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1287423374
Short name T247
Test name
Test status
Simulation time 138562057 ps
CPU time 1.27 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 197576 kb
Host smart-56a5389e-44e3-40ae-bc33-024bed7aa695
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287423374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1287423374
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.429827675
Short name T258
Test name
Test status
Simulation time 964589907 ps
CPU time 25.99 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 198672 kb
Host smart-58f2596c-580b-4016-b048-76ec7f1a3f0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429827675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.429827675
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3281558460
Short name T150
Test name
Test status
Simulation time 12491389 ps
CPU time 0.58 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:34 PM PDT 24
Peak memory 194900 kb
Host smart-032df9ae-7add-4864-8dc1-05ba48e54e76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281558460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3281558460
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.404338338
Short name T165
Test name
Test status
Simulation time 38668465 ps
CPU time 0.79 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:30 PM PDT 24
Peak memory 195820 kb
Host smart-a1cec4fb-b7de-4fb9-afe6-0c5423cf2331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404338338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.404338338
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4015229022
Short name T371
Test name
Test status
Simulation time 309530318 ps
CPU time 3.58 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 196660 kb
Host smart-727ba22a-3e1e-4cb4-85fa-190fe0f96a0b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015229022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4015229022
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4040633745
Short name T504
Test name
Test status
Simulation time 63175205 ps
CPU time 0.64 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:29 PM PDT 24
Peak memory 195956 kb
Host smart-7c20f1b3-6964-4977-b3ad-c1d106a48205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040633745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4040633745
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1183400102
Short name T511
Test name
Test status
Simulation time 310564435 ps
CPU time 1.36 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 198704 kb
Host smart-3620f534-a73a-4e77-8f7f-ed2637c23d0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183400102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1183400102
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.908398711
Short name T502
Test name
Test status
Simulation time 116694556 ps
CPU time 1.36 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:34 PM PDT 24
Peak memory 197632 kb
Host smart-dfad07b1-ed87-4832-94f3-053ff1f490c2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908398711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.908398711
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1470150383
Short name T266
Test name
Test status
Simulation time 117061982 ps
CPU time 3.24 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 198012 kb
Host smart-a2e55423-e136-468c-9e01-c8bb8f8f7852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470150383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1470150383
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3529002533
Short name T579
Test name
Test status
Simulation time 37940947 ps
CPU time 0.7 seconds
Started Jul 05 04:36:24 PM PDT 24
Finished Jul 05 04:36:26 PM PDT 24
Peak memory 195724 kb
Host smart-b30e755a-2084-4fc3-a5f3-f110a3e72e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529002533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3529002533
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4149022300
Short name T38
Test name
Test status
Simulation time 28874058 ps
CPU time 0.98 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:36 PM PDT 24
Peak memory 196480 kb
Host smart-6e95281f-cd47-40b1-9fa7-9d9415985b57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149022300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.4149022300
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2284886667
Short name T117
Test name
Test status
Simulation time 336538968 ps
CPU time 3.47 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 198020 kb
Host smart-8ed3bcae-c173-41c7-9486-08d17c4bc681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284886667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2284886667
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2462039819
Short name T684
Test name
Test status
Simulation time 35805134 ps
CPU time 1.09 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:32 PM PDT 24
Peak memory 196424 kb
Host smart-bc433b95-c070-4aff-828d-40f782810495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462039819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2462039819
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.863237884
Short name T442
Test name
Test status
Simulation time 382923101 ps
CPU time 1.04 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 196412 kb
Host smart-85d96676-50fb-4241-9f41-fffa02ff1f50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863237884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.863237884
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.508381209
Short name T21
Test name
Test status
Simulation time 66259248585 ps
CPU time 195.69 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:39:45 PM PDT 24
Peak memory 198792 kb
Host smart-dfa44b4c-3a1c-4499-b795-a8001163dee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508381209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.508381209
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3493011611
Short name T212
Test name
Test status
Simulation time 13687789 ps
CPU time 0.56 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 195384 kb
Host smart-77a670f3-a85b-4aa2-9ea5-f8d219284ca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493011611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3493011611
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.543105938
Short name T23
Test name
Test status
Simulation time 39906927 ps
CPU time 0.72 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 196684 kb
Host smart-52314610-1d19-49f5-a58e-8a7f4d400e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543105938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.543105938
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.314643829
Short name T528
Test name
Test status
Simulation time 433793909 ps
CPU time 21.91 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 197620 kb
Host smart-ff3b20cc-7795-434e-89f1-3b3a074742c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314643829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.314643829
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.4209972127
Short name T474
Test name
Test status
Simulation time 140001637 ps
CPU time 0.86 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 196692 kb
Host smart-b8d0c0cb-21ed-423d-89ee-2588066470e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209972127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.4209972127
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2609521714
Short name T468
Test name
Test status
Simulation time 43266274 ps
CPU time 1.27 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 198644 kb
Host smart-350d3ae0-a046-4296-88fe-d2e5a088eb12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609521714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2609521714
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1742723570
Short name T329
Test name
Test status
Simulation time 97701226 ps
CPU time 2.01 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 198732 kb
Host smart-71d83267-3321-4431-8e4a-5d47a7488464
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742723570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1742723570
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.519662425
Short name T645
Test name
Test status
Simulation time 109288275 ps
CPU time 2.9 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 196504 kb
Host smart-2d338b31-4d06-487c-ae48-7f75034e230b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519662425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
519662425
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.422524615
Short name T539
Test name
Test status
Simulation time 19688101 ps
CPU time 0.79 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 197188 kb
Host smart-fff9d235-56f7-4d9d-8118-939d8d9498a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422524615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.422524615
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1130086234
Short name T696
Test name
Test status
Simulation time 145206966 ps
CPU time 1.26 seconds
Started Jul 05 04:36:27 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 197184 kb
Host smart-cbd31934-abc6-4d93-8743-28245ae8aa35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130086234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1130086234
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1689188418
Short name T553
Test name
Test status
Simulation time 828807242 ps
CPU time 3.52 seconds
Started Jul 05 04:36:26 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 198600 kb
Host smart-eb6243ef-ee15-425c-8142-5c6ec35cb3ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689188418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1689188418
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.875536349
Short name T325
Test name
Test status
Simulation time 803464993 ps
CPU time 1.09 seconds
Started Jul 05 04:36:29 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 196244 kb
Host smart-f994c5cc-b17d-45d8-8ad3-09854eb26d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875536349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.875536349
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3964487063
Short name T305
Test name
Test status
Simulation time 91750848 ps
CPU time 1.42 seconds
Started Jul 05 04:36:28 PM PDT 24
Finished Jul 05 04:36:33 PM PDT 24
Peak memory 198684 kb
Host smart-d555ee26-4410-4895-b6d3-6b63fc25dba5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964487063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3964487063
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.672915212
Short name T386
Test name
Test status
Simulation time 9591301457 ps
CPU time 120.3 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:38:38 PM PDT 24
Peak memory 198780 kb
Host smart-6c785c32-614b-43cd-bf00-90bbcd474c12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672915212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.672915212
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.352656275
Short name T488
Test name
Test status
Simulation time 28671093 ps
CPU time 0.6 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:36 PM PDT 24
Peak memory 194832 kb
Host smart-8643295d-7bd7-4d5e-97c5-9ec5b793dc6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352656275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.352656275
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.669893801
Short name T437
Test name
Test status
Simulation time 38694693 ps
CPU time 0.83 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 196644 kb
Host smart-091a25ed-fdbe-41e7-83f6-39128d16c1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669893801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.669893801
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2271136181
Short name T376
Test name
Test status
Simulation time 331176066 ps
CPU time 4.69 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:42 PM PDT 24
Peak memory 196636 kb
Host smart-a26a2f9e-bd46-42a7-9075-7ad04496ceb2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271136181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2271136181
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2995373711
Short name T637
Test name
Test status
Simulation time 120092085 ps
CPU time 0.91 seconds
Started Jul 05 04:36:38 PM PDT 24
Finished Jul 05 04:36:41 PM PDT 24
Peak memory 197464 kb
Host smart-266233de-a511-4953-b998-c7f92fd95d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995373711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2995373711
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.21105036
Short name T215
Test name
Test status
Simulation time 207614100 ps
CPU time 1.27 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 196452 kb
Host smart-7079dfed-ab90-4dd7-8bcc-8721faf3399b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.21105036
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3492348925
Short name T312
Test name
Test status
Simulation time 242848198 ps
CPU time 0.96 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:46 PM PDT 24
Peak memory 197600 kb
Host smart-a1bbda3a-1938-432b-85c1-799414c58afb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492348925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3492348925
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.713439754
Short name T591
Test name
Test status
Simulation time 349033348 ps
CPU time 3.29 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:40 PM PDT 24
Peak memory 197752 kb
Host smart-36b0ea39-8b6f-415f-b6bd-b9455c3e7082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713439754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
713439754
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3702061038
Short name T207
Test name
Test status
Simulation time 37091163 ps
CPU time 0.78 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 196188 kb
Host smart-20e5fb22-333b-4212-b387-9c673d1d95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702061038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3702061038
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.495793329
Short name T209
Test name
Test status
Simulation time 140663620 ps
CPU time 0.88 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 197220 kb
Host smart-7f17a0e1-c360-4f63-b1f4-f191253e33b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495793329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.495793329
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.273079483
Short name T680
Test name
Test status
Simulation time 794495735 ps
CPU time 2.23 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 198596 kb
Host smart-97b620b1-8c24-4388-a6b0-14178bb755b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273079483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.273079483
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1377767228
Short name T711
Test name
Test status
Simulation time 126157340 ps
CPU time 0.92 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 196924 kb
Host smart-43f640db-ce6d-4376-96b5-ac7fa0afb118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377767228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1377767228
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3109224703
Short name T410
Test name
Test status
Simulation time 191139480 ps
CPU time 1.12 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 196936 kb
Host smart-d473dcae-127f-4a09-a15f-e75c461adb41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109224703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3109224703
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3875781278
Short name T346
Test name
Test status
Simulation time 7450860450 ps
CPU time 40.13 seconds
Started Jul 05 04:36:43 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 198872 kb
Host smart-3e41fced-24df-4053-bbfc-ee83b0fcfd20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875781278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3875781278
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3713830618
Short name T8
Test name
Test status
Simulation time 53202443930 ps
CPU time 736.66 seconds
Started Jul 05 04:36:30 PM PDT 24
Finished Jul 05 04:48:50 PM PDT 24
Peak memory 198920 kb
Host smart-2bb5aa5b-bf70-42e2-985d-fbc183505e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3713830618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3713830618
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.118114111
Short name T661
Test name
Test status
Simulation time 14738096 ps
CPU time 0.6 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:36 PM PDT 24
Peak memory 195264 kb
Host smart-05a2ab88-e4ca-45ce-a1e8-b770611becc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118114111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.118114111
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2595317538
Short name T683
Test name
Test status
Simulation time 27112049 ps
CPU time 0.62 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 195272 kb
Host smart-4c8ac77b-cc30-486c-9bb1-983405aff179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595317538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2595317538
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.4156194336
Short name T454
Test name
Test status
Simulation time 2936593343 ps
CPU time 21.52 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:37:00 PM PDT 24
Peak memory 197140 kb
Host smart-1c5e4550-b4e1-44e9-ad22-1c5baf00f5ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156194336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.4156194336
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.441871583
Short name T292
Test name
Test status
Simulation time 64836542 ps
CPU time 0.66 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:35 PM PDT 24
Peak memory 195056 kb
Host smart-f71551f5-cc2b-49c6-91e3-1204545350d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441871583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.441871583
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2017881315
Short name T213
Test name
Test status
Simulation time 47064894 ps
CPU time 0.87 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 196820 kb
Host smart-446a55a3-3e39-4aa7-b0a9-502b3f903600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017881315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2017881315
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3172215722
Short name T536
Test name
Test status
Simulation time 148210101 ps
CPU time 3.1 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 197904 kb
Host smart-6bd6cec3-27f4-48f8-a92e-1f4651dd75fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172215722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3172215722
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3419655824
Short name T176
Test name
Test status
Simulation time 535360718 ps
CPU time 1.95 seconds
Started Jul 05 04:36:30 PM PDT 24
Finished Jul 05 04:36:36 PM PDT 24
Peak memory 197880 kb
Host smart-e3743424-bdc9-4ea4-b0e7-f384355a530c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419655824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3419655824
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3379650182
Short name T374
Test name
Test status
Simulation time 120476351 ps
CPU time 1.31 seconds
Started Jul 05 04:36:38 PM PDT 24
Finished Jul 05 04:36:41 PM PDT 24
Peak memory 197696 kb
Host smart-9edaf4ce-3e7d-44fe-a0af-4f5fc5ab236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379650182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3379650182
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3043849937
Short name T497
Test name
Test status
Simulation time 17930582 ps
CPU time 0.69 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 195636 kb
Host smart-1818d8be-4283-448d-a7af-22bca7413b34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043849937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3043849937
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1921102420
Short name T5
Test name
Test status
Simulation time 925542720 ps
CPU time 5.6 seconds
Started Jul 05 04:36:46 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 198624 kb
Host smart-b1266566-0ce4-45f6-9aeb-e67991880c02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921102420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1921102420
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1065953323
Short name T15
Test name
Test status
Simulation time 65395889 ps
CPU time 1.03 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 196420 kb
Host smart-9c2435d9-ccb3-491f-9598-17ff0726d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065953323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1065953323
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.349579563
Short name T475
Test name
Test status
Simulation time 25953498 ps
CPU time 0.87 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 196988 kb
Host smart-079eb455-2786-40af-acc9-0ba97c5873fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349579563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.349579563
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.700574103
Short name T499
Test name
Test status
Simulation time 30735852209 ps
CPU time 210.68 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:40:07 PM PDT 24
Peak memory 198732 kb
Host smart-98d91db8-4a0d-4c4a-a57c-37b7bb070600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700574103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.700574103
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3791463018
Short name T107
Test name
Test status
Simulation time 66386175770 ps
CPU time 450.8 seconds
Started Jul 05 04:36:39 PM PDT 24
Finished Jul 05 04:44:11 PM PDT 24
Peak memory 198856 kb
Host smart-9a14e63b-90a0-4969-bbc1-7d77c3194988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3791463018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3791463018
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2893825538
Short name T530
Test name
Test status
Simulation time 33983297 ps
CPU time 0.57 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 194700 kb
Host smart-4692796e-72ee-4605-bdb1-1f3dc5c2f6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893825538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2893825538
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1777992889
Short name T299
Test name
Test status
Simulation time 27932599 ps
CPU time 0.84 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:36 PM PDT 24
Peak memory 197116 kb
Host smart-661b6a9d-5755-4483-9f56-56ac2e215cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777992889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1777992889
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3463287027
Short name T308
Test name
Test status
Simulation time 2083558586 ps
CPU time 9.82 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:54 PM PDT 24
Peak memory 197492 kb
Host smart-b50f5af3-6a78-44bd-a502-695afc89bfd2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463287027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3463287027
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3526841101
Short name T381
Test name
Test status
Simulation time 42853183 ps
CPU time 0.7 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 195436 kb
Host smart-5f94cff1-9a85-4093-866c-f1efc6d026f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526841101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3526841101
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2677150504
Short name T245
Test name
Test status
Simulation time 35580480 ps
CPU time 0.67 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 194856 kb
Host smart-a58c603c-f8f4-4826-ad35-10c210728d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677150504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2677150504
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3326410587
Short name T26
Test name
Test status
Simulation time 53691871 ps
CPU time 1.98 seconds
Started Jul 05 04:36:42 PM PDT 24
Finished Jul 05 04:36:45 PM PDT 24
Peak memory 198752 kb
Host smart-a6de26b1-6856-49f6-8588-769f2bf71698
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326410587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3326410587
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.559059201
Short name T703
Test name
Test status
Simulation time 40671213 ps
CPU time 1.07 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 196348 kb
Host smart-aafc5360-8e79-49e8-b476-06590d123fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559059201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
559059201
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1628647844
Short name T14
Test name
Test status
Simulation time 73313039 ps
CPU time 1.29 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:36:40 PM PDT 24
Peak memory 197600 kb
Host smart-cc2ffd4f-96ec-4c56-8b89-0ec343cdfd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628647844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1628647844
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3692371576
Short name T264
Test name
Test status
Simulation time 14284244 ps
CPU time 0.64 seconds
Started Jul 05 04:36:32 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 194868 kb
Host smart-aec8e297-ef5b-43ac-a9f3-55e8fb194c3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692371576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3692371576
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.655051514
Short name T479
Test name
Test status
Simulation time 508535849 ps
CPU time 2.15 seconds
Started Jul 05 04:36:39 PM PDT 24
Finished Jul 05 04:36:42 PM PDT 24
Peak memory 198612 kb
Host smart-96571f86-b4ba-421d-a08f-836236849789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655051514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.655051514
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4077866092
Short name T260
Test name
Test status
Simulation time 313032346 ps
CPU time 1.37 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 197512 kb
Host smart-87abe244-415e-4232-93df-453489c47767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077866092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4077866092
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2024806866
Short name T143
Test name
Test status
Simulation time 25181015 ps
CPU time 0.69 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:38 PM PDT 24
Peak memory 195460 kb
Host smart-16f0b46d-9476-41f3-9e91-86ea825055fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024806866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2024806866
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2118641221
Short name T203
Test name
Test status
Simulation time 28080952572 ps
CPU time 223.61 seconds
Started Jul 05 04:36:33 PM PDT 24
Finished Jul 05 04:40:21 PM PDT 24
Peak memory 198860 kb
Host smart-3f994d4f-0834-4c05-bb85-3536030ffc49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118641221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2118641221
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2121650202
Short name T63
Test name
Test status
Simulation time 13791619 ps
CPU time 0.61 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:00 PM PDT 24
Peak memory 196412 kb
Host smart-81c63082-6371-43ff-ae8d-71e814801146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121650202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2121650202
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3180953087
Short name T331
Test name
Test status
Simulation time 160072057 ps
CPU time 0.85 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 196004 kb
Host smart-16da69f8-ebc8-413b-a1d8-510918f54c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180953087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3180953087
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1856603914
Short name T596
Test name
Test status
Simulation time 628387591 ps
CPU time 16.03 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 196984 kb
Host smart-0f43b7b6-2d11-4ec0-b65f-9b64a443aed9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856603914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1856603914
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.3470656283
Short name T9
Test name
Test status
Simulation time 339787903 ps
CPU time 1.02 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:46 PM PDT 24
Peak memory 197324 kb
Host smart-74a0b9da-2e84-4b92-a145-c2a4690512d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470656283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.3470656283
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2376277455
Short name T688
Test name
Test status
Simulation time 71860118 ps
CPU time 0.68 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 196152 kb
Host smart-5661091c-5b5a-44a1-85a4-7822439696f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376277455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2376277455
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.403698795
Short name T413
Test name
Test status
Simulation time 25499111 ps
CPU time 0.99 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:46 PM PDT 24
Peak memory 196796 kb
Host smart-4a310fe3-d78b-4460-83a0-c04928496311
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403698795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.403698795
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2842395335
Short name T180
Test name
Test status
Simulation time 442374342 ps
CPU time 2.73 seconds
Started Jul 05 04:36:31 PM PDT 24
Finished Jul 05 04:36:37 PM PDT 24
Peak memory 198724 kb
Host smart-1c4c9ec8-d718-439a-9717-5446494394a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842395335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2842395335
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2770330114
Short name T395
Test name
Test status
Simulation time 41672324 ps
CPU time 1.43 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:46 PM PDT 24
Peak memory 197504 kb
Host smart-9df16383-f51a-465f-a72e-942752d85949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770330114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2770330114
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1771417329
Short name T593
Test name
Test status
Simulation time 36404656 ps
CPU time 0.99 seconds
Started Jul 05 04:36:35 PM PDT 24
Finished Jul 05 04:36:40 PM PDT 24
Peak memory 196540 kb
Host smart-fa45c4a3-955f-4cba-a6a6-849fc6b33a26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771417329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1771417329
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.998549270
Short name T560
Test name
Test status
Simulation time 342926626 ps
CPU time 2.44 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:54 PM PDT 24
Peak memory 198596 kb
Host smart-fe376ce7-2384-4aad-bf91-617493a3f288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998549270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.998549270
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.106600575
Short name T214
Test name
Test status
Simulation time 84275253 ps
CPU time 1.36 seconds
Started Jul 05 04:36:34 PM PDT 24
Finished Jul 05 04:36:39 PM PDT 24
Peak memory 196200 kb
Host smart-c0541ecb-7a54-4379-9272-536e4c5129d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106600575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.106600575
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4076510728
Short name T510
Test name
Test status
Simulation time 292955183 ps
CPU time 1.26 seconds
Started Jul 05 04:36:38 PM PDT 24
Finished Jul 05 04:36:41 PM PDT 24
Peak memory 197416 kb
Host smart-f3cada83-9b31-466c-8db6-2400b81153db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076510728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4076510728
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.4063209301
Short name T419
Test name
Test status
Simulation time 7791422385 ps
CPU time 187.03 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:39:56 PM PDT 24
Peak memory 198684 kb
Host smart-d012338c-2b22-4e69-a775-ca8244d14ef7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063209301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.4063209301
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1389362301
Short name T490
Test name
Test status
Simulation time 384076933051 ps
CPU time 1095.23 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:55:07 PM PDT 24
Peak memory 198940 kb
Host smart-9cb5188d-056b-4af0-b2f8-77855b10528b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1389362301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1389362301
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1682755287
Short name T422
Test name
Test status
Simulation time 22590594 ps
CPU time 0.55 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:52 PM PDT 24
Peak memory 194580 kb
Host smart-1f243c96-5054-4641-8512-d880a05a34b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682755287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1682755287
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3625353485
Short name T686
Test name
Test status
Simulation time 29211100 ps
CPU time 0.72 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:36:54 PM PDT 24
Peak memory 196680 kb
Host smart-e049b407-95cb-44c9-bacf-6224b152550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625353485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3625353485
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2449385761
Short name T698
Test name
Test status
Simulation time 3660725015 ps
CPU time 25.65 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 197600 kb
Host smart-68a94a97-1b64-4756-b7da-402fc29f8d21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449385761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2449385761
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.105288115
Short name T440
Test name
Test status
Simulation time 187980608 ps
CPU time 0.84 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 196560 kb
Host smart-3bc1f097-8fd5-4c01-8bff-48d7680fcc12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105288115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.105288115
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3322561910
Short name T365
Test name
Test status
Simulation time 115787915 ps
CPU time 1.28 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 196416 kb
Host smart-cfaf0e07-4d78-4fd8-8bfe-b601a73d943c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322561910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3322561910
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3880282579
Short name T142
Test name
Test status
Simulation time 90467911 ps
CPU time 3.29 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 198656 kb
Host smart-2ebb7cfd-ebde-42c1-8811-8efc88218ae4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880282579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3880282579
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.4089236370
Short name T158
Test name
Test status
Simulation time 256041756 ps
CPU time 1.71 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:47 PM PDT 24
Peak memory 196692 kb
Host smart-9ac8bdb7-889c-43d4-9536-7080e07ad758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089236370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.4089236370
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.921677230
Short name T306
Test name
Test status
Simulation time 96509856 ps
CPU time 0.75 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 195940 kb
Host smart-b2854d94-2f3b-413e-b2b2-2a754088377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921677230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.921677230
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2513568570
Short name T538
Test name
Test status
Simulation time 53243450 ps
CPU time 1.16 seconds
Started Jul 05 04:36:46 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 196528 kb
Host smart-aa5af36f-0602-4696-b17a-cd24eb274f39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513568570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2513568570
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3647864156
Short name T152
Test name
Test status
Simulation time 79086163 ps
CPU time 3.21 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 198696 kb
Host smart-6935945b-34a0-4246-a067-64b330cbeb76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647864156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3647864156
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1060305839
Short name T632
Test name
Test status
Simulation time 49270016 ps
CPU time 0.81 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 196100 kb
Host smart-a1dfb4f4-16a2-48f4-a4b1-0156360761b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060305839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1060305839
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3115716315
Short name T173
Test name
Test status
Simulation time 133514108 ps
CPU time 1.24 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 197580 kb
Host smart-207d179f-81c8-44a4-a45e-efc13178d872
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115716315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3115716315
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3524403389
Short name T649
Test name
Test status
Simulation time 2936745705 ps
CPU time 71.89 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:38:02 PM PDT 24
Peak memory 198844 kb
Host smart-eb24b97b-10c3-493b-8c90-3931fe7012dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524403389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3524403389
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3610791772
Short name T186
Test name
Test status
Simulation time 11031055 ps
CPU time 0.56 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:50 PM PDT 24
Peak memory 193484 kb
Host smart-2f14acb5-9479-4e08-ad3b-ebe53300b0d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610791772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3610791772
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.32571878
Short name T73
Test name
Test status
Simulation time 91142090 ps
CPU time 0.85 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 197188 kb
Host smart-25d0acd2-202d-437e-85b9-cb637c27c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32571878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.32571878
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.38259288
Short name T277
Test name
Test status
Simulation time 987071939 ps
CPU time 15.58 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:37:06 PM PDT 24
Peak memory 198692 kb
Host smart-738b691b-c2d1-4079-8e5f-993ebb3e40d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38259288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stress
.38259288
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.283956014
Short name T524
Test name
Test status
Simulation time 227821271 ps
CPU time 0.95 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 198356 kb
Host smart-982d392d-0493-4e1c-a529-14ce99f2bbe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283956014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.283956014
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2096656459
Short name T587
Test name
Test status
Simulation time 504941413 ps
CPU time 1.19 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:36:52 PM PDT 24
Peak memory 197236 kb
Host smart-833bdf78-897d-4215-bfa3-ae2af2b53b95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096656459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2096656459
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1519215923
Short name T532
Test name
Test status
Simulation time 84726161 ps
CPU time 3.22 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:51 PM PDT 24
Peak memory 198816 kb
Host smart-6d5d58d0-ef63-48c0-95df-a8be1134ee20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519215923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1519215923
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.835377897
Short name T435
Test name
Test status
Simulation time 465865913 ps
CPU time 2.28 seconds
Started Jul 05 04:36:38 PM PDT 24
Finished Jul 05 04:36:42 PM PDT 24
Peak memory 198612 kb
Host smart-b150b4b7-654b-4788-9a5c-c3d1e3ff3461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835377897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
835377897
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1679528742
Short name T630
Test name
Test status
Simulation time 50152224 ps
CPU time 0.64 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:36:52 PM PDT 24
Peak memory 194844 kb
Host smart-f0203a4d-754b-4869-b176-ab77f7fad503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679528742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1679528742
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3544938246
Short name T34
Test name
Test status
Simulation time 239334494 ps
CPU time 1.21 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 197760 kb
Host smart-138e0c10-4317-4254-89a1-9f41db6031b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544938246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3544938246
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.571673845
Short name T132
Test name
Test status
Simulation time 98436653 ps
CPU time 2.14 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 198688 kb
Host smart-b039d0e6-3533-4409-a845-dc06a71fd26b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571673845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.571673845
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4245648161
Short name T275
Test name
Test status
Simulation time 60780857 ps
CPU time 0.94 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:50 PM PDT 24
Peak memory 196488 kb
Host smart-f52e1776-b508-427c-87b0-337623226f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245648161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4245648161
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1362924167
Short name T671
Test name
Test status
Simulation time 118359325 ps
CPU time 1.04 seconds
Started Jul 05 04:36:45 PM PDT 24
Finished Jul 05 04:36:47 PM PDT 24
Peak memory 197184 kb
Host smart-8fca35ee-4758-4c6b-8475-48db6255bc28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362924167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1362924167
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3795712017
Short name T236
Test name
Test status
Simulation time 14475176725 ps
CPU time 99.24 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:38:31 PM PDT 24
Peak memory 198828 kb
Host smart-e6ac45ee-2178-440b-bc92-bb18aa2f8a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795712017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3795712017
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.715123166
Short name T653
Test name
Test status
Simulation time 14398029 ps
CPU time 0.58 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 195264 kb
Host smart-70e7aaf6-c357-4a96-8021-d3ad1d2ed30f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715123166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.715123166
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3389501407
Short name T289
Test name
Test status
Simulation time 30123933 ps
CPU time 0.75 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:52 PM PDT 24
Peak memory 196588 kb
Host smart-6afed08e-2441-4a98-b033-410d18ec2e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389501407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3389501407
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3524623218
Short name T76
Test name
Test status
Simulation time 345425378 ps
CPU time 6 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 197620 kb
Host smart-5d03ec20-e067-4467-9730-e8a70c5b8066
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524623218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3524623218
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1361672026
Short name T65
Test name
Test status
Simulation time 46719045 ps
CPU time 0.73 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 196380 kb
Host smart-7bef795a-18a0-46fd-be65-700f5cd752d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361672026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1361672026
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1357134533
Short name T492
Test name
Test status
Simulation time 117403203 ps
CPU time 1.01 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 196740 kb
Host smart-739952a1-bfe7-4673-81e5-4c56d621234c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357134533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1357134533
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1066974653
Short name T171
Test name
Test status
Simulation time 87101279 ps
CPU time 3.36 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 198696 kb
Host smart-429fd271-302c-4d40-8b6a-347f586e6c3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066974653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1066974653
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1213722991
Short name T700
Test name
Test status
Simulation time 75752696 ps
CPU time 2.31 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 196532 kb
Host smart-d9fbfb06-6701-4fb1-b17f-a08447066733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213722991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1213722991
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2479179192
Short name T460
Test name
Test status
Simulation time 93314810 ps
CPU time 1.05 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:45 PM PDT 24
Peak memory 197200 kb
Host smart-76671601-6901-469a-aeee-18984f37aa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479179192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2479179192
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.204816031
Short name T601
Test name
Test status
Simulation time 54002973 ps
CPU time 1.08 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 196800 kb
Host smart-34544049-809e-404c-ad22-19be18bc4306
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204816031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.204816031
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.361564954
Short name T20
Test name
Test status
Simulation time 1571011459 ps
CPU time 1.85 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 198636 kb
Host smart-2207f2a8-a4b4-4b40-8006-fb15235f8caf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361564954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.361564954
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.808888260
Short name T363
Test name
Test status
Simulation time 311551378 ps
CPU time 1.32 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 197704 kb
Host smart-00cb308a-479e-434e-a9ff-7a665836d156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808888260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.808888260
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3693868654
Short name T582
Test name
Test status
Simulation time 250259533 ps
CPU time 1.24 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 196960 kb
Host smart-7b8c7a29-971a-40be-b3b9-dfc49f74ff4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693868654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3693868654
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1417338245
Short name T268
Test name
Test status
Simulation time 12578672640 ps
CPU time 158.43 seconds
Started Jul 05 04:36:46 PM PDT 24
Finished Jul 05 04:39:26 PM PDT 24
Peak memory 198816 kb
Host smart-42b6f8ec-66b2-4a70-b70e-e160fc9bf5b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417338245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1417338245
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.98641505
Short name T182
Test name
Test status
Simulation time 91991748 ps
CPU time 0.55 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:46 PM PDT 24
Peak memory 195368 kb
Host smart-9b142590-de13-4db9-b0b7-290153ecf22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98641505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.98641505
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3623693772
Short name T177
Test name
Test status
Simulation time 28877286 ps
CPU time 0.83 seconds
Started Jul 05 04:35:51 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 197148 kb
Host smart-bd836b67-ec90-4884-adae-e022a3defc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623693772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3623693772
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1382932998
Short name T37
Test name
Test status
Simulation time 312886300 ps
CPU time 4.78 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 197312 kb
Host smart-5827de59-0cea-451a-a753-bd533bd8009f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382932998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1382932998
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1456999962
Short name T545
Test name
Test status
Simulation time 120543457 ps
CPU time 0.66 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:44 PM PDT 24
Peak memory 195316 kb
Host smart-bc5e3be8-5ace-4b7f-a05e-cfb70c8ce901
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456999962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1456999962
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2947489323
Short name T424
Test name
Test status
Simulation time 119453364 ps
CPU time 1.15 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 196352 kb
Host smart-4c29778d-f245-4904-ba67-bd8ef486d26d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947489323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2947489323
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2094854132
Short name T355
Test name
Test status
Simulation time 221534667 ps
CPU time 2.23 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 198760 kb
Host smart-4091a071-7366-4cd8-8ab1-eb0ac7378ca5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094854132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2094854132
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1306680380
Short name T347
Test name
Test status
Simulation time 588083512 ps
CPU time 2.62 seconds
Started Jul 05 04:35:51 PM PDT 24
Finished Jul 05 04:35:54 PM PDT 24
Peak memory 196496 kb
Host smart-910ad994-46dd-4269-abf9-12e130effe6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306680380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1306680380
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.4282483120
Short name T421
Test name
Test status
Simulation time 34408495 ps
CPU time 0.93 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 197272 kb
Host smart-bca6b6b3-d248-478e-a782-8bed5332162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282483120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.4282483120
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1379748813
Short name T517
Test name
Test status
Simulation time 28300071 ps
CPU time 0.79 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 196120 kb
Host smart-709736b8-2d12-44e1-91d5-cfa00a93af68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379748813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1379748813
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3508003372
Short name T443
Test name
Test status
Simulation time 359617378 ps
CPU time 5.74 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:49 PM PDT 24
Peak memory 198720 kb
Host smart-37eec56b-92ab-4156-82cc-0188c436d9a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508003372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3508003372
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3848311200
Short name T50
Test name
Test status
Simulation time 64336494 ps
CPU time 0.81 seconds
Started Jul 05 04:35:42 PM PDT 24
Finished Jul 05 04:35:44 PM PDT 24
Peak memory 214160 kb
Host smart-42fdd124-6f87-4e73-bfbd-f67ba2da0cd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848311200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3848311200
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.365443076
Short name T621
Test name
Test status
Simulation time 47159162 ps
CPU time 1.29 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:03 PM PDT 24
Peak memory 197440 kb
Host smart-2be9e594-7450-4013-bd55-7d55e83c46b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365443076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.365443076
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3458157932
Short name T416
Test name
Test status
Simulation time 142743930 ps
CPU time 0.78 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:45 PM PDT 24
Peak memory 195832 kb
Host smart-7735a87e-00b9-42f2-8d03-70359e166799
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458157932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3458157932
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.351942207
Short name T525
Test name
Test status
Simulation time 6904530379 ps
CPU time 177.63 seconds
Started Jul 05 04:35:51 PM PDT 24
Finished Jul 05 04:38:49 PM PDT 24
Peak memory 198800 kb
Host smart-795d6410-7ac8-489a-b6cd-0d06b6ced992
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351942207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.351942207
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4070731189
Short name T356
Test name
Test status
Simulation time 16998435 ps
CPU time 0.61 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 194648 kb
Host smart-ff695655-ef3b-4dbb-b6e5-e1a0a24042db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070731189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4070731189
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3305162971
Short name T228
Test name
Test status
Simulation time 178805352 ps
CPU time 0.71 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 194788 kb
Host smart-d9301dec-49e4-459a-97c2-d05fc4adfe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305162971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3305162971
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1667949658
Short name T701
Test name
Test status
Simulation time 509293461 ps
CPU time 26.36 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:37:16 PM PDT 24
Peak memory 196244 kb
Host smart-07531b3b-9319-4785-9c3a-c7c180a38be1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667949658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1667949658
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.588196769
Short name T41
Test name
Test status
Simulation time 258306212 ps
CPU time 0.79 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 197236 kb
Host smart-26d7433d-d543-4a32-a88b-76733a97d01c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588196769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.588196769
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3911454625
Short name T272
Test name
Test status
Simulation time 28407116 ps
CPU time 0.73 seconds
Started Jul 05 04:36:44 PM PDT 24
Finished Jul 05 04:36:46 PM PDT 24
Peak memory 195080 kb
Host smart-0f5a7f48-2606-40be-a6fd-1d9d356dd9f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911454625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3911454625
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3178011491
Short name T425
Test name
Test status
Simulation time 254421527 ps
CPU time 2.65 seconds
Started Jul 05 04:36:57 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 198708 kb
Host smart-5cee510e-78da-42a0-ad77-15a3f1e5c749
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178011491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3178011491
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.808062779
Short name T131
Test name
Test status
Simulation time 158598222 ps
CPU time 1.07 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:36:52 PM PDT 24
Peak memory 196332 kb
Host smart-b69ea1d2-d1ed-43b1-9377-29e10f0549ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808062779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
808062779
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3348843012
Short name T527
Test name
Test status
Simulation time 64298081 ps
CPU time 0.91 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 196504 kb
Host smart-9df080ae-d1f8-4954-b8ff-3f4d4d9f9112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348843012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3348843012
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3637273376
Short name T708
Test name
Test status
Simulation time 61784817 ps
CPU time 0.68 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:50 PM PDT 24
Peak memory 196052 kb
Host smart-3153052c-707b-4725-9219-149c5bca78f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637273376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3637273376
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1277698681
Short name T254
Test name
Test status
Simulation time 139574794 ps
CPU time 2.51 seconds
Started Jul 05 04:36:49 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 198624 kb
Host smart-ebb2eae6-9fc2-45ac-8342-bded4da238b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277698681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1277698681
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.166117073
Short name T638
Test name
Test status
Simulation time 272952309 ps
CPU time 1.3 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:36:49 PM PDT 24
Peak memory 198568 kb
Host smart-6c19c366-23e9-400c-be92-8be71b011c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166117073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.166117073
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3831745831
Short name T353
Test name
Test status
Simulation time 22484996 ps
CPU time 0.73 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:50 PM PDT 24
Peak memory 194720 kb
Host smart-a221f22d-8853-407c-8cda-1849d83c070d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831745831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3831745831
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3714480420
Short name T198
Test name
Test status
Simulation time 4018023415 ps
CPU time 28.21 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:37:20 PM PDT 24
Peak memory 198816 kb
Host smart-3270843b-79af-4f56-b051-8c5691b3c896
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714480420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3714480420
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.214209349
Short name T484
Test name
Test status
Simulation time 13009352 ps
CPU time 0.56 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 194872 kb
Host smart-ecab827f-1774-43d0-96a0-f06da7667a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214209349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.214209349
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3528899664
Short name T382
Test name
Test status
Simulation time 26837935 ps
CPU time 0.78 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 195804 kb
Host smart-e209501f-6303-4aa2-923a-237da4d4b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528899664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3528899664
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2652113735
Short name T291
Test name
Test status
Simulation time 175982619 ps
CPU time 9.09 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:37:05 PM PDT 24
Peak memory 196136 kb
Host smart-edd75041-9856-49a4-9991-265d1c6bcc89
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652113735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2652113735
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3565303846
Short name T1
Test name
Test status
Simulation time 355844075 ps
CPU time 1.03 seconds
Started Jul 05 04:37:05 PM PDT 24
Finished Jul 05 04:37:07 PM PDT 24
Peak memory 198472 kb
Host smart-46cf1298-220e-40a9-8857-2c664162154c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565303846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3565303846
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1731042834
Short name T405
Test name
Test status
Simulation time 22370108 ps
CPU time 0.74 seconds
Started Jul 05 04:37:04 PM PDT 24
Finished Jul 05 04:37:06 PM PDT 24
Peak memory 196748 kb
Host smart-f00e50f0-e5f7-4797-9a17-f2e5a39242a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731042834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1731042834
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.895911887
Short name T195
Test name
Test status
Simulation time 70539338 ps
CPU time 2.45 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:37:11 PM PDT 24
Peak memory 198596 kb
Host smart-ff222808-6c5c-49a3-8f7e-3647c10e82c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895911887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.895911887
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2544925566
Short name T611
Test name
Test status
Simulation time 193940367 ps
CPU time 1.32 seconds
Started Jul 05 04:36:58 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 197236 kb
Host smart-bb40fa61-96ec-4c58-a7f3-9f81b3740844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544925566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2544925566
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2229068876
Short name T589
Test name
Test status
Simulation time 78553009 ps
CPU time 1.33 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 197656 kb
Host smart-66843b8f-cba2-4c09-b12e-91c1539836ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229068876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2229068876
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1374899331
Short name T569
Test name
Test status
Simulation time 128985305 ps
CPU time 1.18 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 196528 kb
Host smart-9168ac8f-14db-4d42-8254-d9fcb5d3d6e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374899331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1374899331
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3031177403
Short name T10
Test name
Test status
Simulation time 1172473866 ps
CPU time 2.78 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 198548 kb
Host smart-db5e7d7c-4eaa-4918-8070-c78a887e0cea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031177403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3031177403
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3486412134
Short name T486
Test name
Test status
Simulation time 122208604 ps
CPU time 1.21 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 196592 kb
Host smart-b46d7642-6318-4987-85ec-2acacddf6d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486412134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3486412134
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2491298572
Short name T657
Test name
Test status
Simulation time 97936302 ps
CPU time 1.1 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 196328 kb
Host smart-4c2285c0-d608-495f-a4fa-4d397d53967f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491298572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2491298572
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3551517129
Short name T188
Test name
Test status
Simulation time 15392323598 ps
CPU time 111.88 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:38:48 PM PDT 24
Peak memory 198844 kb
Host smart-0304f4dc-279a-46aa-8163-b2f4f72784ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551517129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3551517129
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3759714568
Short name T68
Test name
Test status
Simulation time 46882855845 ps
CPU time 473.9 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:44:54 PM PDT 24
Peak memory 198892 kb
Host smart-f08222e7-a050-443c-afd6-4fb6cf07cacf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3759714568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3759714568
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.985660457
Short name T624
Test name
Test status
Simulation time 11202283 ps
CPU time 0.57 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:50 PM PDT 24
Peak memory 194672 kb
Host smart-47e29290-fc90-4fe1-b2ca-673a813b35bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985660457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.985660457
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2911078818
Short name T265
Test name
Test status
Simulation time 64762663 ps
CPU time 0.72 seconds
Started Jul 05 04:37:06 PM PDT 24
Finished Jul 05 04:37:09 PM PDT 24
Peak memory 195696 kb
Host smart-0ed73d17-dbcf-417e-b602-f6553a83fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911078818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2911078818
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1540306094
Short name T588
Test name
Test status
Simulation time 3297282794 ps
CPU time 23.93 seconds
Started Jul 05 04:36:47 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 197576 kb
Host smart-c30a3c03-a971-4c8e-9d33-112e68209c4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540306094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1540306094
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2736906424
Short name T244
Test name
Test status
Simulation time 262271010 ps
CPU time 0.89 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 198540 kb
Host smart-48505d58-ec3f-470a-9819-27e450b73693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736906424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2736906424
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2111611037
Short name T609
Test name
Test status
Simulation time 56102585 ps
CPU time 0.93 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 196684 kb
Host smart-34b75730-4e9b-4bef-9d37-d6e6d2beb4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111611037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2111611037
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3164184631
Short name T572
Test name
Test status
Simulation time 62361635 ps
CPU time 0.94 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 196820 kb
Host smart-f0827528-cb42-4581-b4bb-ff95033cc141
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164184631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3164184631
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4242907980
Short name T614
Test name
Test status
Simulation time 121691458 ps
CPU time 1.09 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 196264 kb
Host smart-216871de-e99f-4d59-b720-5a45f34977df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242907980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4242907980
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3684875566
Short name T462
Test name
Test status
Simulation time 59200886 ps
CPU time 1.27 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 197512 kb
Host smart-60debffa-a652-4a9a-8914-67e4161031cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684875566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3684875566
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.178489115
Short name T607
Test name
Test status
Simulation time 37226847 ps
CPU time 1.22 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 198620 kb
Host smart-2331915b-3466-4746-8138-5a5a610f09be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178489115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.178489115
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1400349160
Short name T452
Test name
Test status
Simulation time 389310513 ps
CPU time 4.38 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 198648 kb
Host smart-5f41b4c7-800f-4503-a9e5-ba3bec31e5d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400349160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1400349160
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1862012241
Short name T237
Test name
Test status
Simulation time 236501072 ps
CPU time 1.06 seconds
Started Jul 05 04:37:05 PM PDT 24
Finished Jul 05 04:37:07 PM PDT 24
Peak memory 196996 kb
Host smart-1be0e73c-727c-4387-8c60-da1560e9fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862012241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1862012241
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4137168587
Short name T31
Test name
Test status
Simulation time 180616862 ps
CPU time 1.29 seconds
Started Jul 05 04:37:11 PM PDT 24
Finished Jul 05 04:37:18 PM PDT 24
Peak memory 197396 kb
Host smart-a46c0de1-4e01-410a-ab17-ed38183e5a32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137168587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4137168587
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2964494105
Short name T218
Test name
Test status
Simulation time 21118759015 ps
CPU time 141.51 seconds
Started Jul 05 04:36:51 PM PDT 24
Finished Jul 05 04:39:16 PM PDT 24
Peak memory 198692 kb
Host smart-94f978f8-a740-42b5-89f3-98b4c277355e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964494105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2964494105
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.417310800
Short name T233
Test name
Test status
Simulation time 12256868 ps
CPU time 0.56 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 195400 kb
Host smart-b82e08e8-67cc-4389-a858-326057d5c1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417310800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.417310800
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.824650476
Short name T157
Test name
Test status
Simulation time 36783576 ps
CPU time 0.84 seconds
Started Jul 05 04:37:06 PM PDT 24
Finished Jul 05 04:37:08 PM PDT 24
Peak memory 195752 kb
Host smart-006a72bb-aca1-49e9-95f7-7a536a622b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824650476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.824650476
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.332781569
Short name T519
Test name
Test status
Simulation time 387558251 ps
CPU time 12.74 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:37:10 PM PDT 24
Peak memory 197408 kb
Host smart-cdeef209-5e30-4f5a-877d-51edd41cfdd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332781569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.332781569
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.987137188
Short name T466
Test name
Test status
Simulation time 68643591 ps
CPU time 0.99 seconds
Started Jul 05 04:36:50 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 197348 kb
Host smart-eb586607-c6d7-4378-8f50-70bb6d4330a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987137188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.987137188
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2330536987
Short name T455
Test name
Test status
Simulation time 166766944 ps
CPU time 1.04 seconds
Started Jul 05 04:37:01 PM PDT 24
Finished Jul 05 04:37:03 PM PDT 24
Peak memory 197236 kb
Host smart-7260d11b-afa9-4a2d-85c8-19a5b5e5687d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330536987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2330536987
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1201695698
Short name T585
Test name
Test status
Simulation time 501532838 ps
CPU time 3.12 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 196924 kb
Host smart-80fe40ba-9518-4491-b626-0786977872b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201695698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1201695698
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3967967521
Short name T710
Test name
Test status
Simulation time 115265829 ps
CPU time 1.76 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 197460 kb
Host smart-1eb26189-7719-45c3-a092-def3686f3a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967967521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3967967521
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2799952730
Short name T406
Test name
Test status
Simulation time 65357338 ps
CPU time 0.9 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 198000 kb
Host smart-3d6c196c-ae71-45d9-a526-74f6d2d3234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799952730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2799952730
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3940570629
Short name T341
Test name
Test status
Simulation time 78192716 ps
CPU time 1.07 seconds
Started Jul 05 04:37:11 PM PDT 24
Finished Jul 05 04:37:17 PM PDT 24
Peak memory 196680 kb
Host smart-26bc7e43-5c1e-4c3f-a3f8-0a9caab131ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940570629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3940570629
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3448937889
Short name T418
Test name
Test status
Simulation time 486502479 ps
CPU time 3.7 seconds
Started Jul 05 04:36:48 PM PDT 24
Finished Jul 05 04:36:53 PM PDT 24
Peak memory 198508 kb
Host smart-65a3d6d4-ffd9-43fd-94e2-c61d41981cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448937889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3448937889
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1762913628
Short name T498
Test name
Test status
Simulation time 172389084 ps
CPU time 1.4 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 196136 kb
Host smart-536206ec-d51c-4165-a718-e8f516197f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762913628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1762913628
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.218567901
Short name T257
Test name
Test status
Simulation time 44181622 ps
CPU time 1.16 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 196224 kb
Host smart-cd8967a4-67c3-4c6d-881f-bcb87baefa71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218567901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.218567901
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2525451647
Short name T542
Test name
Test status
Simulation time 26646964924 ps
CPU time 83.11 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:38:41 PM PDT 24
Peak memory 198812 kb
Host smart-8465c657-7bd8-4f98-8acb-2ac67d03de85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525451647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2525451647
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.643118382
Short name T53
Test name
Test status
Simulation time 71325120 ps
CPU time 0.57 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:37:11 PM PDT 24
Peak memory 195376 kb
Host smart-a5712fe3-3564-4d39-9e05-1292f133e0e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643118382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.643118382
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3536579565
Short name T590
Test name
Test status
Simulation time 29474029 ps
CPU time 0.84 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 197200 kb
Host smart-d8318003-71c0-4d16-9dfb-2e4929018aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536579565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3536579565
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2291544486
Short name T61
Test name
Test status
Simulation time 2464589917 ps
CPU time 18.34 seconds
Started Jul 05 04:37:04 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 197616 kb
Host smart-d5d322ad-100c-4004-86c6-440da1c909c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291544486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2291544486
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.300330188
Short name T697
Test name
Test status
Simulation time 220630826 ps
CPU time 0.76 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:37:09 PM PDT 24
Peak memory 197160 kb
Host smart-cb283bb1-dd1c-4b5a-8998-85d4b14630c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300330188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.300330188
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1914993799
Short name T287
Test name
Test status
Simulation time 29734931 ps
CPU time 0.75 seconds
Started Jul 05 04:37:10 PM PDT 24
Finished Jul 05 04:37:16 PM PDT 24
Peak memory 195920 kb
Host smart-45566eec-5bdb-48bd-8be1-cc625b36e035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914993799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1914993799
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1782391642
Short name T438
Test name
Test status
Simulation time 425199398 ps
CPU time 2.65 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 198752 kb
Host smart-78410cac-a614-43e8-ae8f-6295f158eafe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782391642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1782391642
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2578884858
Short name T280
Test name
Test status
Simulation time 164676047 ps
CPU time 3.12 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 197652 kb
Host smart-1b7838fb-b950-4883-83a7-4f0f9ff3cc62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578884858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2578884858
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.521443366
Short name T144
Test name
Test status
Simulation time 52466629 ps
CPU time 1.16 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 197364 kb
Host smart-95b546ab-3ee2-41b4-8c23-a62b1be04edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521443366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.521443366
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.587827531
Short name T646
Test name
Test status
Simulation time 32074620 ps
CPU time 0.66 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:55 PM PDT 24
Peak memory 195688 kb
Host smart-7c29c8d1-656b-4d9e-a4c1-7eb022cea809
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587827531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.587827531
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1094930352
Short name T320
Test name
Test status
Simulation time 530792821 ps
CPU time 5.65 seconds
Started Jul 05 04:37:06 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 198496 kb
Host smart-8fc6633d-3012-4ae2-93d5-b3f340ba59f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094930352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1094930352
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2667611800
Short name T628
Test name
Test status
Simulation time 88619938 ps
CPU time 1.26 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 198648 kb
Host smart-55253505-4f52-4416-b9c6-74eb031ea00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667611800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2667611800
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3391260892
Short name T271
Test name
Test status
Simulation time 32709599 ps
CPU time 0.92 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 196156 kb
Host smart-3b7af576-1d18-4e95-b4a4-9270478ebce8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391260892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3391260892
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.576151753
Short name T328
Test name
Test status
Simulation time 22513265869 ps
CPU time 158.05 seconds
Started Jul 05 04:36:56 PM PDT 24
Finished Jul 05 04:39:36 PM PDT 24
Peak memory 198788 kb
Host smart-3909f2ac-7d69-416f-9717-a157f4086716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576151753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.576151753
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.4241411524
Short name T652
Test name
Test status
Simulation time 42348228 ps
CPU time 0.63 seconds
Started Jul 05 04:37:04 PM PDT 24
Finished Jul 05 04:37:06 PM PDT 24
Peak memory 195280 kb
Host smart-254ae091-28fe-464f-a867-2eb6954440e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241411524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.4241411524
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2826254647
Short name T303
Test name
Test status
Simulation time 154592223 ps
CPU time 0.87 seconds
Started Jul 05 04:37:00 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 195708 kb
Host smart-b06ca16f-c877-44c1-afa5-a83bbbb3c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826254647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2826254647
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2782685157
Short name T420
Test name
Test status
Simulation time 277186908 ps
CPU time 13.77 seconds
Started Jul 05 04:36:57 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 197372 kb
Host smart-0a8a3d7a-56ce-40ce-9c73-fbabe0745a0b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782685157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2782685157
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3922940489
Short name T30
Test name
Test status
Simulation time 191446209 ps
CPU time 0.79 seconds
Started Jul 05 04:37:11 PM PDT 24
Finished Jul 05 04:37:16 PM PDT 24
Peak memory 197164 kb
Host smart-8f0ca630-7848-49fb-9c68-8dc9cade8c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922940489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3922940489
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1533037583
Short name T496
Test name
Test status
Simulation time 166425831 ps
CPU time 0.75 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 196092 kb
Host smart-61d131f2-f0ae-4e6d-aac7-cc64738b30b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533037583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1533037583
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1653126796
Short name T301
Test name
Test status
Simulation time 408853214 ps
CPU time 3.55 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 198776 kb
Host smart-72e1a595-b121-4a5b-96b7-4f4ab4b7809a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653126796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1653126796
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.70637521
Short name T531
Test name
Test status
Simulation time 181332012 ps
CPU time 1.99 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 197464 kb
Host smart-4f414229-92f5-4f46-ab28-346a802def08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70637521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.70637521
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1721006832
Short name T232
Test name
Test status
Simulation time 538054797 ps
CPU time 1.15 seconds
Started Jul 05 04:37:00 PM PDT 24
Finished Jul 05 04:37:03 PM PDT 24
Peak memory 196648 kb
Host smart-c7121f97-8bb9-4571-9f15-0c523dd09abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721006832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1721006832
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4270974059
Short name T615
Test name
Test status
Simulation time 117317511 ps
CPU time 0.77 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 196128 kb
Host smart-ff8a8fc4-fdb9-41f7-abc8-6db94e5a785f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270974059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4270974059
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.22082009
Short name T491
Test name
Test status
Simulation time 79607041 ps
CPU time 3.79 seconds
Started Jul 05 04:37:03 PM PDT 24
Finished Jul 05 04:37:08 PM PDT 24
Peak memory 198576 kb
Host smart-2bb87f05-3613-4781-8cdb-2c981b259df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22082009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand
om_long_reg_writes_reg_reads.22082009
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1551516954
Short name T200
Test name
Test status
Simulation time 110444214 ps
CPU time 1.17 seconds
Started Jul 05 04:36:52 PM PDT 24
Finished Jul 05 04:36:56 PM PDT 24
Peak memory 196464 kb
Host smart-b6d17ae1-73ff-4494-ab7e-06f0175487b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551516954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1551516954
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1023837070
Short name T672
Test name
Test status
Simulation time 38286321 ps
CPU time 0.92 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:58 PM PDT 24
Peak memory 197084 kb
Host smart-64632490-9675-4772-b479-e5be44aed7eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023837070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1023837070
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2359259726
Short name T709
Test name
Test status
Simulation time 1915014131 ps
CPU time 22.14 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:37:20 PM PDT 24
Peak memory 198700 kb
Host smart-f3421d94-db17-49d0-9e01-38e8b032154b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359259726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2359259726
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.4280990468
Short name T106
Test name
Test status
Simulation time 517826547745 ps
CPU time 2251.9 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 05:14:52 PM PDT 24
Peak memory 207028 kb
Host smart-4e004c67-5c18-4199-ab1b-50d884a38713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4280990468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.4280990468
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1875539547
Short name T139
Test name
Test status
Simulation time 19448429 ps
CPU time 0.62 seconds
Started Jul 05 04:37:00 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 194948 kb
Host smart-41ff29af-b037-4376-a86d-3490661d1524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875539547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1875539547
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2352258453
Short name T307
Test name
Test status
Simulation time 20101031 ps
CPU time 0.74 seconds
Started Jul 05 04:37:11 PM PDT 24
Finished Jul 05 04:37:16 PM PDT 24
Peak memory 196692 kb
Host smart-0ad803ba-8256-486a-b817-e67b9bb5c028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352258453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2352258453
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2756072229
Short name T293
Test name
Test status
Simulation time 177406292 ps
CPU time 5.32 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:37:14 PM PDT 24
Peak memory 197456 kb
Host smart-c82f6ff5-d4ed-4a03-bf73-d88caf2f9e2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756072229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2756072229
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3035562726
Short name T670
Test name
Test status
Simulation time 282043242 ps
CPU time 1.02 seconds
Started Jul 05 04:37:04 PM PDT 24
Finished Jul 05 04:37:06 PM PDT 24
Peak memory 197304 kb
Host smart-6801c54e-5d36-4e47-a1b4-ba0d7a7a38ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035562726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3035562726
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1921546198
Short name T74
Test name
Test status
Simulation time 67358034 ps
CPU time 1.26 seconds
Started Jul 05 04:37:02 PM PDT 24
Finished Jul 05 04:37:04 PM PDT 24
Peak memory 197528 kb
Host smart-1266501c-8559-4264-8a72-8a44fdcf103d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921546198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1921546198
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2235692671
Short name T255
Test name
Test status
Simulation time 104262970 ps
CPU time 2.33 seconds
Started Jul 05 04:36:58 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 198772 kb
Host smart-eb58c784-d2a0-4b5c-bbee-73dd238d92c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235692671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2235692671
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.891966998
Short name T370
Test name
Test status
Simulation time 360804447 ps
CPU time 2.73 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:37:00 PM PDT 24
Peak memory 196520 kb
Host smart-071201ef-0594-4f1b-b2c2-0f620fd616ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891966998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
891966998
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2890553712
Short name T322
Test name
Test status
Simulation time 41123288 ps
CPU time 0.98 seconds
Started Jul 05 04:37:00 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 196596 kb
Host smart-b0245147-ce7e-4ecb-866e-50842353956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890553712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2890553712
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2957328736
Short name T644
Test name
Test status
Simulation time 21976832 ps
CPU time 0.81 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 197204 kb
Host smart-b22d1f37-374e-4fe5-a63f-820cb98fa946
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957328736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2957328736
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2264296533
Short name T402
Test name
Test status
Simulation time 298720010 ps
CPU time 4.28 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 198672 kb
Host smart-cbc990a0-448f-46d0-aee7-cfe76f5fddcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264296533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2264296533
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3715082435
Short name T217
Test name
Test status
Simulation time 68331114 ps
CPU time 0.8 seconds
Started Jul 05 04:37:09 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 196448 kb
Host smart-e7e950ac-521f-4aa0-b334-db99af599698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715082435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3715082435
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1332101701
Short name T204
Test name
Test status
Simulation time 101723247 ps
CPU time 1.07 seconds
Started Jul 05 04:37:06 PM PDT 24
Finished Jul 05 04:37:08 PM PDT 24
Peak memory 196384 kb
Host smart-3c87e1ce-ddaf-414f-8879-08853dd77f89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332101701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1332101701
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.431650720
Short name T309
Test name
Test status
Simulation time 2027097497 ps
CPU time 46.69 seconds
Started Jul 05 04:37:09 PM PDT 24
Finished Jul 05 04:37:59 PM PDT 24
Peak memory 198744 kb
Host smart-3c008d1f-5c66-4b98-9b1a-da956930b48f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431650720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.431650720
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3335858614
Short name T705
Test name
Test status
Simulation time 27365126 ps
CPU time 0.57 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:37:11 PM PDT 24
Peak memory 195300 kb
Host smart-8fd238e7-9d94-4054-ae13-c9ebafda8f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335858614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3335858614
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1881969413
Short name T140
Test name
Test status
Simulation time 28409218 ps
CPU time 0.76 seconds
Started Jul 05 04:37:02 PM PDT 24
Finished Jul 05 04:37:04 PM PDT 24
Peak memory 194804 kb
Host smart-cc7c9c0a-14f8-416b-b665-97cad9c7aaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881969413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1881969413
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1644500308
Short name T39
Test name
Test status
Simulation time 1798061425 ps
CPU time 22.52 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:43 PM PDT 24
Peak memory 196212 kb
Host smart-f3b344e5-cc8c-4243-bdca-7a262bafa365
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644500308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1644500308
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4193253288
Short name T647
Test name
Test status
Simulation time 86014568 ps
CPU time 1.08 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 197112 kb
Host smart-27773925-0960-43ae-a3ce-03b901e0d808
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193253288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4193253288
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.727401138
Short name T221
Test name
Test status
Simulation time 44404670 ps
CPU time 1.25 seconds
Started Jul 05 04:37:03 PM PDT 24
Finished Jul 05 04:37:05 PM PDT 24
Peak memory 197660 kb
Host smart-a53a3116-7e33-4216-90c9-5b806835f621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727401138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.727401138
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2101288214
Short name T270
Test name
Test status
Simulation time 88598058 ps
CPU time 1.2 seconds
Started Jul 05 04:37:03 PM PDT 24
Finished Jul 05 04:37:05 PM PDT 24
Peak memory 197420 kb
Host smart-838ee436-eb07-4ac1-92c9-e62bd6e78466
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101288214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2101288214
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1391370998
Short name T281
Test name
Test status
Simulation time 197023092 ps
CPU time 1.33 seconds
Started Jul 05 04:37:12 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 196796 kb
Host smart-8355742a-ba93-43f7-bce0-5af12fa7206f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391370998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1391370998
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3612347555
Short name T398
Test name
Test status
Simulation time 99419283 ps
CPU time 0.78 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:57 PM PDT 24
Peak memory 196908 kb
Host smart-5d23a042-bacd-48ff-87b6-0d524c1f12ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612347555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3612347555
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.512908982
Short name T391
Test name
Test status
Simulation time 38884831 ps
CPU time 0.63 seconds
Started Jul 05 04:36:55 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 195628 kb
Host smart-f90e9217-e221-4fe9-b222-8b19a4d144cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512908982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.512908982
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1750509461
Short name T574
Test name
Test status
Simulation time 518807901 ps
CPU time 5.92 seconds
Started Jul 05 04:37:12 PM PDT 24
Finished Jul 05 04:37:23 PM PDT 24
Peak memory 198652 kb
Host smart-81efd588-9adc-4107-aeee-d6fd56ce9a04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750509461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1750509461
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3021737229
Short name T643
Test name
Test status
Simulation time 41576591 ps
CPU time 1.24 seconds
Started Jul 05 04:37:01 PM PDT 24
Finished Jul 05 04:37:03 PM PDT 24
Peak memory 197164 kb
Host smart-ff131898-1aa8-4359-89fe-b5c369d5b3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021737229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3021737229
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3716135832
Short name T253
Test name
Test status
Simulation time 112786514 ps
CPU time 1.02 seconds
Started Jul 05 04:36:56 PM PDT 24
Finished Jul 05 04:37:00 PM PDT 24
Peak memory 197000 kb
Host smart-64a2a79e-a29b-4e03-839e-ba587dee6d7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716135832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3716135832
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1741844799
Short name T148
Test name
Test status
Simulation time 7659429014 ps
CPU time 188.79 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:40:20 PM PDT 24
Peak memory 198712 kb
Host smart-345cb99b-5ca1-42c2-a02f-7b564a1fd550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741844799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1741844799
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1626287673
Short name T52
Test name
Test status
Simulation time 25438899 ps
CPU time 0.57 seconds
Started Jul 05 04:37:19 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 194680 kb
Host smart-23c42b01-8a7a-4313-9a14-eca317224f48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626287673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1626287673
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2943173803
Short name T552
Test name
Test status
Simulation time 63866664 ps
CPU time 0.69 seconds
Started Jul 05 04:37:07 PM PDT 24
Finished Jul 05 04:37:11 PM PDT 24
Peak memory 195444 kb
Host smart-06f0dc6f-46ed-4644-912a-430ef02aaa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943173803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2943173803
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1472058962
Short name T469
Test name
Test status
Simulation time 311990538 ps
CPU time 8.34 seconds
Started Jul 05 04:37:04 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 198668 kb
Host smart-d58a5f9f-304d-4490-9a1f-2e1574b6619e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472058962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1472058962
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2727404202
Short name T651
Test name
Test status
Simulation time 96935791 ps
CPU time 0.82 seconds
Started Jul 05 04:37:06 PM PDT 24
Finished Jul 05 04:37:07 PM PDT 24
Peak memory 197252 kb
Host smart-13eb424b-1993-4fdc-aad7-8f4e3061df17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727404202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2727404202
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3082409936
Short name T256
Test name
Test status
Simulation time 232341652 ps
CPU time 0.96 seconds
Started Jul 05 04:37:02 PM PDT 24
Finished Jul 05 04:37:04 PM PDT 24
Peak memory 196624 kb
Host smart-d4c464cc-2315-4f99-911f-b1b1601674c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082409936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3082409936
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2123347638
Short name T60
Test name
Test status
Simulation time 531120596 ps
CPU time 2.02 seconds
Started Jul 05 04:37:06 PM PDT 24
Finished Jul 05 04:37:10 PM PDT 24
Peak memory 197060 kb
Host smart-752237df-6c3b-4ac7-ae4e-8ab47ef1f909
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123347638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2123347638
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3851195545
Short name T503
Test name
Test status
Simulation time 247012562 ps
CPU time 2.57 seconds
Started Jul 05 04:36:53 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 198632 kb
Host smart-57850014-5adb-45e8-8d60-20558cafac79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851195545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3851195545
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3000982065
Short name T714
Test name
Test status
Simulation time 269387779 ps
CPU time 1.31 seconds
Started Jul 05 04:36:54 PM PDT 24
Finished Jul 05 04:36:59 PM PDT 24
Peak memory 196488 kb
Host smart-3ffad6d6-b59a-4965-9b9c-e96d016334eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000982065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3000982065
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.87877466
Short name T407
Test name
Test status
Simulation time 388336628 ps
CPU time 0.98 seconds
Started Jul 05 04:36:58 PM PDT 24
Finished Jul 05 04:37:01 PM PDT 24
Peak memory 196668 kb
Host smart-bea6843e-d211-4fb7-8b64-a147920f1cd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87877466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_
pulldown.87877466
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4257710045
Short name T367
Test name
Test status
Simulation time 195465166 ps
CPU time 2.05 seconds
Started Jul 05 04:36:59 PM PDT 24
Finished Jul 05 04:37:02 PM PDT 24
Peak memory 198716 kb
Host smart-4d4a23aa-38a5-43ba-89dd-0401ab6391a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257710045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4257710045
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.73014416
Short name T242
Test name
Test status
Simulation time 1248281452 ps
CPU time 1.06 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:37:19 PM PDT 24
Peak memory 196460 kb
Host smart-2654b723-1a1a-4310-bddf-3f62b39448a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73014416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.73014416
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1974376024
Short name T388
Test name
Test status
Simulation time 48780703 ps
CPU time 0.95 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 197028 kb
Host smart-25077346-5ba4-4fb1-b595-a8063b2dfc6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974376024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1974376024
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2766988387
Short name T608
Test name
Test status
Simulation time 11998715660 ps
CPU time 161.06 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:39:59 PM PDT 24
Peak memory 198740 kb
Host smart-aec6be25-eb22-4ea6-8466-b2c93b423881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766988387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2766988387
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2584229998
Short name T399
Test name
Test status
Simulation time 11806909 ps
CPU time 0.61 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 194580 kb
Host smart-b9814c4a-e04d-43f9-bbc3-71ee07c69e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584229998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2584229998
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3273203044
Short name T333
Test name
Test status
Simulation time 200786743 ps
CPU time 0.62 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 194524 kb
Host smart-dd21fa79-79bf-4445-8fad-d51898ed91a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273203044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3273203044
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1980472426
Short name T160
Test name
Test status
Simulation time 827607993 ps
CPU time 20.05 seconds
Started Jul 05 04:37:12 PM PDT 24
Finished Jul 05 04:37:37 PM PDT 24
Peak memory 197364 kb
Host smart-6138c837-0894-4c78-af19-3b7c528b8210
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980472426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1980472426
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3373101009
Short name T241
Test name
Test status
Simulation time 49483595 ps
CPU time 0.77 seconds
Started Jul 05 04:37:08 PM PDT 24
Finished Jul 05 04:37:12 PM PDT 24
Peak memory 196536 kb
Host smart-b249ef76-b7bd-4361-8ffb-6e0d39aa97f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373101009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3373101009
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.231085406
Short name T230
Test name
Test status
Simulation time 84035284 ps
CPU time 0.91 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 197096 kb
Host smart-e1c53151-a828-4953-8a6a-22459b7e50ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231085406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.231085406
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.479108654
Short name T690
Test name
Test status
Simulation time 74899972 ps
CPU time 1.03 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:20 PM PDT 24
Peak memory 197704 kb
Host smart-1e88949c-19fd-440f-acf0-8b60c7ec926a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479108654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.479108654
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3747533068
Short name T211
Test name
Test status
Simulation time 199015599 ps
CPU time 2.25 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 197700 kb
Host smart-14ae7b31-ff4f-4655-b83e-9f56e81143a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747533068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3747533068
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3980843867
Short name T619
Test name
Test status
Simulation time 322838887 ps
CPU time 1.08 seconds
Started Jul 05 04:37:09 PM PDT 24
Finished Jul 05 04:37:14 PM PDT 24
Peak memory 197248 kb
Host smart-55ca5b3c-9bf2-4a5a-bcc5-f26eb1e6780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980843867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3980843867
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3808951678
Short name T487
Test name
Test status
Simulation time 110524276 ps
CPU time 0.67 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:37:19 PM PDT 24
Peak memory 195728 kb
Host smart-ea9bfa1b-165a-4b50-8d18-baa6805b5ffd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808951678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3808951678
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3032197164
Short name T178
Test name
Test status
Simulation time 4620679156 ps
CPU time 3.92 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 198480 kb
Host smart-02130f57-06ad-4b83-99a5-bf618b54ef61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032197164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3032197164
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1131523566
Short name T400
Test name
Test status
Simulation time 40121672 ps
CPU time 1.09 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 196228 kb
Host smart-ef8ecdf9-c1f2-48d5-9bcb-b791ad7e3dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131523566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1131523566
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3456269111
Short name T66
Test name
Test status
Simulation time 87790924 ps
CPU time 0.9 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 196944 kb
Host smart-65bea48e-4bf7-41a8-a744-a1c0c7bf3cad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456269111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3456269111
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.670526163
Short name T321
Test name
Test status
Simulation time 6365328535 ps
CPU time 155.5 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:39:55 PM PDT 24
Peak memory 198804 kb
Host smart-472ecbb7-bc67-4fd8-89bc-b92e7bf8efc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670526163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.670526163
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2474150492
Short name T67
Test name
Test status
Simulation time 379599504879 ps
CPU time 2120.14 seconds
Started Jul 05 04:37:10 PM PDT 24
Finished Jul 05 05:12:35 PM PDT 24
Peak memory 198944 kb
Host smart-1f38a6c4-252a-4350-8930-ae16e713e9fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2474150492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2474150492
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2344307228
Short name T450
Test name
Test status
Simulation time 38129101 ps
CPU time 0.55 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:55 PM PDT 24
Peak memory 195388 kb
Host smart-5030f37a-18bb-4da4-80cb-08235af384b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344307228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2344307228
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2717178562
Short name T678
Test name
Test status
Simulation time 123467706 ps
CPU time 0.65 seconds
Started Jul 05 04:35:52 PM PDT 24
Finished Jul 05 04:35:53 PM PDT 24
Peak memory 194704 kb
Host smart-bee60724-35cb-43d3-8b00-27f82c2cded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717178562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2717178562
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3218497784
Short name T324
Test name
Test status
Simulation time 1083010753 ps
CPU time 8.58 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:55 PM PDT 24
Peak memory 197472 kb
Host smart-93edbf55-8a3f-469b-bdf4-a23fd87cebf3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218497784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3218497784
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3847386382
Short name T580
Test name
Test status
Simulation time 31065785 ps
CPU time 0.69 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:46 PM PDT 24
Peak memory 195232 kb
Host smart-c0d03eb5-1853-4bb7-a2b4-7bfd921b8be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847386382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3847386382
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2222371519
Short name T124
Test name
Test status
Simulation time 84083137 ps
CPU time 1.51 seconds
Started Jul 05 04:35:53 PM PDT 24
Finished Jul 05 04:35:56 PM PDT 24
Peak memory 197716 kb
Host smart-a4038f47-95cd-4763-a20b-0a1247c3a7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222371519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2222371519
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2268254212
Short name T654
Test name
Test status
Simulation time 349916598 ps
CPU time 1.24 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 197276 kb
Host smart-ded94a02-39cd-4ca5-bdae-f24c3f38538f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268254212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2268254212
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3321426003
Short name T578
Test name
Test status
Simulation time 1047396058 ps
CPU time 3.46 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 197796 kb
Host smart-bf9d3f1b-6a67-4e3b-a57b-0ef43d3d0f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321426003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3321426003
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3984579110
Short name T694
Test name
Test status
Simulation time 19115856 ps
CPU time 0.71 seconds
Started Jul 05 04:35:49 PM PDT 24
Finished Jul 05 04:35:51 PM PDT 24
Peak memory 196020 kb
Host smart-bdec8dd7-45c1-4fe2-9167-dd5844cd14c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984579110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3984579110
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.39543845
Short name T393
Test name
Test status
Simulation time 98631680 ps
CPU time 1 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 197428 kb
Host smart-859be657-5012-4a05-ba0c-5bc9a1400926
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39543845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_p
ulldown.39543845
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.310023655
Short name T444
Test name
Test status
Simulation time 312393371 ps
CPU time 1.6 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:48 PM PDT 24
Peak memory 198552 kb
Host smart-0147b66d-5260-4549-9111-bb8df5b9ebb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310023655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.310023655
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.420443390
Short name T49
Test name
Test status
Simulation time 118563683 ps
CPU time 0.87 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 214216 kb
Host smart-8dea4a3b-4c6e-428d-bfbf-2de183f14cd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420443390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.420443390
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1138045282
Short name T617
Test name
Test status
Simulation time 82354104 ps
CPU time 1.24 seconds
Started Jul 05 04:35:46 PM PDT 24
Finished Jul 05 04:35:48 PM PDT 24
Peak memory 196296 kb
Host smart-2fea2304-a2e8-4d83-a27b-e11d846ea91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138045282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1138045282
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3547614169
Short name T249
Test name
Test status
Simulation time 151053769 ps
CPU time 0.93 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:57 PM PDT 24
Peak memory 197120 kb
Host smart-01dac42b-18f7-4eb1-a131-60e16029278f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547614169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3547614169
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2807940383
Short name T332
Test name
Test status
Simulation time 24429985723 ps
CPU time 135.69 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:38:12 PM PDT 24
Peak memory 198788 kb
Host smart-287d5c4b-59d3-440c-aa21-0eaf58e4be7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807940383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2807940383
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4093380634
Short name T518
Test name
Test status
Simulation time 29703210 ps
CPU time 0.56 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 194576 kb
Host smart-bb579ed6-9e1e-469f-b35b-827c07bd8258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093380634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4093380634
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3023970028
Short name T118
Test name
Test status
Simulation time 672645160 ps
CPU time 0.87 seconds
Started Jul 05 04:37:16 PM PDT 24
Finished Jul 05 04:37:23 PM PDT 24
Peak memory 196748 kb
Host smart-e6fd67d3-2b1b-4a6e-a1e5-eb0c267ff03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023970028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3023970028
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1917261089
Short name T13
Test name
Test status
Simulation time 964090246 ps
CPU time 12.45 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:38 PM PDT 24
Peak memory 197756 kb
Host smart-2df2ee51-2365-412b-a00e-cace5e44190c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917261089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1917261089
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1605143889
Short name T313
Test name
Test status
Simulation time 175848135 ps
CPU time 0.76 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 195352 kb
Host smart-7c16bdc9-49c9-4565-8a43-1c9cb0801f54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605143889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1605143889
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1893229899
Short name T556
Test name
Test status
Simulation time 72947656 ps
CPU time 0.91 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 196524 kb
Host smart-81871d3f-6e9b-4dc5-90ea-5464fdc2aea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893229899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1893229899
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.112525492
Short name T456
Test name
Test status
Simulation time 48979909 ps
CPU time 1.84 seconds
Started Jul 05 04:37:08 PM PDT 24
Finished Jul 05 04:37:13 PM PDT 24
Peak memory 198608 kb
Host smart-9854868a-eb63-46fd-b094-e373ada67421
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112525492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.112525492
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3529559636
Short name T627
Test name
Test status
Simulation time 421225955 ps
CPU time 2.44 seconds
Started Jul 05 04:37:10 PM PDT 24
Finished Jul 05 04:37:17 PM PDT 24
Peak memory 198720 kb
Host smart-70ebbe1d-39dc-49a9-a652-28dd55917f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529559636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3529559636
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.271473258
Short name T300
Test name
Test status
Simulation time 18067005 ps
CPU time 0.66 seconds
Started Jul 05 04:37:09 PM PDT 24
Finished Jul 05 04:37:14 PM PDT 24
Peak memory 194772 kb
Host smart-97b6abd9-7902-4dac-a2eb-ee8b052e29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271473258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.271473258
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1248367229
Short name T216
Test name
Test status
Simulation time 55098035 ps
CPU time 1.25 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 197824 kb
Host smart-2ad166cb-6424-4297-a64b-66025977d5e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248367229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1248367229
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4239796490
Short name T685
Test name
Test status
Simulation time 107033589 ps
CPU time 1.9 seconds
Started Jul 05 04:37:09 PM PDT 24
Finished Jul 05 04:37:14 PM PDT 24
Peak memory 198672 kb
Host smart-3d6ea35b-9650-455d-b78a-bfbadab43146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239796490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4239796490
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3537913666
Short name T220
Test name
Test status
Simulation time 139121766 ps
CPU time 1.14 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:20 PM PDT 24
Peak memory 198636 kb
Host smart-e77bd124-8276-404e-81df-244e53ee6410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537913666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3537913666
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.564300698
Short name T166
Test name
Test status
Simulation time 29305867 ps
CPU time 0.89 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 197168 kb
Host smart-cf5ada25-cbdb-4cc5-9935-a8651c0a922d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564300698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.564300698
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.623629128
Short name T623
Test name
Test status
Simulation time 4718905702 ps
CPU time 63.18 seconds
Started Jul 05 04:37:08 PM PDT 24
Finished Jul 05 04:38:15 PM PDT 24
Peak memory 198776 kb
Host smart-efb3e1b8-73fb-4553-a6a0-8f8232e5b39b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623629128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.623629128
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2163191661
Short name T185
Test name
Test status
Simulation time 16328787 ps
CPU time 0.61 seconds
Started Jul 05 04:37:10 PM PDT 24
Finished Jul 05 04:37:16 PM PDT 24
Peak memory 194888 kb
Host smart-37535bea-bdbf-4271-b3d0-66485507732b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163191661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2163191661
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3252556123
Short name T130
Test name
Test status
Simulation time 83206389 ps
CPU time 0.72 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 195460 kb
Host smart-fa9298f0-41b5-43de-97f6-bdf3fe70caac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252556123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3252556123
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2517686188
Short name T576
Test name
Test status
Simulation time 301960310 ps
CPU time 16.1 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:37 PM PDT 24
Peak memory 197592 kb
Host smart-ea6e086d-b014-4f4c-b0a0-49870744f259
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517686188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2517686188
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.935054366
Short name T4
Test name
Test status
Simulation time 230613499 ps
CPU time 0.92 seconds
Started Jul 05 04:37:43 PM PDT 24
Finished Jul 05 04:37:46 PM PDT 24
Peak memory 196716 kb
Host smart-5d4968df-9e98-41fe-a889-58725ba8f08e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935054366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.935054366
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2724948651
Short name T675
Test name
Test status
Simulation time 83894930 ps
CPU time 0.97 seconds
Started Jul 05 04:37:16 PM PDT 24
Finished Jul 05 04:37:23 PM PDT 24
Peak memory 196732 kb
Host smart-e148f42f-338e-429a-8aca-00f5a80f34a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724948651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2724948651
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.89805004
Short name T629
Test name
Test status
Simulation time 89765596 ps
CPU time 3.3 seconds
Started Jul 05 04:37:16 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 198812 kb
Host smart-e337d369-17ba-42d6-aacd-f5657d886fa5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89805004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.gpio_intr_with_filter_rand_intr_event.89805004
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3348842737
Short name T426
Test name
Test status
Simulation time 96967311 ps
CPU time 2.14 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:22 PM PDT 24
Peak memory 198448 kb
Host smart-5625c00d-1585-46cb-90fe-bb985299f75a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348842737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3348842737
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3502997252
Short name T658
Test name
Test status
Simulation time 115725255 ps
CPU time 1.22 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 197180 kb
Host smart-04630d81-47a8-44ef-abdd-5e0ce931d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502997252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3502997252
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2428492525
Short name T133
Test name
Test status
Simulation time 39497129 ps
CPU time 1.09 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:29 PM PDT 24
Peak memory 197120 kb
Host smart-951ae075-4026-435c-8784-95d84d32e5a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428492525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2428492525
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1130504224
Short name T342
Test name
Test status
Simulation time 128721885 ps
CPU time 5.57 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 198588 kb
Host smart-560c7d87-d380-4a81-bd7f-bd70c7f2323d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130504224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1130504224
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.246464131
Short name T348
Test name
Test status
Simulation time 86050227 ps
CPU time 0.91 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:37:19 PM PDT 24
Peak memory 196060 kb
Host smart-4fbe363c-b756-49c2-b6c7-b07b4adbba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246464131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.246464131
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3661671101
Short name T389
Test name
Test status
Simulation time 88534037 ps
CPU time 0.83 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:37:18 PM PDT 24
Peak memory 196608 kb
Host smart-4ac01d50-39b9-4894-a196-87af229d32a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661671101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3661671101
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1966217657
Short name T472
Test name
Test status
Simulation time 9925469854 ps
CPU time 141.47 seconds
Started Jul 05 04:37:38 PM PDT 24
Finished Jul 05 04:40:00 PM PDT 24
Peak memory 198792 kb
Host smart-be18f279-94c7-4fbb-ad71-bc385ba63b08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966217657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1966217657
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.551209152
Short name T184
Test name
Test status
Simulation time 13311064 ps
CPU time 0.56 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 194684 kb
Host smart-b297b3e0-003a-4d6a-8895-c3bea547d1a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551209152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.551209152
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3545027976
Short name T659
Test name
Test status
Simulation time 113773438 ps
CPU time 0.72 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 195824 kb
Host smart-57c5f6e1-8380-4b33-9787-fc545127c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545027976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3545027976
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3022850224
Short name T315
Test name
Test status
Simulation time 2591116133 ps
CPU time 23.09 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:48 PM PDT 24
Peak memory 198788 kb
Host smart-efaede22-40aa-44ef-9525-21923832afb4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022850224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3022850224
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2143766840
Short name T201
Test name
Test status
Simulation time 38146522 ps
CPU time 0.74 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 196388 kb
Host smart-ca1bdbd0-0786-4485-a572-b842c1faaa7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143766840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2143766840
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1180282750
Short name T189
Test name
Test status
Simulation time 925970717 ps
CPU time 1.01 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 197548 kb
Host smart-91da2554-913c-4d3b-82a0-8b7166fcf12f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180282750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1180282750
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1768297119
Short name T429
Test name
Test status
Simulation time 270597599 ps
CPU time 1.89 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 198676 kb
Host smart-c0cfcf0a-8fc6-4531-bc01-03c04cae86e3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768297119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1768297119
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2654494471
Short name T441
Test name
Test status
Simulation time 33426701 ps
CPU time 0.87 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 195132 kb
Host smart-06c4438e-ef2d-4659-9718-e92eefdb3548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654494471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2654494471
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.27169720
Short name T29
Test name
Test status
Simulation time 33303748 ps
CPU time 0.84 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:21 PM PDT 24
Peak memory 196884 kb
Host smart-2193263a-a2b0-4dbb-9ec8-f20dd85c3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27169720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.27169720
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1162788772
Short name T229
Test name
Test status
Simulation time 28820562 ps
CPU time 0.84 seconds
Started Jul 05 04:37:13 PM PDT 24
Finished Jul 05 04:37:19 PM PDT 24
Peak memory 196260 kb
Host smart-2338aa80-1219-4a7f-ba9f-2230c2ab7520
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162788772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1162788772
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3982340952
Short name T432
Test name
Test status
Simulation time 1452910266 ps
CPU time 3.41 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 198528 kb
Host smart-742d3ef6-406a-4493-a336-d144a770c017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982340952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3982340952
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3113038929
Short name T610
Test name
Test status
Simulation time 60199021 ps
CPU time 1.02 seconds
Started Jul 05 04:37:10 PM PDT 24
Finished Jul 05 04:37:16 PM PDT 24
Peak memory 196868 kb
Host smart-dee250c1-4450-474c-9295-44edb11d8fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113038929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3113038929
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1085936079
Short name T523
Test name
Test status
Simulation time 43589063 ps
CPU time 0.84 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 195856 kb
Host smart-b656b303-dcb5-4063-8384-d39bc10f06f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085936079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1085936079
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.4072257972
Short name T404
Test name
Test status
Simulation time 3237471372 ps
CPU time 84.18 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:38:47 PM PDT 24
Peak memory 198844 kb
Host smart-066ae06e-a528-4593-b91a-59be1ca03ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072257972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.4072257972
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1107091821
Short name T606
Test name
Test status
Simulation time 42080205 ps
CPU time 0.58 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 194688 kb
Host smart-334efd08-cd63-4de4-95f1-bb33e9f4b368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107091821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1107091821
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2793112996
Short name T476
Test name
Test status
Simulation time 106358185 ps
CPU time 0.71 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:20 PM PDT 24
Peak memory 194868 kb
Host smart-eea054a8-800a-4aff-8b25-dc5cfa8b1bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793112996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2793112996
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.574952452
Short name T563
Test name
Test status
Simulation time 269087936 ps
CPU time 3.11 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 197340 kb
Host smart-5f87f4e0-9bf5-4384-9d34-d3f12bbe6be3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574952452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.574952452
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.892390930
Short name T222
Test name
Test status
Simulation time 49854172 ps
CPU time 0.8 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:20 PM PDT 24
Peak memory 197284 kb
Host smart-98a8c509-5b77-486d-a270-1e1af8e170f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892390930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.892390930
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4128299969
Short name T336
Test name
Test status
Simulation time 36301515 ps
CPU time 0.69 seconds
Started Jul 05 04:37:19 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 194948 kb
Host smart-f2c98684-7f4f-4570-ac83-340f90495a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128299969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4128299969
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3070492812
Short name T461
Test name
Test status
Simulation time 35333069 ps
CPU time 1.35 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 197436 kb
Host smart-4f9c70ed-9e40-4fc9-8c0e-5e72feaa1c33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070492812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3070492812
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3688327529
Short name T430
Test name
Test status
Simulation time 302135826 ps
CPU time 2.21 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 198648 kb
Host smart-f65687cd-1882-449c-93b7-4622e93ee8d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688327529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3688327529
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3961640689
Short name T707
Test name
Test status
Simulation time 42972204 ps
CPU time 0.89 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 196552 kb
Host smart-3ecd1e43-4800-4931-853d-e2c90ad40572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961640689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3961640689
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.13135486
Short name T192
Test name
Test status
Simulation time 19606882 ps
CPU time 0.72 seconds
Started Jul 05 04:37:19 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 195528 kb
Host smart-d19da244-e4af-4539-a669-78f95ac9fa40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13135486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup_
pulldown.13135486
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1742255806
Short name T168
Test name
Test status
Simulation time 1248856671 ps
CPU time 5.26 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 198644 kb
Host smart-d24f3258-a955-4e11-bfad-f7db1ea38b72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742255806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1742255806
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3701757999
Short name T448
Test name
Test status
Simulation time 114233819 ps
CPU time 1.11 seconds
Started Jul 05 04:37:38 PM PDT 24
Finished Jul 05 04:37:40 PM PDT 24
Peak memory 196856 kb
Host smart-85416c14-c8c7-4482-a771-957247228eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701757999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3701757999
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1813331183
Short name T75
Test name
Test status
Simulation time 124094821 ps
CPU time 1.08 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 196524 kb
Host smart-172609fd-385f-4370-990e-0a908c90f3ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813331183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1813331183
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4096238820
Short name T509
Test name
Test status
Simulation time 15299179694 ps
CPU time 144.34 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:39:47 PM PDT 24
Peak memory 198732 kb
Host smart-6c164712-5dcd-45fa-a5fd-44cb220f2ead
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096238820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4096238820
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2979405091
Short name T70
Test name
Test status
Simulation time 248263253912 ps
CPU time 1462.38 seconds
Started Jul 05 04:37:19 PM PDT 24
Finished Jul 05 05:01:49 PM PDT 24
Peak memory 198904 kb
Host smart-bc1ce08d-8345-49c5-a162-04ef0acfe640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2979405091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2979405091
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1807661068
Short name T636
Test name
Test status
Simulation time 42691289 ps
CPU time 0.59 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 194676 kb
Host smart-48573a7f-afc9-4b40-a6a1-5614cd0f8c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807661068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1807661068
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.981334051
Short name T288
Test name
Test status
Simulation time 15139333 ps
CPU time 0.6 seconds
Started Jul 05 04:37:09 PM PDT 24
Finished Jul 05 04:37:12 PM PDT 24
Peak memory 194560 kb
Host smart-20b8629f-f611-46e8-8539-2c9a20e79691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981334051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.981334051
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.261947248
Short name T156
Test name
Test status
Simulation time 315170579 ps
CPU time 15.74 seconds
Started Jul 05 04:37:19 PM PDT 24
Finished Jul 05 04:37:42 PM PDT 24
Peak memory 196224 kb
Host smart-9fe4ec13-fdfa-42c5-8f38-e9836f6f6e06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261947248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.261947248
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2262918503
Short name T279
Test name
Test status
Simulation time 119913485 ps
CPU time 0.79 seconds
Started Jul 05 04:37:12 PM PDT 24
Finished Jul 05 04:37:17 PM PDT 24
Peak memory 196552 kb
Host smart-f93543ad-0cba-4101-b84f-81c23a2661f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262918503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2262918503
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3209347354
Short name T343
Test name
Test status
Simulation time 25782049 ps
CPU time 0.75 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 196760 kb
Host smart-e3ab2399-b75d-4293-9181-af8ed5af7c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209347354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3209347354
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3815696835
Short name T409
Test name
Test status
Simulation time 76868143 ps
CPU time 2.88 seconds
Started Jul 05 04:37:36 PM PDT 24
Finished Jul 05 04:37:40 PM PDT 24
Peak memory 198732 kb
Host smart-1c357fe4-0340-42cb-a7f4-411cca53b6ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815696835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3815696835
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3876581498
Short name T546
Test name
Test status
Simulation time 81119210 ps
CPU time 1.39 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 197920 kb
Host smart-d232ed03-f030-4edd-b0e1-6411f500e4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876581498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3876581498
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1596267834
Short name T689
Test name
Test status
Simulation time 126826019 ps
CPU time 0.83 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 197340 kb
Host smart-be2d0ede-6096-48c9-8cfd-49995005a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596267834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1596267834
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3189075630
Short name T508
Test name
Test status
Simulation time 128744843 ps
CPU time 1.28 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 197648 kb
Host smart-9ffd15ec-bc7a-4bf2-890d-f5a6cc66f13c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189075630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3189075630
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3993923063
Short name T357
Test name
Test status
Simulation time 411162196 ps
CPU time 1.6 seconds
Started Jul 05 04:37:22 PM PDT 24
Finished Jul 05 04:37:30 PM PDT 24
Peak memory 198576 kb
Host smart-fe8804c7-84dd-4105-b198-7f37955cd639
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993923063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3993923063
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1611625424
Short name T493
Test name
Test status
Simulation time 48601038 ps
CPU time 1.23 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:29 PM PDT 24
Peak memory 197040 kb
Host smart-ed45abb5-dea9-4925-8f93-16857d962b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611625424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1611625424
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.16816759
Short name T449
Test name
Test status
Simulation time 87147985 ps
CPU time 1.32 seconds
Started Jul 05 04:37:22 PM PDT 24
Finished Jul 05 04:37:30 PM PDT 24
Peak memory 196264 kb
Host smart-0831c863-e5b1-4940-80b1-389f690c9cc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16816759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.16816759
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4101640804
Short name T28
Test name
Test status
Simulation time 9699971650 ps
CPU time 60.42 seconds
Started Jul 05 04:37:12 PM PDT 24
Finished Jul 05 04:38:18 PM PDT 24
Peak memory 198768 kb
Host smart-24e016aa-07d6-4183-8cf3-08bca4a6ae67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101640804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4101640804
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1250082249
Short name T69
Test name
Test status
Simulation time 28840368319 ps
CPU time 634.59 seconds
Started Jul 05 04:37:11 PM PDT 24
Finished Jul 05 04:47:50 PM PDT 24
Peak memory 198968 kb
Host smart-96d04c29-21d0-4eab-960c-43493c6f0d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1250082249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1250082249
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3525700893
Short name T294
Test name
Test status
Simulation time 100361780 ps
CPU time 0.55 seconds
Started Jul 05 04:37:34 PM PDT 24
Finished Jul 05 04:37:35 PM PDT 24
Peak memory 194860 kb
Host smart-240a244e-79ee-4778-8bf6-71f593c4b6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525700893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3525700893
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1470474757
Short name T126
Test name
Test status
Simulation time 41185190 ps
CPU time 0.76 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 196064 kb
Host smart-3658b98c-cd92-4637-8588-1aaefb8dc348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470474757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1470474757
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3167981130
Short name T414
Test name
Test status
Simulation time 704639420 ps
CPU time 18.43 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:48 PM PDT 24
Peak memory 197644 kb
Host smart-ff4670aa-6398-4681-868a-bd0bdc1b85eb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167981130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3167981130
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2960172808
Short name T190
Test name
Test status
Simulation time 154247708 ps
CPU time 0.85 seconds
Started Jul 05 04:37:25 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 197444 kb
Host smart-5e3fec79-5c61-478e-80aa-dfb3ef394539
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960172808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2960172808
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4030178823
Short name T682
Test name
Test status
Simulation time 140840170 ps
CPU time 1.15 seconds
Started Jul 05 04:37:14 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 196400 kb
Host smart-07f973c6-2e3d-4d39-bf76-1b633aaac94b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030178823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4030178823
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.322214675
Short name T625
Test name
Test status
Simulation time 44398473 ps
CPU time 1.5 seconds
Started Jul 05 04:37:37 PM PDT 24
Finished Jul 05 04:37:39 PM PDT 24
Peak memory 198696 kb
Host smart-9a9ac942-0498-4c0b-a0fa-9369506c9458
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322214675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.322214675
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4104949605
Short name T224
Test name
Test status
Simulation time 241309885 ps
CPU time 2.64 seconds
Started Jul 05 04:37:37 PM PDT 24
Finished Jul 05 04:37:40 PM PDT 24
Peak memory 196504 kb
Host smart-88e0650c-4a5c-4e0a-a8ed-afea9b20c2ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104949605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4104949605
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4197204708
Short name T159
Test name
Test status
Simulation time 94302899 ps
CPU time 1.1 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:24 PM PDT 24
Peak memory 197104 kb
Host smart-5e6e93a4-efdb-452f-ab9d-42249e959dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197204708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4197204708
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1347832675
Short name T252
Test name
Test status
Simulation time 14270768 ps
CPU time 0.63 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:25 PM PDT 24
Peak memory 194772 kb
Host smart-48abbd12-d314-469f-9544-3e5c2a8b5e4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347832675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1347832675
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4199178285
Short name T369
Test name
Test status
Simulation time 563615350 ps
CPU time 2.78 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 198700 kb
Host smart-97991775-f190-42d6-9b32-2174d97e1cef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199178285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4199178285
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3044166197
Short name T505
Test name
Test status
Simulation time 168788456 ps
CPU time 1.29 seconds
Started Jul 05 04:37:15 PM PDT 24
Finished Jul 05 04:37:23 PM PDT 24
Peak memory 196252 kb
Host smart-8003f71a-6e57-48a3-9669-02399823b962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044166197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3044166197
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1866984593
Short name T146
Test name
Test status
Simulation time 125387465 ps
CPU time 0.93 seconds
Started Jul 05 04:38:48 PM PDT 24
Finished Jul 05 04:38:53 PM PDT 24
Peak memory 196932 kb
Host smart-5a25da5a-4eee-4d81-8f5e-b4ab47beb46a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866984593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1866984593
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1923213041
Short name T457
Test name
Test status
Simulation time 14144420573 ps
CPU time 192 seconds
Started Jul 05 04:37:27 PM PDT 24
Finished Jul 05 04:40:43 PM PDT 24
Peak memory 198612 kb
Host smart-db129c27-5b48-41c9-ae7f-de7150b59563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923213041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1923213041
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2240893189
Short name T602
Test name
Test status
Simulation time 224779519185 ps
CPU time 2522.49 seconds
Started Jul 05 04:37:28 PM PDT 24
Finished Jul 05 05:19:34 PM PDT 24
Peak memory 198840 kb
Host smart-9f99dba0-c28e-4e6e-b2bc-d58b6e6586aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2240893189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2240893189
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3931175689
Short name T573
Test name
Test status
Simulation time 13036316 ps
CPU time 0.56 seconds
Started Jul 05 04:37:37 PM PDT 24
Finished Jul 05 04:37:38 PM PDT 24
Peak memory 194916 kb
Host smart-5553a7f6-1e6f-4fa5-a4ea-c6bacdddd1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931175689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3931175689
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3158903051
Short name T433
Test name
Test status
Simulation time 104175400 ps
CPU time 0.8 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 196088 kb
Host smart-d331cb91-93c7-428c-914a-10d3e25933d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158903051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3158903051
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1617883542
Short name T394
Test name
Test status
Simulation time 1578218843 ps
CPU time 15.31 seconds
Started Jul 05 04:37:33 PM PDT 24
Finished Jul 05 04:37:49 PM PDT 24
Peak memory 197440 kb
Host smart-0e407574-6dcf-4523-a6c7-5a0732b53f94
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617883542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1617883542
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2905855643
Short name T668
Test name
Test status
Simulation time 44750359 ps
CPU time 0.81 seconds
Started Jul 05 04:37:27 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 196620 kb
Host smart-167766fb-cebc-44b8-aa0c-19912146fcdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905855643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2905855643
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.145392701
Short name T219
Test name
Test status
Simulation time 216438010 ps
CPU time 1.08 seconds
Started Jul 05 04:37:40 PM PDT 24
Finished Jul 05 04:37:42 PM PDT 24
Peak memory 197228 kb
Host smart-2abeccc9-fe17-4cbe-8829-36312ab156e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145392701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.145392701
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1942119468
Short name T533
Test name
Test status
Simulation time 66714763 ps
CPU time 2.53 seconds
Started Jul 05 04:37:23 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 198776 kb
Host smart-346ff392-241f-4e7a-932e-0799af5d05c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942119468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1942119468
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2735129331
Short name T194
Test name
Test status
Simulation time 276593201 ps
CPU time 2.83 seconds
Started Jul 05 04:37:34 PM PDT 24
Finished Jul 05 04:37:38 PM PDT 24
Peak memory 198692 kb
Host smart-e3009139-d425-4a12-9439-ad3ddae92b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735129331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2735129331
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1726915850
Short name T616
Test name
Test status
Simulation time 91013810 ps
CPU time 1.23 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 197636 kb
Host smart-fd9f77da-60b0-438e-9fc6-d2c6e570f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726915850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1726915850
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3447118018
Short name T516
Test name
Test status
Simulation time 46440667 ps
CPU time 1.01 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 196620 kb
Host smart-9b621a18-9940-4857-835f-b0e605938e5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447118018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3447118018
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1400726922
Short name T2
Test name
Test status
Simulation time 2321377411 ps
CPU time 4.5 seconds
Started Jul 05 04:37:23 PM PDT 24
Finished Jul 05 04:37:34 PM PDT 24
Peak memory 198644 kb
Host smart-3347ff4e-9d14-4a3b-b994-83de1c9a4af4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400726922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1400726922
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.649768694
Short name T520
Test name
Test status
Simulation time 95035738 ps
CPU time 1.12 seconds
Started Jul 05 04:37:32 PM PDT 24
Finished Jul 05 04:37:35 PM PDT 24
Peak memory 196508 kb
Host smart-6f9e49c0-9c23-45a1-8182-8aa052f38974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649768694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.649768694
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2608103889
Short name T240
Test name
Test status
Simulation time 62301223 ps
CPU time 0.89 seconds
Started Jul 05 04:37:32 PM PDT 24
Finished Jul 05 04:37:35 PM PDT 24
Peak memory 197216 kb
Host smart-8d2972c8-2dcb-40b4-a19a-4e9a50e5e80d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608103889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2608103889
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1303413850
Short name T541
Test name
Test status
Simulation time 64812731577 ps
CPU time 342.62 seconds
Started Jul 05 04:37:30 PM PDT 24
Finished Jul 05 04:43:15 PM PDT 24
Peak memory 198840 kb
Host smart-51519af3-d321-426b-9447-c1de36b7edfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1303413850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1303413850
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2323102374
Short name T577
Test name
Test status
Simulation time 24021789 ps
CPU time 0.55 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 194576 kb
Host smart-840bdde7-0e82-4570-963e-f0cb6e746f1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323102374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2323102374
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1812289680
Short name T501
Test name
Test status
Simulation time 536318656 ps
CPU time 0.88 seconds
Started Jul 05 04:37:27 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 195896 kb
Host smart-b923cc08-4659-447e-9aaf-b64f4dfe7552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812289680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1812289680
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1941172660
Short name T665
Test name
Test status
Simulation time 3501919834 ps
CPU time 24.36 seconds
Started Jul 05 04:37:19 PM PDT 24
Finished Jul 05 04:37:50 PM PDT 24
Peak memory 197640 kb
Host smart-f45488c9-36fb-4992-a45e-63f88ff77408
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941172660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1941172660
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.687059310
Short name T663
Test name
Test status
Simulation time 148279949 ps
CPU time 0.96 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 197132 kb
Host smart-54c738a8-c9e8-436a-ba67-35e17f73ce3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687059310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.687059310
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1124269619
Short name T567
Test name
Test status
Simulation time 49877700 ps
CPU time 0.89 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 198236 kb
Host smart-e60670d1-4257-4e8e-a4e6-cc7d7021f125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124269619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1124269619
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1977011525
Short name T64
Test name
Test status
Simulation time 273522161 ps
CPU time 3.07 seconds
Started Jul 05 04:37:43 PM PDT 24
Finished Jul 05 04:37:48 PM PDT 24
Peak memory 198776 kb
Host smart-4879d634-8b00-4c4a-ad4a-5babf1a9cbc7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977011525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1977011525
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3286690770
Short name T458
Test name
Test status
Simulation time 211141088 ps
CPU time 2.45 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 197800 kb
Host smart-f6bd8795-1926-4168-87ee-e32313ea5842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286690770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3286690770
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1935783736
Short name T234
Test name
Test status
Simulation time 53370842 ps
CPU time 0.83 seconds
Started Jul 05 04:37:26 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 197084 kb
Host smart-3956505e-fc90-429c-b23a-cf5ad8804d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935783736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1935783736
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3386566920
Short name T323
Test name
Test status
Simulation time 45858454 ps
CPU time 1.04 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:29 PM PDT 24
Peak memory 196620 kb
Host smart-21179027-8368-4c3f-b35c-1f99eefae64d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386566920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3386566920
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1706126592
Short name T18
Test name
Test status
Simulation time 368533049 ps
CPU time 5.51 seconds
Started Jul 05 04:37:42 PM PDT 24
Finished Jul 05 04:37:49 PM PDT 24
Peak memory 198676 kb
Host smart-894d68a7-2e93-4ceb-8360-ac3a399515d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706126592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1706126592
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3965157931
Short name T669
Test name
Test status
Simulation time 42357782 ps
CPU time 0.98 seconds
Started Jul 05 04:37:32 PM PDT 24
Finished Jul 05 04:37:34 PM PDT 24
Peak memory 197096 kb
Host smart-d6d45955-5b4b-49c5-81a9-4ca6edc6be98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965157931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3965157931
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1606315312
Short name T155
Test name
Test status
Simulation time 177396870 ps
CPU time 1.34 seconds
Started Jul 05 04:37:46 PM PDT 24
Finished Jul 05 04:37:49 PM PDT 24
Peak memory 197288 kb
Host smart-414d358d-88e1-4200-b721-bbda4b55368d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606315312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1606315312
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.254555639
Short name T566
Test name
Test status
Simulation time 22848163924 ps
CPU time 219.49 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:41:04 PM PDT 24
Peak memory 198736 kb
Host smart-e1dce7ba-597f-4c23-af11-766c7851bb0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254555639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.254555639
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3482022654
Short name T35
Test name
Test status
Simulation time 183039479 ps
CPU time 0.57 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:27 PM PDT 24
Peak memory 194772 kb
Host smart-b0268bb6-5d77-48eb-affd-74d5e3e1f9e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482022654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3482022654
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3424450436
Short name T550
Test name
Test status
Simulation time 74310946 ps
CPU time 0.82 seconds
Started Jul 05 04:37:30 PM PDT 24
Finished Jul 05 04:37:34 PM PDT 24
Peak memory 196100 kb
Host smart-313a32b2-0965-44db-868d-edafd2a53ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424450436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3424450436
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2585559126
Short name T385
Test name
Test status
Simulation time 1371542434 ps
CPU time 11.98 seconds
Started Jul 05 04:37:25 PM PDT 24
Finished Jul 05 04:37:42 PM PDT 24
Peak memory 196240 kb
Host smart-074cf98c-fc10-4fd3-8565-6428809719c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585559126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2585559126
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.248806375
Short name T595
Test name
Test status
Simulation time 57745878 ps
CPU time 0.87 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 196724 kb
Host smart-fca095e4-a2ad-42ca-aa1d-d8d345253a25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248806375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.248806375
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2270190865
Short name T316
Test name
Test status
Simulation time 35573078 ps
CPU time 0.95 seconds
Started Jul 05 04:37:43 PM PDT 24
Finished Jul 05 04:37:46 PM PDT 24
Peak memory 196736 kb
Host smart-29d4f2a2-14d5-4567-9622-db7d44c0707a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270190865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2270190865
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2437643956
Short name T679
Test name
Test status
Simulation time 226392447 ps
CPU time 2.57 seconds
Started Jul 05 04:37:36 PM PDT 24
Finished Jul 05 04:37:39 PM PDT 24
Peak memory 198624 kb
Host smart-7e8844d3-e20f-459f-b1cd-22f76ae2edb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437643956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2437643956
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3232373936
Short name T568
Test name
Test status
Simulation time 35728747 ps
CPU time 1.03 seconds
Started Jul 05 04:37:27 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 196900 kb
Host smart-3226d5c7-fd5b-401c-828e-efe763519efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232373936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3232373936
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3372853246
Short name T554
Test name
Test status
Simulation time 60692230 ps
CPU time 0.88 seconds
Started Jul 05 04:37:22 PM PDT 24
Finished Jul 05 04:37:29 PM PDT 24
Peak memory 197284 kb
Host smart-79799472-4b86-4452-b62f-7b06cfa5cdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372853246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3372853246
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3611118627
Short name T167
Test name
Test status
Simulation time 78120582 ps
CPU time 1 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 196584 kb
Host smart-0c59131b-ad25-4d8e-9e9b-234c71e70851
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611118627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3611118627
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3545511475
Short name T202
Test name
Test status
Simulation time 624787549 ps
CPU time 2.91 seconds
Started Jul 05 04:37:32 PM PDT 24
Finished Jul 05 04:37:37 PM PDT 24
Peak memory 198640 kb
Host smart-47fb7550-3821-407e-b5bf-8d80a3676568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545511475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3545511475
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.381734168
Short name T172
Test name
Test status
Simulation time 280004989 ps
CPU time 1.46 seconds
Started Jul 05 04:37:22 PM PDT 24
Finished Jul 05 04:37:30 PM PDT 24
Peak memory 197460 kb
Host smart-746d8d6a-87b9-4ce4-881d-bff394586aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381734168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.381734168
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2976778864
Short name T401
Test name
Test status
Simulation time 88538601 ps
CPU time 1.43 seconds
Started Jul 05 04:37:26 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 198600 kb
Host smart-19928d89-cd40-497c-a38d-02a9908884ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976778864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2976778864
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3570169011
Short name T699
Test name
Test status
Simulation time 2282262441 ps
CPU time 56.42 seconds
Started Jul 05 04:37:38 PM PDT 24
Finished Jul 05 04:38:36 PM PDT 24
Peak memory 198820 kb
Host smart-8a35474a-8dbc-4f89-9696-d77311306e9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570169011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3570169011
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.424570325
Short name T71
Test name
Test status
Simulation time 186187589257 ps
CPU time 673.29 seconds
Started Jul 05 04:37:40 PM PDT 24
Finished Jul 05 04:48:54 PM PDT 24
Peak memory 198980 kb
Host smart-a69933ed-b4ff-4739-b418-83d2f768cba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=424570325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.424570325
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3131608803
Short name T464
Test name
Test status
Simulation time 39895973 ps
CPU time 0.56 seconds
Started Jul 05 04:37:47 PM PDT 24
Finished Jul 05 04:37:49 PM PDT 24
Peak memory 194696 kb
Host smart-20e889da-1077-4b8f-92b7-cbdb5ac2118e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131608803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3131608803
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1551650063
Short name T417
Test name
Test status
Simulation time 24791252 ps
CPU time 0.73 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 195984 kb
Host smart-2d71d489-a820-4279-8513-8a0903b5378c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551650063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1551650063
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.763509259
Short name T319
Test name
Test status
Simulation time 422098174 ps
CPU time 21.82 seconds
Started Jul 05 04:37:17 PM PDT 24
Finished Jul 05 04:37:46 PM PDT 24
Peak memory 197488 kb
Host smart-7171e6b2-2e0e-4c79-a8f5-9407c0bac520
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763509259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.763509259
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2109424546
Short name T650
Test name
Test status
Simulation time 661915019 ps
CPU time 1.04 seconds
Started Jul 05 04:37:24 PM PDT 24
Finished Jul 05 04:37:31 PM PDT 24
Peak memory 197260 kb
Host smart-e04d701a-64dd-4377-ba00-a20d962c52db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109424546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2109424546
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2579984339
Short name T318
Test name
Test status
Simulation time 176428846 ps
CPU time 1.17 seconds
Started Jul 05 04:37:38 PM PDT 24
Finished Jul 05 04:37:41 PM PDT 24
Peak memory 196792 kb
Host smart-df619a5d-17ac-4104-b4d5-88ca7ee33d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579984339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2579984339
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.756095844
Short name T302
Test name
Test status
Simulation time 870346424 ps
CPU time 3.45 seconds
Started Jul 05 04:37:36 PM PDT 24
Finished Jul 05 04:37:40 PM PDT 24
Peak memory 198784 kb
Host smart-8855c870-4861-420a-8731-44eb9569f489
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756095844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.756095844
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3868258085
Short name T12
Test name
Test status
Simulation time 129068652 ps
CPU time 2.41 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 197792 kb
Host smart-ca11e9e1-1e59-4512-baf9-9c9ef362cfd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868258085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3868258085
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2721914732
Short name T600
Test name
Test status
Simulation time 202986327 ps
CPU time 1.2 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:37:28 PM PDT 24
Peak memory 197660 kb
Host smart-2507f6c1-3f00-4efc-bf4c-75d4a358dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721914732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2721914732
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2168097705
Short name T622
Test name
Test status
Simulation time 37217129 ps
CPU time 0.94 seconds
Started Jul 05 04:37:18 PM PDT 24
Finished Jul 05 04:37:26 PM PDT 24
Peak memory 197308 kb
Host smart-4c6cc6de-e687-44a6-8266-ba7780304973
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168097705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2168097705
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2483537487
Short name T681
Test name
Test status
Simulation time 84715538 ps
CPU time 3.98 seconds
Started Jul 05 04:37:21 PM PDT 24
Finished Jul 05 04:37:35 PM PDT 24
Peak memory 198640 kb
Host smart-9b49a57e-5ba9-48d8-a606-664925e61c52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483537487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2483537487
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.707999090
Short name T463
Test name
Test status
Simulation time 249777253 ps
CPU time 1.15 seconds
Started Jul 05 04:37:33 PM PDT 24
Finished Jul 05 04:37:35 PM PDT 24
Peak memory 197104 kb
Host smart-ccae6e06-e257-4a45-9a4e-e5bdc557e94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707999090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.707999090
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.495731674
Short name T415
Test name
Test status
Simulation time 254475648 ps
CPU time 1.26 seconds
Started Jul 05 04:37:25 PM PDT 24
Finished Jul 05 04:37:32 PM PDT 24
Peak memory 197836 kb
Host smart-2f2e5f48-69fd-47db-8015-e000a863d106
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495731674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.495731674
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3372197281
Short name T480
Test name
Test status
Simulation time 2114003990 ps
CPU time 57.13 seconds
Started Jul 05 04:37:20 PM PDT 24
Finished Jul 05 04:38:24 PM PDT 24
Peak memory 198672 kb
Host smart-8420bb09-cf19-4cd1-b38f-a31f6e8e6f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372197281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3372197281
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.4185606370
Short name T141
Test name
Test status
Simulation time 40491733 ps
CPU time 0.59 seconds
Started Jul 05 04:35:47 PM PDT 24
Finished Jul 05 04:35:49 PM PDT 24
Peak memory 194876 kb
Host smart-2b4505c4-ad5f-4357-b682-73a35db6e168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185606370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.4185606370
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3635287947
Short name T153
Test name
Test status
Simulation time 122721093 ps
CPU time 0.64 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 195272 kb
Host smart-b3f25481-baeb-4ebe-9ad0-f1f840c17a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635287947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3635287947
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.349210494
Short name T197
Test name
Test status
Simulation time 801307936 ps
CPU time 26.69 seconds
Started Jul 05 04:35:46 PM PDT 24
Finished Jul 05 04:36:14 PM PDT 24
Peak memory 198528 kb
Host smart-154c142c-feb6-4f9f-9b55-5ebffadfa86a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349210494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.349210494
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2210154488
Short name T261
Test name
Test status
Simulation time 82180690 ps
CPU time 1.01 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:35:59 PM PDT 24
Peak memory 197108 kb
Host smart-4e56e5ee-3eed-4854-9b2b-2083dbf0ff32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210154488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2210154488
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.563375353
Short name T584
Test name
Test status
Simulation time 117984693 ps
CPU time 0.84 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 196908 kb
Host smart-2010a923-4e66-4076-8a6b-24f3079217fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563375353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.563375353
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3315292169
Short name T290
Test name
Test status
Simulation time 227411662 ps
CPU time 2.9 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 196920 kb
Host smart-59e0089e-63ef-4fa3-a27a-60aa1c6fc4f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315292169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3315292169
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1029200688
Short name T208
Test name
Test status
Simulation time 211054669 ps
CPU time 2.39 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 197808 kb
Host smart-06fb6764-1a12-49eb-9ec8-ff0388090bac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029200688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1029200688
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.19044012
Short name T282
Test name
Test status
Simulation time 23968107 ps
CPU time 0.95 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:36:03 PM PDT 24
Peak memory 196684 kb
Host smart-cc316268-d582-4019-8c2d-41cf7feb8163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19044012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.19044012
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2508783987
Short name T702
Test name
Test status
Simulation time 164274524 ps
CPU time 0.95 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 196156 kb
Host smart-5a2edfdc-b6b0-466c-bc0d-25599758fabf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508783987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2508783987
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2428602274
Short name T17
Test name
Test status
Simulation time 364850141 ps
CPU time 6.23 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:50 PM PDT 24
Peak memory 198640 kb
Host smart-0b0db87b-3473-485f-99fe-9195352dd530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428602274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2428602274
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2615573466
Short name T174
Test name
Test status
Simulation time 148499293 ps
CPU time 1.36 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 198592 kb
Host smart-b7aa15ba-08a4-4b46-8feb-e2d3197e9dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615573466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2615573466
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.946007067
Short name T465
Test name
Test status
Simulation time 231445600 ps
CPU time 0.9 seconds
Started Jul 05 04:35:49 PM PDT 24
Finished Jul 05 04:35:51 PM PDT 24
Peak memory 197028 kb
Host smart-5fe7e955-aa88-4d04-a820-3f71ffa76ee1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946007067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.946007067
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1043132931
Short name T344
Test name
Test status
Simulation time 17560090817 ps
CPU time 43.15 seconds
Started Jul 05 04:35:46 PM PDT 24
Finished Jul 05 04:36:31 PM PDT 24
Peak memory 198708 kb
Host smart-7684c0f1-3171-4302-a8a0-66f98829fc67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043132931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1043132931
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1624700590
Short name T43
Test name
Test status
Simulation time 35176076424 ps
CPU time 533.79 seconds
Started Jul 05 04:35:47 PM PDT 24
Finished Jul 05 04:44:42 PM PDT 24
Peak memory 198952 kb
Host smart-5d57ff20-7447-4607-8fcc-d3bce349b21c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1624700590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1624700590
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3457808059
Short name T179
Test name
Test status
Simulation time 22771714 ps
CPU time 0.63 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 194824 kb
Host smart-d1865214-7fed-46d6-b01e-c6b2dc8521ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457808059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3457808059
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2827711295
Short name T387
Test name
Test status
Simulation time 40601502 ps
CPU time 0.85 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:45 PM PDT 24
Peak memory 196128 kb
Host smart-0ac29ab4-78a5-4e24-bdc5-69675f809a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827711295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2827711295
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1714710666
Short name T489
Test name
Test status
Simulation time 132367048 ps
CPU time 6.99 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:36:05 PM PDT 24
Peak memory 198656 kb
Host smart-0b3061e6-7ce3-443a-9335-176b2bf7534e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714710666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1714710666
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3157629491
Short name T597
Test name
Test status
Simulation time 290038178 ps
CPU time 1.04 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 197356 kb
Host smart-f5d13872-4034-4c4e-ab22-31c7179fe461
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157629491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3157629491
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2644015573
Short name T36
Test name
Test status
Simulation time 40179694 ps
CPU time 0.81 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 196216 kb
Host smart-20b6b13a-2d6d-4511-92c9-8cc3f6a781c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644015573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2644015573
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3113157989
Short name T662
Test name
Test status
Simulation time 190163563 ps
CPU time 1.14 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 198000 kb
Host smart-0b95192a-474c-4423-bad1-b2d719622347
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113157989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3113157989
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1912283264
Short name T692
Test name
Test status
Simulation time 697799146 ps
CPU time 3.13 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:48 PM PDT 24
Peak memory 198728 kb
Host smart-34259487-00d1-4fbd-aafb-f7b93833cc97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912283264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1912283264
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.352962268
Short name T16
Test name
Test status
Simulation time 26481396 ps
CPU time 0.76 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 196048 kb
Host smart-86f236aa-75dd-4c74-8314-96cee35abf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352962268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.352962268
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2356997390
Short name T507
Test name
Test status
Simulation time 36872669 ps
CPU time 0.76 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 196128 kb
Host smart-e354830e-cd95-47cd-ae28-bf1599144a8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356997390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2356997390
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1388693195
Short name T687
Test name
Test status
Simulation time 59676693 ps
CPU time 2.6 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 198324 kb
Host smart-87f6f52d-9736-436c-9714-87ac27d2cfea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388693195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1388693195
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.518335221
Short name T335
Test name
Test status
Simulation time 42317983 ps
CPU time 1.06 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 197048 kb
Host smart-f64b4dbc-b440-41e2-86c9-195ee20b64a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518335221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.518335221
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3547002476
Short name T557
Test name
Test status
Simulation time 357155283 ps
CPU time 1.19 seconds
Started Jul 05 04:35:43 PM PDT 24
Finished Jul 05 04:35:45 PM PDT 24
Peak memory 197240 kb
Host smart-a5308207-7b3a-4b8a-95ae-3dee63431b46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547002476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3547002476
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3959071984
Short name T674
Test name
Test status
Simulation time 49313417476 ps
CPU time 162 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:38:43 PM PDT 24
Peak memory 198704 kb
Host smart-68ce8a4c-e93e-469b-8807-64fdaf07f64f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959071984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3959071984
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.411243614
Short name T529
Test name
Test status
Simulation time 16607514536 ps
CPU time 452.15 seconds
Started Jul 05 04:35:58 PM PDT 24
Finished Jul 05 04:43:32 PM PDT 24
Peak memory 198812 kb
Host smart-607bee26-e491-42da-9a61-af86b2ce3a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=411243614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.411243614
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1145538059
Short name T547
Test name
Test status
Simulation time 44820938 ps
CPU time 0.58 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 194676 kb
Host smart-adc0064e-6427-4a76-bb57-de7e53c258af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145538059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1145538059
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4259014650
Short name T522
Test name
Test status
Simulation time 26366451 ps
CPU time 0.78 seconds
Started Jul 05 04:35:47 PM PDT 24
Finished Jul 05 04:35:49 PM PDT 24
Peak memory 195832 kb
Host smart-8eed88a4-1041-4352-b440-d24d45e8f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259014650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4259014650
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1117726334
Short name T383
Test name
Test status
Simulation time 519251843 ps
CPU time 18.49 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:36:15 PM PDT 24
Peak memory 197652 kb
Host smart-cccf2542-92f2-4814-b3cf-2ee4b5db9e98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117726334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1117726334
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3702174848
Short name T128
Test name
Test status
Simulation time 63151888 ps
CPU time 0.84 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 196416 kb
Host smart-ca2396b9-8eeb-4419-b047-0788d7bda1ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702174848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3702174848
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3413578424
Short name T226
Test name
Test status
Simulation time 85650651 ps
CPU time 1.43 seconds
Started Jul 05 04:36:02 PM PDT 24
Finished Jul 05 04:36:06 PM PDT 24
Peak memory 197868 kb
Host smart-10af0d55-891f-4fa9-ac8d-02f91618a988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413578424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3413578424
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.461845006
Short name T633
Test name
Test status
Simulation time 78227141 ps
CPU time 3.1 seconds
Started Jul 05 04:35:47 PM PDT 24
Finished Jul 05 04:35:51 PM PDT 24
Peak memory 198592 kb
Host smart-6ba06a35-81ea-4191-a4e3-d4888340a599
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461845006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.461845006
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3960144659
Short name T119
Test name
Test status
Simulation time 110091850 ps
CPU time 1.03 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:47 PM PDT 24
Peak memory 196152 kb
Host smart-5f2be52f-e840-4e08-8a21-07ff0651e8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960144659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3960144659
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3016437501
Short name T116
Test name
Test status
Simulation time 39091532 ps
CPU time 0.91 seconds
Started Jul 05 04:35:46 PM PDT 24
Finished Jul 05 04:35:48 PM PDT 24
Peak memory 197092 kb
Host smart-ff065067-4d22-4e7d-8227-7d49ce5e717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016437501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3016437501
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3554924603
Short name T512
Test name
Test status
Simulation time 15877761 ps
CPU time 0.63 seconds
Started Jul 05 04:35:44 PM PDT 24
Finished Jul 05 04:35:46 PM PDT 24
Peak memory 195652 kb
Host smart-ed4071c3-3b9e-4200-8dc8-5caa03b60e77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554924603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3554924603
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3174493670
Short name T351
Test name
Test status
Simulation time 287509854 ps
CPU time 2.48 seconds
Started Jul 05 04:35:54 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 198532 kb
Host smart-341bfcc7-9d76-4361-8da9-fa85144d53ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174493670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3174493670
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2893094939
Short name T163
Test name
Test status
Simulation time 53935111 ps
CPU time 1.33 seconds
Started Jul 05 04:35:45 PM PDT 24
Finished Jul 05 04:35:48 PM PDT 24
Peak memory 197568 kb
Host smart-9ab194c5-2d48-42ee-900e-a742e35527d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893094939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2893094939
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1746352971
Short name T495
Test name
Test status
Simulation time 49527478 ps
CPU time 1.02 seconds
Started Jul 05 04:35:46 PM PDT 24
Finished Jul 05 04:35:49 PM PDT 24
Peak memory 196296 kb
Host smart-8a6dc43f-e3c5-4ea2-8c94-e2299c136372
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746352971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1746352971
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.828569460
Short name T263
Test name
Test status
Simulation time 93676126536 ps
CPU time 170.05 seconds
Started Jul 05 04:36:03 PM PDT 24
Finished Jul 05 04:38:55 PM PDT 24
Peak memory 198700 kb
Host smart-92344b16-7207-416e-a316-25bb215e3b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828569460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.828569460
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3011225895
Short name T521
Test name
Test status
Simulation time 218109989797 ps
CPU time 740.55 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:48:17 PM PDT 24
Peak memory 198840 kb
Host smart-022083da-1661-43bc-b1a9-0d1d9b47d256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3011225895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3011225895
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1084339245
Short name T631
Test name
Test status
Simulation time 13521784 ps
CPU time 0.6 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:36:03 PM PDT 24
Peak memory 195704 kb
Host smart-ec221376-efef-410e-8d6a-1a9e5f04ff7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084339245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1084339245
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.888252515
Short name T548
Test name
Test status
Simulation time 38958468 ps
CPU time 0.72 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 195904 kb
Host smart-1e99a11e-db04-483f-8b35-4fa6f146874c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888252515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.888252515
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1859031666
Short name T691
Test name
Test status
Simulation time 373229985 ps
CPU time 11.67 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:15 PM PDT 24
Peak memory 196224 kb
Host smart-a996aa39-8006-456f-93f7-61b4cda38646
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859031666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1859031666
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.466349795
Short name T447
Test name
Test status
Simulation time 131599148 ps
CPU time 0.87 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 196768 kb
Host smart-cde67a6c-aae0-49db-a0b0-242e83ae002d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466349795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.466349795
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1723164007
Short name T514
Test name
Test status
Simulation time 139598395 ps
CPU time 1.19 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 197188 kb
Host smart-18f279a6-17dc-4f3a-a206-59448ada6561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723164007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1723164007
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2074361515
Short name T459
Test name
Test status
Simulation time 89595409 ps
CPU time 3.23 seconds
Started Jul 05 04:36:02 PM PDT 24
Finished Jul 05 04:36:07 PM PDT 24
Peak memory 198580 kb
Host smart-af227ced-3f3a-4a2e-815b-c29d448d5223
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074361515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2074361515
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1103229859
Short name T246
Test name
Test status
Simulation time 354911554 ps
CPU time 3.38 seconds
Started Jul 05 04:35:51 PM PDT 24
Finished Jul 05 04:35:55 PM PDT 24
Peak memory 197692 kb
Host smart-3003c7e2-1ac8-47f6-be09-c129b701ee42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103229859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1103229859
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3836134082
Short name T713
Test name
Test status
Simulation time 50449691 ps
CPU time 1.02 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 196748 kb
Host smart-7a074064-4c05-4643-a279-175a0fa4b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836134082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3836134082
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3672171087
Short name T695
Test name
Test status
Simulation time 106524408 ps
CPU time 1.17 seconds
Started Jul 05 04:35:50 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 197528 kb
Host smart-90fe67f7-c370-42ea-a20d-48a9ebc6722e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672171087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3672171087
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1738515782
Short name T581
Test name
Test status
Simulation time 52797607 ps
CPU time 1.21 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:03 PM PDT 24
Peak memory 198572 kb
Host smart-54a2ab90-1161-4597-88d8-7b7be8424ed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738515782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1738515782
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2278821696
Short name T149
Test name
Test status
Simulation time 33013187 ps
CPU time 0.71 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 195728 kb
Host smart-ad13d73b-851f-4769-8ecf-c1969c2c15a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278821696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2278821696
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2075067426
Short name T349
Test name
Test status
Simulation time 63602215 ps
CPU time 1.32 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:01 PM PDT 24
Peak memory 198668 kb
Host smart-ae00c23a-92b8-4fef-8d6c-84a0bbaa8d69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075067426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2075067426
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3670352255
Short name T377
Test name
Test status
Simulation time 2375006344 ps
CPU time 33.02 seconds
Started Jul 05 04:35:53 PM PDT 24
Finished Jul 05 04:36:27 PM PDT 24
Peak memory 198684 kb
Host smart-bf130d30-ac64-43df-afda-68c961966941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670352255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3670352255
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3003163496
Short name T599
Test name
Test status
Simulation time 38285509 ps
CPU time 0.58 seconds
Started Jul 05 04:36:03 PM PDT 24
Finished Jul 05 04:36:05 PM PDT 24
Peak memory 194872 kb
Host smart-24b8342c-19b9-4bee-b367-2105b8ddeabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003163496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3003163496
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.345767311
Short name T267
Test name
Test status
Simulation time 414127171 ps
CPU time 0.87 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 197000 kb
Host smart-3fef036d-0a75-4e4c-9896-031921fa8e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345767311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.345767311
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2266097149
Short name T575
Test name
Test status
Simulation time 277904102 ps
CPU time 10.46 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:13 PM PDT 24
Peak memory 197656 kb
Host smart-5ae15af8-b2e5-4147-90cd-73141a0fc821
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266097149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2266097149
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2540486348
Short name T339
Test name
Test status
Simulation time 45741876 ps
CPU time 0.74 seconds
Started Jul 05 04:35:53 PM PDT 24
Finished Jul 05 04:35:55 PM PDT 24
Peak memory 195408 kb
Host smart-310c6dd4-82ab-445d-873e-27876b26d482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540486348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2540486348
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3209307313
Short name T284
Test name
Test status
Simulation time 48371225 ps
CPU time 1.31 seconds
Started Jul 05 04:35:57 PM PDT 24
Finished Jul 05 04:36:00 PM PDT 24
Peak memory 198764 kb
Host smart-17848485-e39b-476b-88e2-ff7889a02164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209307313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3209307313
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2208239997
Short name T147
Test name
Test status
Simulation time 23749618 ps
CPU time 1.11 seconds
Started Jul 05 04:35:51 PM PDT 24
Finished Jul 05 04:35:53 PM PDT 24
Peak memory 197820 kb
Host smart-34a5afb3-0a77-4274-9680-95d46654cce7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208239997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2208239997
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.131713589
Short name T19
Test name
Test status
Simulation time 278572583 ps
CPU time 1.03 seconds
Started Jul 05 04:35:59 PM PDT 24
Finished Jul 05 04:36:02 PM PDT 24
Peak memory 196160 kb
Host smart-e25bc1bd-673c-4072-8913-d14aa294b9fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131713589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.131713589
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3683612206
Short name T361
Test name
Test status
Simulation time 140211054 ps
CPU time 1.32 seconds
Started Jul 05 04:35:55 PM PDT 24
Finished Jul 05 04:35:58 PM PDT 24
Peak memory 197608 kb
Host smart-96e6a39d-311a-4cb4-8732-7085a5fbd9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683612206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3683612206
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2724013200
Short name T565
Test name
Test status
Simulation time 105632630 ps
CPU time 1.25 seconds
Started Jul 05 04:36:01 PM PDT 24
Finished Jul 05 04:36:04 PM PDT 24
Peak memory 197700 kb
Host smart-a3a8a328-8d7c-4bb2-8678-20b7b9e01a00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724013200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2724013200
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3864297892
Short name T626
Test name
Test status
Simulation time 779198463 ps
CPU time 2.25 seconds
Started Jul 05 04:36:00 PM PDT 24
Finished Jul 05 04:36:05 PM PDT 24
Peak memory 198636 kb
Host smart-1f7f2b03-9486-4192-a638-04ebed97567d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864297892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3864297892
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2039129415
Short name T175
Test name
Test status
Simulation time 285445128 ps
CPU time 1.32 seconds
Started Jul 05 04:35:50 PM PDT 24
Finished Jul 05 04:35:52 PM PDT 24
Peak memory 196164 kb
Host smart-39d0af98-d0b7-49f9-9f0a-a1f11c18cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039129415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2039129415
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4112692150
Short name T161
Test name
Test status
Simulation time 68404493 ps
CPU time 1.25 seconds
Started Jul 05 04:35:53 PM PDT 24
Finished Jul 05 04:35:55 PM PDT 24
Peak memory 196944 kb
Host smart-1fa68d8d-ad48-45c3-bcc2-51493af8c507
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112692150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4112692150
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2318159401
Short name T354
Test name
Test status
Simulation time 50964020201 ps
CPU time 45.32 seconds
Started Jul 05 04:35:56 PM PDT 24
Finished Jul 05 04:36:43 PM PDT 24
Peak memory 198848 kb
Host smart-1bc13281-e7ab-479f-a316-726e9b874e87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318159401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2318159401
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1950194881
Short name T879
Test name
Test status
Simulation time 151912820 ps
CPU time 1.21 seconds
Started Jul 05 04:21:57 PM PDT 24
Finished Jul 05 04:21:59 PM PDT 24
Peak memory 195036 kb
Host smart-75c2b009-b7ba-468a-b0d1-793e57f261e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1950194881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1950194881
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3112907537
Short name T919
Test name
Test status
Simulation time 147580325 ps
CPU time 1.01 seconds
Started Jul 05 04:19:22 PM PDT 24
Finished Jul 05 04:19:23 PM PDT 24
Peak memory 197692 kb
Host smart-c155b2b7-ab65-4d15-9e8c-d645cb620494
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112907537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3112907537
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3193288362
Short name T899
Test name
Test status
Simulation time 23285607 ps
CPU time 0.79 seconds
Started Jul 05 04:22:34 PM PDT 24
Finished Jul 05 04:22:35 PM PDT 24
Peak memory 196408 kb
Host smart-e6659149-33e0-407a-8430-4743024c0816
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3193288362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3193288362
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.191381543
Short name T878
Test name
Test status
Simulation time 47907828 ps
CPU time 1.35 seconds
Started Jul 05 04:19:05 PM PDT 24
Finished Jul 05 04:19:06 PM PDT 24
Peak memory 197128 kb
Host smart-a4a404e6-97a3-42c1-af7c-509a633ab801
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191381543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.191381543
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3351905428
Short name T844
Test name
Test status
Simulation time 52260336 ps
CPU time 1.35 seconds
Started Jul 05 04:22:31 PM PDT 24
Finished Jul 05 04:22:33 PM PDT 24
Peak memory 197052 kb
Host smart-bc52bcd1-7a5f-43e4-9edb-124764e48d27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3351905428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3351905428
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3639511822
Short name T869
Test name
Test status
Simulation time 53756876 ps
CPU time 0.84 seconds
Started Jul 05 04:17:42 PM PDT 24
Finished Jul 05 04:17:43 PM PDT 24
Peak memory 196556 kb
Host smart-dbffbfa5-8432-41dc-9f6b-8af2ac9e395b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639511822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3639511822
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3512223984
Short name T845
Test name
Test status
Simulation time 186592420 ps
CPU time 1.27 seconds
Started Jul 05 04:22:14 PM PDT 24
Finished Jul 05 04:22:16 PM PDT 24
Peak memory 195300 kb
Host smart-281c425a-6b11-4160-a033-897e1014192d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3512223984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3512223984
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744169316
Short name T902
Test name
Test status
Simulation time 160822462 ps
CPU time 0.91 seconds
Started Jul 05 04:22:14 PM PDT 24
Finished Jul 05 04:22:16 PM PDT 24
Peak memory 195088 kb
Host smart-8b38b216-5820-4222-ac33-6e975140bded
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744169316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2744169316
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3697298657
Short name T863
Test name
Test status
Simulation time 23998615 ps
CPU time 0.78 seconds
Started Jul 05 04:22:47 PM PDT 24
Finished Jul 05 04:22:49 PM PDT 24
Peak memory 194576 kb
Host smart-54a798f1-42cc-45fd-b157-9482093302f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3697298657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3697298657
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2903163844
Short name T903
Test name
Test status
Simulation time 75907292 ps
CPU time 0.89 seconds
Started Jul 05 04:23:08 PM PDT 24
Finished Jul 05 04:23:10 PM PDT 24
Peak memory 195652 kb
Host smart-2b719b76-4af2-4ffe-9408-cdfa376c477b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903163844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2903163844
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3586840426
Short name T860
Test name
Test status
Simulation time 128341929 ps
CPU time 1.21 seconds
Started Jul 05 04:22:47 PM PDT 24
Finished Jul 05 04:22:49 PM PDT 24
Peak memory 195656 kb
Host smart-87d0e755-143f-452f-b420-5cebd03f851a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3586840426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3586840426
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.771582104
Short name T866
Test name
Test status
Simulation time 145177369 ps
CPU time 1.41 seconds
Started Jul 05 04:22:36 PM PDT 24
Finished Jul 05 04:22:39 PM PDT 24
Peak memory 194828 kb
Host smart-f323a141-b51a-45cb-b18d-37d94b12fdb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771582104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.771582104
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.996647554
Short name T882
Test name
Test status
Simulation time 294848674 ps
CPU time 1.08 seconds
Started Jul 05 04:22:41 PM PDT 24
Finished Jul 05 04:22:42 PM PDT 24
Peak memory 195744 kb
Host smart-b6365c44-29f2-4cd4-a975-5f244c49c550
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=996647554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.996647554
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885892045
Short name T892
Test name
Test status
Simulation time 85832762 ps
CPU time 1.23 seconds
Started Jul 05 04:22:27 PM PDT 24
Finished Jul 05 04:22:29 PM PDT 24
Peak memory 196120 kb
Host smart-6cc83fff-f39f-4037-8491-f51d53233714
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885892045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.885892045
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1349313702
Short name T906
Test name
Test status
Simulation time 284164713 ps
CPU time 0.89 seconds
Started Jul 05 04:22:40 PM PDT 24
Finished Jul 05 04:22:42 PM PDT 24
Peak memory 196216 kb
Host smart-ba024303-09ad-41dd-bcee-4a17f4ff4b81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1349313702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1349313702
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1637754765
Short name T842
Test name
Test status
Simulation time 92897116 ps
CPU time 1.36 seconds
Started Jul 05 04:22:40 PM PDT 24
Finished Jul 05 04:22:43 PM PDT 24
Peak memory 195356 kb
Host smart-1f4c696f-9c1c-4b0b-89e3-1c5abee6df05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637754765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1637754765
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4257957842
Short name T913
Test name
Test status
Simulation time 392559977 ps
CPU time 1.06 seconds
Started Jul 05 04:22:40 PM PDT 24
Finished Jul 05 04:22:42 PM PDT 24
Peak memory 194476 kb
Host smart-6c14dd90-bc2b-425b-b317-9645fa83bf1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4257957842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4257957842
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.187693324
Short name T874
Test name
Test status
Simulation time 75216720 ps
CPU time 1.17 seconds
Started Jul 05 04:21:05 PM PDT 24
Finished Jul 05 04:21:06 PM PDT 24
Peak memory 196864 kb
Host smart-a55f6acd-a3e1-4f17-be98-549e18221230
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187693324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.187693324
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.736849993
Short name T880
Test name
Test status
Simulation time 32515375 ps
CPU time 0.9 seconds
Started Jul 05 04:18:36 PM PDT 24
Finished Jul 05 04:18:38 PM PDT 24
Peak memory 196768 kb
Host smart-f4240d78-54a9-44f3-a7a2-2ce191c1c38d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=736849993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.736849993
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.680935383
Short name T856
Test name
Test status
Simulation time 167125381 ps
CPU time 1.07 seconds
Started Jul 05 04:22:27 PM PDT 24
Finished Jul 05 04:22:29 PM PDT 24
Peak memory 195508 kb
Host smart-29e1ae88-d67a-43d1-a931-86e3365683f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680935383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.680935383
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1677778720
Short name T898
Test name
Test status
Simulation time 125248642 ps
CPU time 1.2 seconds
Started Jul 05 04:22:47 PM PDT 24
Finished Jul 05 04:22:48 PM PDT 24
Peak memory 196444 kb
Host smart-832b912e-be18-4bf9-8094-22f4931f6ea0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1677778720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1677778720
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2961920227
Short name T929
Test name
Test status
Simulation time 190925468 ps
CPU time 1.33 seconds
Started Jul 05 04:19:48 PM PDT 24
Finished Jul 05 04:19:50 PM PDT 24
Peak memory 195924 kb
Host smart-78308c05-c7ec-4a7c-8985-95645f2cd158
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961920227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2961920227
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3279527307
Short name T916
Test name
Test status
Simulation time 186814569 ps
CPU time 0.9 seconds
Started Jul 05 04:22:49 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 196904 kb
Host smart-13232669-8b53-4561-9d33-564ec7b0f896
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3279527307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3279527307
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1146947369
Short name T924
Test name
Test status
Simulation time 122935517 ps
CPU time 1.25 seconds
Started Jul 05 04:23:02 PM PDT 24
Finished Jul 05 04:23:04 PM PDT 24
Peak memory 196652 kb
Host smart-8c4e6ee8-c32e-4446-8acd-9fe830b3ad0e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146947369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1146947369
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4162855355
Short name T923
Test name
Test status
Simulation time 208168525 ps
CPU time 0.89 seconds
Started Jul 05 04:22:33 PM PDT 24
Finished Jul 05 04:22:35 PM PDT 24
Peak memory 195620 kb
Host smart-6e5d8ca9-9311-456b-a76a-390bcc68bbd3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4162855355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4162855355
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1632828577
Short name T884
Test name
Test status
Simulation time 122993576 ps
CPU time 0.84 seconds
Started Jul 05 04:18:29 PM PDT 24
Finished Jul 05 04:18:31 PM PDT 24
Peak memory 195560 kb
Host smart-90f5bb1c-f4b5-4ab3-95b2-e64a7804972a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632828577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1632828577
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2237087245
Short name T871
Test name
Test status
Simulation time 87992219 ps
CPU time 1.32 seconds
Started Jul 05 04:22:04 PM PDT 24
Finished Jul 05 04:22:07 PM PDT 24
Peak memory 195244 kb
Host smart-e72c2bc0-5bd0-489d-8c03-821835954b97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2237087245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2237087245
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2457683163
Short name T886
Test name
Test status
Simulation time 33373187 ps
CPU time 0.84 seconds
Started Jul 05 04:18:58 PM PDT 24
Finished Jul 05 04:18:59 PM PDT 24
Peak memory 196356 kb
Host smart-b91a426e-6f42-4779-a46c-155699dc0763
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457683163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2457683163
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1362651212
Short name T909
Test name
Test status
Simulation time 115388921 ps
CPU time 0.73 seconds
Started Jul 05 04:19:15 PM PDT 24
Finished Jul 05 04:19:16 PM PDT 24
Peak memory 195052 kb
Host smart-9ce20f67-a6c6-40ce-9a8a-afa058f62f69
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1362651212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1362651212
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.150719531
Short name T859
Test name
Test status
Simulation time 428636006 ps
CPU time 1.04 seconds
Started Jul 05 04:23:18 PM PDT 24
Finished Jul 05 04:23:20 PM PDT 24
Peak memory 198264 kb
Host smart-41810e7b-fa71-403a-bf3e-70a229a717b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150719531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.150719531
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2699431455
Short name T901
Test name
Test status
Simulation time 35761297 ps
CPU time 1.05 seconds
Started Jul 05 04:22:25 PM PDT 24
Finished Jul 05 04:22:27 PM PDT 24
Peak memory 196760 kb
Host smart-e0755ddf-9dcf-409b-a063-c7c689383b00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2699431455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2699431455
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703702559
Short name T846
Test name
Test status
Simulation time 55092579 ps
CPU time 1 seconds
Started Jul 05 04:18:42 PM PDT 24
Finished Jul 05 04:18:44 PM PDT 24
Peak memory 196932 kb
Host smart-619c874a-8876-40c6-8d62-aa48ad9031c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703702559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1703702559
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1844282991
Short name T893
Test name
Test status
Simulation time 26742438 ps
CPU time 0.85 seconds
Started Jul 05 04:22:18 PM PDT 24
Finished Jul 05 04:22:20 PM PDT 24
Peak memory 195656 kb
Host smart-3896ff17-6105-4bbf-bbfe-3fb103b392ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1844282991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1844282991
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2667403895
Short name T851
Test name
Test status
Simulation time 50720860 ps
CPU time 0.95 seconds
Started Jul 05 04:19:09 PM PDT 24
Finished Jul 05 04:19:10 PM PDT 24
Peak memory 197508 kb
Host smart-be038961-2347-478e-8b25-586db44f9231
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667403895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2667403895
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2552310678
Short name T915
Test name
Test status
Simulation time 61246469 ps
CPU time 1.21 seconds
Started Jul 05 04:22:04 PM PDT 24
Finished Jul 05 04:22:07 PM PDT 24
Peak memory 195456 kb
Host smart-e838ee76-1c23-4473-b7ba-6e93678e2ec1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2552310678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2552310678
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3844265973
Short name T928
Test name
Test status
Simulation time 188002119 ps
CPU time 1.15 seconds
Started Jul 05 04:22:16 PM PDT 24
Finished Jul 05 04:22:18 PM PDT 24
Peak memory 195288 kb
Host smart-a4924613-5429-4839-8ce6-06f6d3bfa048
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844265973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3844265973
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2129042078
Short name T911
Test name
Test status
Simulation time 246662513 ps
CPU time 1.13 seconds
Started Jul 05 04:22:15 PM PDT 24
Finished Jul 05 04:22:17 PM PDT 24
Peak memory 196964 kb
Host smart-c4819b7c-2594-482f-bff2-8e2cd68f6120
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2129042078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2129042078
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3810093032
Short name T888
Test name
Test status
Simulation time 44546759 ps
CPU time 1.32 seconds
Started Jul 05 04:22:02 PM PDT 24
Finished Jul 05 04:22:04 PM PDT 24
Peak memory 193824 kb
Host smart-c3d0cd2f-53a6-4dd7-895f-66521d341d18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810093032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3810093032
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4094174506
Short name T875
Test name
Test status
Simulation time 53397775 ps
CPU time 1.15 seconds
Started Jul 05 04:20:22 PM PDT 24
Finished Jul 05 04:20:24 PM PDT 24
Peak memory 196760 kb
Host smart-3135c72f-b3ed-4f51-a4a2-8dee67d752e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4094174506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4094174506
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3507029714
Short name T907
Test name
Test status
Simulation time 719510968 ps
CPU time 0.98 seconds
Started Jul 05 04:22:02 PM PDT 24
Finished Jul 05 04:22:04 PM PDT 24
Peak memory 194816 kb
Host smart-169f33cb-cda0-4481-bcf6-4e15815b258a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507029714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3507029714
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.698104634
Short name T876
Test name
Test status
Simulation time 114707167 ps
CPU time 1.19 seconds
Started Jul 05 04:19:04 PM PDT 24
Finished Jul 05 04:19:05 PM PDT 24
Peak memory 198276 kb
Host smart-0a2700bc-3f8c-4368-a69b-356fd85236ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=698104634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.698104634
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.231703855
Short name T854
Test name
Test status
Simulation time 38083717 ps
CPU time 0.72 seconds
Started Jul 05 04:22:02 PM PDT 24
Finished Jul 05 04:22:04 PM PDT 24
Peak memory 193224 kb
Host smart-955ab3b3-8813-491d-8bef-4bad91943f93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231703855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.231703855
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2403207609
Short name T918
Test name
Test status
Simulation time 56453433 ps
CPU time 1 seconds
Started Jul 05 04:22:02 PM PDT 24
Finished Jul 05 04:22:04 PM PDT 24
Peak memory 195684 kb
Host smart-40ccfb42-932b-41b1-8923-b13231755cd2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2403207609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2403207609
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3587736425
Short name T867
Test name
Test status
Simulation time 121746714 ps
CPU time 1.22 seconds
Started Jul 05 04:20:46 PM PDT 24
Finished Jul 05 04:20:47 PM PDT 24
Peak memory 198408 kb
Host smart-a698d295-c0c8-41f1-a0e6-edd5fc57116d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587736425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3587736425
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3785271752
Short name T843
Test name
Test status
Simulation time 23997817 ps
CPU time 0.79 seconds
Started Jul 05 04:22:17 PM PDT 24
Finished Jul 05 04:22:18 PM PDT 24
Peak memory 195744 kb
Host smart-9f4ffb2f-3021-404d-b526-0599f720810b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3785271752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3785271752
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4211655190
Short name T934
Test name
Test status
Simulation time 552390760 ps
CPU time 1.16 seconds
Started Jul 05 04:21:47 PM PDT 24
Finished Jul 05 04:21:49 PM PDT 24
Peak memory 196964 kb
Host smart-0eead37a-8b57-43ef-8cd4-96669821b5e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211655190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4211655190
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2402643461
Short name T936
Test name
Test status
Simulation time 57684709 ps
CPU time 0.9 seconds
Started Jul 05 04:22:23 PM PDT 24
Finished Jul 05 04:22:25 PM PDT 24
Peak memory 195552 kb
Host smart-5c02ecb5-b97a-4ccf-a7c3-e726e05dad77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2402643461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2402643461
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.177171264
Short name T894
Test name
Test status
Simulation time 48777489 ps
CPU time 1.02 seconds
Started Jul 05 04:20:40 PM PDT 24
Finished Jul 05 04:20:42 PM PDT 24
Peak memory 196620 kb
Host smart-86a1b564-041d-4ca3-87ee-f3c8c8b62ddf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177171264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.177171264
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2758304411
Short name T931
Test name
Test status
Simulation time 67807577 ps
CPU time 0.99 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:12 PM PDT 24
Peak memory 195496 kb
Host smart-907bd15f-62cb-4533-bb88-5febf4a6ca61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2758304411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2758304411
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623880753
Short name T920
Test name
Test status
Simulation time 573862573 ps
CPU time 0.99 seconds
Started Jul 05 04:22:28 PM PDT 24
Finished Jul 05 04:22:30 PM PDT 24
Peak memory 193868 kb
Host smart-cef23323-4ec9-492d-b486-13c150ad762d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623880753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.623880753
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3425353126
Short name T868
Test name
Test status
Simulation time 355508200 ps
CPU time 1.12 seconds
Started Jul 05 04:22:10 PM PDT 24
Finished Jul 05 04:22:12 PM PDT 24
Peak memory 195524 kb
Host smart-dee944f3-e054-445f-97d4-da010d81a7be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3425353126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3425353126
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3169108542
Short name T858
Test name
Test status
Simulation time 254069149 ps
CPU time 0.96 seconds
Started Jul 05 04:20:15 PM PDT 24
Finished Jul 05 04:20:18 PM PDT 24
Peak memory 198180 kb
Host smart-5613db4b-188e-45fb-ae86-3c33a191bd89
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169108542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3169108542
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2111279563
Short name T865
Test name
Test status
Simulation time 110165637 ps
CPU time 1.4 seconds
Started Jul 05 04:19:13 PM PDT 24
Finished Jul 05 04:19:15 PM PDT 24
Peak memory 198300 kb
Host smart-ddd03604-0934-41e2-a091-3502b36827b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2111279563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2111279563
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884880604
Short name T917
Test name
Test status
Simulation time 48522736 ps
CPU time 1.33 seconds
Started Jul 05 04:22:12 PM PDT 24
Finished Jul 05 04:22:14 PM PDT 24
Peak memory 196280 kb
Host smart-b865eb0f-fc56-46ba-bae7-42138b88c5d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884880604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.884880604
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.705040634
Short name T927
Test name
Test status
Simulation time 37414900 ps
CPU time 1.11 seconds
Started Jul 05 04:20:19 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 196228 kb
Host smart-7dfea7e4-c6c7-4b0d-9856-767c3bdcbf0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=705040634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.705040634
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1618792021
Short name T891
Test name
Test status
Simulation time 107072114 ps
CPU time 1.01 seconds
Started Jul 05 04:21:04 PM PDT 24
Finished Jul 05 04:21:06 PM PDT 24
Peak memory 196896 kb
Host smart-38e5e678-cda6-4bcc-83d3-439607f22922
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618792021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1618792021
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3560041451
Short name T883
Test name
Test status
Simulation time 257073143 ps
CPU time 1 seconds
Started Jul 05 04:22:30 PM PDT 24
Finished Jul 05 04:22:31 PM PDT 24
Peak memory 195896 kb
Host smart-6529700a-e868-4969-9a98-3ca6c0cc3798
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3560041451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3560041451
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1326896306
Short name T905
Test name
Test status
Simulation time 73562996 ps
CPU time 0.89 seconds
Started Jul 05 04:22:14 PM PDT 24
Finished Jul 05 04:22:16 PM PDT 24
Peak memory 194904 kb
Host smart-bb21b0c0-d0d0-4d2e-b133-9b1efe404678
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326896306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1326896306
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.348019866
Short name T861
Test name
Test status
Simulation time 45698078 ps
CPU time 1.26 seconds
Started Jul 05 04:22:31 PM PDT 24
Finished Jul 05 04:22:33 PM PDT 24
Peak memory 198236 kb
Host smart-166e5cc2-2f68-46ac-9db2-97cb2692006b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=348019866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.348019866
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1938663576
Short name T885
Test name
Test status
Simulation time 383745970 ps
CPU time 1.15 seconds
Started Jul 05 04:19:15 PM PDT 24
Finished Jul 05 04:19:16 PM PDT 24
Peak memory 196980 kb
Host smart-409449f8-5f86-4636-bed9-3d6bb58be24f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938663576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1938663576
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.462950662
Short name T922
Test name
Test status
Simulation time 76121843 ps
CPU time 1.31 seconds
Started Jul 05 04:20:38 PM PDT 24
Finished Jul 05 04:20:39 PM PDT 24
Peak memory 196112 kb
Host smart-bc03098b-5d26-4be9-afdd-c5308b1514af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=462950662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.462950662
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1255227619
Short name T925
Test name
Test status
Simulation time 176896161 ps
CPU time 1.19 seconds
Started Jul 05 04:23:08 PM PDT 24
Finished Jul 05 04:23:10 PM PDT 24
Peak memory 196064 kb
Host smart-b3bfddc2-991d-4448-b6d8-36e7478727e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255227619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1255227619
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1594180025
Short name T914
Test name
Test status
Simulation time 97239307 ps
CPU time 1.19 seconds
Started Jul 05 04:22:43 PM PDT 24
Finished Jul 05 04:22:44 PM PDT 24
Peak memory 197096 kb
Host smart-6c678fdc-831e-4c9b-8f6f-c00bf66ee752
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1594180025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1594180025
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.23490032
Short name T935
Test name
Test status
Simulation time 240623675 ps
CPU time 1.59 seconds
Started Jul 05 04:20:08 PM PDT 24
Finished Jul 05 04:20:10 PM PDT 24
Peak memory 198248 kb
Host smart-1d1af4fb-05a8-4eb5-9ae1-6c5812fe3624
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23490032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.23490032
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.42118335
Short name T873
Test name
Test status
Simulation time 99326575 ps
CPU time 1.4 seconds
Started Jul 05 04:23:05 PM PDT 24
Finished Jul 05 04:23:08 PM PDT 24
Peak memory 196092 kb
Host smart-6c7efd7c-c0d4-4b84-b534-fa90b23470e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=42118335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.42118335
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3594393905
Short name T839
Test name
Test status
Simulation time 47710745 ps
CPU time 0.91 seconds
Started Jul 05 04:18:29 PM PDT 24
Finished Jul 05 04:18:31 PM PDT 24
Peak memory 195480 kb
Host smart-1494fb6e-ee63-4a09-baf7-62b2d75b84bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594393905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3594393905
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2893276895
Short name T849
Test name
Test status
Simulation time 38371390 ps
CPU time 0.92 seconds
Started Jul 05 04:21:17 PM PDT 24
Finished Jul 05 04:21:18 PM PDT 24
Peak memory 196640 kb
Host smart-d271fabe-2957-4dda-b247-c35cd21ed735
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2893276895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2893276895
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1555103389
Short name T900
Test name
Test status
Simulation time 68453053 ps
CPU time 1.28 seconds
Started Jul 05 04:20:19 PM PDT 24
Finished Jul 05 04:20:23 PM PDT 24
Peak memory 196904 kb
Host smart-834be48c-16b8-4a6a-90a5-07bdfe466df2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555103389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1555103389
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3833799842
Short name T841
Test name
Test status
Simulation time 80974805 ps
CPU time 1.51 seconds
Started Jul 05 04:20:40 PM PDT 24
Finished Jul 05 04:20:42 PM PDT 24
Peak memory 196960 kb
Host smart-596b5d5d-1fd7-48cf-bb02-26e8d9241e1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3833799842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3833799842
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.306032772
Short name T932
Test name
Test status
Simulation time 36778907 ps
CPU time 0.91 seconds
Started Jul 05 04:17:34 PM PDT 24
Finished Jul 05 04:17:35 PM PDT 24
Peak memory 196780 kb
Host smart-4f865ac1-b2a0-4bc8-b696-4d310e8789c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306032772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.306032772
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1045691798
Short name T877
Test name
Test status
Simulation time 71236782 ps
CPU time 1.44 seconds
Started Jul 05 04:23:05 PM PDT 24
Finished Jul 05 04:23:08 PM PDT 24
Peak memory 195896 kb
Host smart-1af2edbc-ea60-4fdf-be70-de4a936ede15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1045691798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1045691798
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.160816485
Short name T872
Test name
Test status
Simulation time 444504729 ps
CPU time 0.93 seconds
Started Jul 05 04:21:26 PM PDT 24
Finished Jul 05 04:21:27 PM PDT 24
Peak memory 196820 kb
Host smart-266a24b7-a473-4347-9e7c-56f3165142c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160816485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.160816485
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3657390799
Short name T926
Test name
Test status
Simulation time 139358087 ps
CPU time 0.8 seconds
Started Jul 05 04:22:27 PM PDT 24
Finished Jul 05 04:22:28 PM PDT 24
Peak memory 194372 kb
Host smart-44b6d402-6f16-479a-bd30-4a083e1535a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3657390799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3657390799
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3856784728
Short name T881
Test name
Test status
Simulation time 290078604 ps
CPU time 1.23 seconds
Started Jul 05 04:18:49 PM PDT 24
Finished Jul 05 04:18:51 PM PDT 24
Peak memory 197220 kb
Host smart-39f146bc-9b11-49f1-85db-d882fcbd5a1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856784728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3856784728
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.361179110
Short name T840
Test name
Test status
Simulation time 46555746 ps
CPU time 1.15 seconds
Started Jul 05 04:22:42 PM PDT 24
Finished Jul 05 04:22:44 PM PDT 24
Peak memory 196848 kb
Host smart-a0d1144f-7b4f-40a9-acd2-bf52df9062dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=361179110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.361179110
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926653380
Short name T889
Test name
Test status
Simulation time 51632262 ps
CPU time 1.27 seconds
Started Jul 05 04:20:55 PM PDT 24
Finished Jul 05 04:20:57 PM PDT 24
Peak memory 196676 kb
Host smart-3a020853-3f58-45ed-b9df-a3a711b036a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926653380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.926653380
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3453400577
Short name T855
Test name
Test status
Simulation time 66339562 ps
CPU time 0.7 seconds
Started Jul 05 04:22:46 PM PDT 24
Finished Jul 05 04:22:47 PM PDT 24
Peak memory 193460 kb
Host smart-64c896a4-9f2c-437d-b6f9-57c5c39f6585
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3453400577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3453400577
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1573726120
Short name T895
Test name
Test status
Simulation time 49213756 ps
CPU time 0.96 seconds
Started Jul 05 04:22:20 PM PDT 24
Finished Jul 05 04:22:22 PM PDT 24
Peak memory 197732 kb
Host smart-ed4840dc-fe56-42f2-a841-3e756dfbc6cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573726120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1573726120
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2335101030
Short name T853
Test name
Test status
Simulation time 204572592 ps
CPU time 1.01 seconds
Started Jul 05 04:22:41 PM PDT 24
Finished Jul 05 04:22:43 PM PDT 24
Peak memory 194892 kb
Host smart-04bc191c-b4c7-4ba9-8cc1-213479f14759
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2335101030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2335101030
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2858716690
Short name T887
Test name
Test status
Simulation time 127363720 ps
CPU time 1.14 seconds
Started Jul 05 04:21:10 PM PDT 24
Finished Jul 05 04:21:12 PM PDT 24
Peak memory 196996 kb
Host smart-6b01ba8b-1474-419a-8031-49aca865a95c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858716690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2858716690
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.35372903
Short name T852
Test name
Test status
Simulation time 356823876 ps
CPU time 1.61 seconds
Started Jul 05 04:18:27 PM PDT 24
Finished Jul 05 04:18:29 PM PDT 24
Peak memory 198260 kb
Host smart-a403c30f-667d-4edf-8fe8-e091aba6322c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=35372903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.35372903
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3624302893
Short name T890
Test name
Test status
Simulation time 28661165 ps
CPU time 0.91 seconds
Started Jul 05 04:20:06 PM PDT 24
Finished Jul 05 04:20:07 PM PDT 24
Peak memory 198100 kb
Host smart-5130a240-0bfc-4ba8-8bed-4f4384648237
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624302893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3624302893
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4278906779
Short name T848
Test name
Test status
Simulation time 471216689 ps
CPU time 1.1 seconds
Started Jul 05 04:22:19 PM PDT 24
Finished Jul 05 04:22:20 PM PDT 24
Peak memory 197584 kb
Host smart-2048b5cd-a391-4eb1-b9f0-47e139c2ca7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4278906779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4278906779
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3544904451
Short name T904
Test name
Test status
Simulation time 103421412 ps
CPU time 1.01 seconds
Started Jul 05 04:23:02 PM PDT 24
Finished Jul 05 04:23:04 PM PDT 24
Peak memory 195288 kb
Host smart-d88a3021-1527-45e5-b709-1f3950d652b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544904451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3544904451
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3974545626
Short name T938
Test name
Test status
Simulation time 1563669119 ps
CPU time 1.5 seconds
Started Jul 05 04:20:37 PM PDT 24
Finished Jul 05 04:20:39 PM PDT 24
Peak memory 197020 kb
Host smart-855fe596-b942-46a1-80dc-eb5b2552d616
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3974545626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3974545626
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3952611829
Short name T937
Test name
Test status
Simulation time 814324942 ps
CPU time 1.06 seconds
Started Jul 05 04:22:18 PM PDT 24
Finished Jul 05 04:22:20 PM PDT 24
Peak memory 195252 kb
Host smart-7bdccd90-8971-4753-948f-7552177bc959
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952611829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3952611829
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3033574575
Short name T930
Test name
Test status
Simulation time 60521058 ps
CPU time 1.08 seconds
Started Jul 05 04:23:18 PM PDT 24
Finished Jul 05 04:23:19 PM PDT 24
Peak memory 196148 kb
Host smart-443ccab2-8bcf-457c-87eb-a10ac01380e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3033574575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3033574575
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4268101786
Short name T912
Test name
Test status
Simulation time 300585179 ps
CPU time 1.49 seconds
Started Jul 05 04:20:06 PM PDT 24
Finished Jul 05 04:20:08 PM PDT 24
Peak memory 197016 kb
Host smart-231faf9b-d833-41cb-a141-8c9eb9b58c8c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268101786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4268101786
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3668522789
Short name T862
Test name
Test status
Simulation time 675662298 ps
CPU time 0.9 seconds
Started Jul 05 04:23:03 PM PDT 24
Finished Jul 05 04:23:04 PM PDT 24
Peak memory 196368 kb
Host smart-5ec61411-8dfa-4f24-a55b-f07cd4e09a38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3668522789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3668522789
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2172401188
Short name T850
Test name
Test status
Simulation time 186752601 ps
CPU time 0.83 seconds
Started Jul 05 04:22:06 PM PDT 24
Finished Jul 05 04:22:08 PM PDT 24
Peak memory 194844 kb
Host smart-351ff5e6-7264-45cf-87e4-277e54aecee1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172401188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2172401188
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2009489462
Short name T933
Test name
Test status
Simulation time 46255342 ps
CPU time 1.21 seconds
Started Jul 05 04:22:03 PM PDT 24
Finished Jul 05 04:22:06 PM PDT 24
Peak memory 194464 kb
Host smart-e3a69875-cb99-402f-bc43-49c4c716d34e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2009489462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2009489462
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4158996008
Short name T870
Test name
Test status
Simulation time 40498354 ps
CPU time 0.88 seconds
Started Jul 05 04:22:12 PM PDT 24
Finished Jul 05 04:22:13 PM PDT 24
Peak memory 196268 kb
Host smart-413c531e-d392-44f2-830d-fcc7d7865cc7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158996008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4158996008
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2911447371
Short name T896
Test name
Test status
Simulation time 83798700 ps
CPU time 1.38 seconds
Started Jul 05 04:21:04 PM PDT 24
Finished Jul 05 04:21:06 PM PDT 24
Peak memory 196776 kb
Host smart-a05b48c2-8d26-44ec-9f88-53a77d9771a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2911447371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2911447371
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3789529239
Short name T857
Test name
Test status
Simulation time 80095292 ps
CPU time 0.89 seconds
Started Jul 05 04:21:06 PM PDT 24
Finished Jul 05 04:21:08 PM PDT 24
Peak memory 195840 kb
Host smart-1cce46a3-ebb5-4458-94f8-2734a412e2ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789529239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3789529239
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2016608331
Short name T897
Test name
Test status
Simulation time 37815909 ps
CPU time 1.04 seconds
Started Jul 05 04:23:13 PM PDT 24
Finished Jul 05 04:23:21 PM PDT 24
Peak memory 195992 kb
Host smart-19906871-52c2-4b37-824c-38b9bc812a94
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2016608331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2016608331
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.478714766
Short name T910
Test name
Test status
Simulation time 171568546 ps
CPU time 1.53 seconds
Started Jul 05 04:22:28 PM PDT 24
Finished Jul 05 04:22:31 PM PDT 24
Peak memory 195052 kb
Host smart-e370031a-16b0-4be0-984e-330d62127e42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478714766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.478714766
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2302222384
Short name T921
Test name
Test status
Simulation time 212470457 ps
CPU time 1.14 seconds
Started Jul 05 04:22:28 PM PDT 24
Finished Jul 05 04:22:30 PM PDT 24
Peak memory 193996 kb
Host smart-df6f6665-5a6d-494a-aba4-3bef160cb73f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2302222384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2302222384
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1831517923
Short name T847
Test name
Test status
Simulation time 70701455 ps
CPU time 1.19 seconds
Started Jul 05 04:22:49 PM PDT 24
Finished Jul 05 04:22:51 PM PDT 24
Peak memory 196812 kb
Host smart-445a9a6c-2d02-49c6-ab0e-f684b94b71e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831517923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1831517923
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.992562874
Short name T864
Test name
Test status
Simulation time 77279944 ps
CPU time 1.22 seconds
Started Jul 05 04:22:35 PM PDT 24
Finished Jul 05 04:22:38 PM PDT 24
Peak memory 198092 kb
Host smart-4bb0f0cc-faf1-4936-87a4-137bf0b4f51f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=992562874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.992562874
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1036608343
Short name T908
Test name
Test status
Simulation time 30411637 ps
CPU time 0.87 seconds
Started Jul 05 04:22:13 PM PDT 24
Finished Jul 05 04:22:15 PM PDT 24
Peak memory 194184 kb
Host smart-9e235036-2111-49e1-bae6-0d085c5e4103
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036608343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1036608343
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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