Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4498331	1			T22	1		T23	69		T24	102
all_pins[1]	4498331	1			T22	1		T23	69		T24	102
all_pins[2]	4498331	1			T22	1		T23	69		T24	102
all_pins[3]	4498331	1			T22	1		T23	69		T24	102
all_pins[4]	4498331	1			T22	1		T23	69		T24	102
all_pins[5]	4498331	1			T22	1		T23	69		T24	102
all_pins[6]	4498331	1			T22	1		T23	69		T24	102
all_pins[7]	4498331	1			T22	1		T23	69		T24	102
all_pins[8]	4498331	1			T22	1		T23	69		T24	102
all_pins[9]	4498331	1			T22	1		T23	69		T24	102
all_pins[10]	4498331	1			T22	1		T23	69		T24	102
all_pins[11]	4498331	1			T22	1		T23	69		T24	102
all_pins[12]	4498331	1			T22	1		T23	69		T24	102
all_pins[13]	4498331	1			T22	1		T23	69		T24	102
all_pins[14]	4498331	1			T22	1		T23	69		T24	102
all_pins[15]	4498331	1			T22	1		T23	69		T24	102
all_pins[16]	4498331	1			T22	1		T23	69		T24	102
all_pins[17]	4498331	1			T22	1		T23	69		T24	102
all_pins[18]	4498331	1			T22	1		T23	69		T24	102
all_pins[19]	4498331	1			T22	1		T23	69		T24	102
all_pins[20]	4498331	1			T22	1		T23	69		T24	102
all_pins[21]	4498331	1			T22	1		T23	69		T24	102
all_pins[22]	4498331	1			T22	1		T23	69		T24	102
all_pins[23]	4498331	1			T22	1		T23	69		T24	102
all_pins[24]	4498331	1			T22	1		T23	69		T24	102
all_pins[25]	4498331	1			T22	1		T23	69		T24	102
all_pins[26]	4498331	1			T22	1		T23	69		T24	102
all_pins[27]	4498331	1			T22	1		T23	69		T24	102
all_pins[28]	4498331	1			T22	1		T23	69		T24	102
all_pins[29]	4498331	1			T22	1		T23	69		T24	102
all_pins[30]	4498331	1			T22	1		T23	69		T24	102
all_pins[31]	4498331	1			T22	1		T23	69		T24	102

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	89407290	1			T22	32		T23	1108		T24	2731
values[0x1]	54539302	1			T23	1100		T24	533		T25	1482
transitions[0x0=>0x1]	32657643	1			T23	550		T24	361		T25	735
transitions[0x1=>0x0]	32657498	1			T23	549		T24	361		T25	734

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2797951	1			T22	1		T23	35		T24	89
all_pins[0]	values[0x1]	1700380	1			T23	34		T24	13		T25	57
all_pins[0]	transitions[0x0=>0x1]	1050886	1			T23	18		T24	11		T25	19
all_pins[0]	transitions[0x1=>0x0]	1060525	1			T23	17		T24	14		T25	18
all_pins[1]	values[0x0]	2791579	1			T22	1		T23	32		T24	95
all_pins[1]	values[0x1]	1706752	1			T23	37		T24	7		T25	45
all_pins[1]	transitions[0x0=>0x1]	1021119	1			T23	22		T24	6		T25	18
all_pins[1]	transitions[0x1=>0x0]	1014747	1			T23	19		T24	12		T25	30
all_pins[2]	values[0x0]	2791557	1			T22	1		T23	33		T24	86
all_pins[2]	values[0x1]	1706774	1			T23	36		T24	16		T25	43
all_pins[2]	transitions[0x0=>0x1]	1018888	1			T23	15		T24	15		T25	21
all_pins[2]	transitions[0x1=>0x0]	1018866	1			T23	16		T24	6		T25	23
all_pins[3]	values[0x0]	2795449	1			T22	1		T23	39		T24	86
all_pins[3]	values[0x1]	1702882	1			T23	30		T24	16		T25	50
all_pins[3]	transitions[0x0=>0x1]	1018284	1			T23	14		T24	8		T25	33
all_pins[3]	transitions[0x1=>0x0]	1022176	1			T23	20		T24	8		T25	26
all_pins[4]	values[0x0]	2791225	1			T22	1		T23	38		T24	88
all_pins[4]	values[0x1]	1707106	1			T23	31		T24	14		T25	53
all_pins[4]	transitions[0x0=>0x1]	1023132	1			T23	16		T24	14		T25	20
all_pins[4]	transitions[0x1=>0x0]	1018908	1			T23	15		T24	16		T25	17
all_pins[5]	values[0x0]	2794804	1			T22	1		T23	39		T24	85
all_pins[5]	values[0x1]	1703527	1			T23	30		T24	17		T25	42
all_pins[5]	transitions[0x0=>0x1]	1017433	1			T23	18		T24	9		T25	17
all_pins[5]	transitions[0x1=>0x0]	1021012	1			T23	19		T24	6		T25	28
all_pins[6]	values[0x0]	2799697	1			T22	1		T23	31		T24	78
all_pins[6]	values[0x1]	1698634	1			T23	38		T24	24		T25	38
all_pins[6]	transitions[0x0=>0x1]	1017373	1			T23	23		T24	11		T25	18
all_pins[6]	transitions[0x1=>0x0]	1022266	1			T23	15		T24	4		T25	22
all_pins[7]	values[0x0]	2792511	1			T22	1		T23	40		T24	83
all_pins[7]	values[0x1]	1705820	1			T23	29		T24	19		T25	47
all_pins[7]	transitions[0x0=>0x1]	1024614	1			T23	13		T24	12		T25	28
all_pins[7]	transitions[0x1=>0x0]	1017428	1			T23	22		T24	17		T25	19
all_pins[8]	values[0x0]	2797884	1			T22	1		T23	37		T24	87
all_pins[8]	values[0x1]	1700447	1			T23	32		T24	15		T25	38
all_pins[8]	transitions[0x0=>0x1]	1016037	1			T23	19		T24	9		T25	16
all_pins[8]	transitions[0x1=>0x0]	1021410	1			T23	16		T24	13		T25	25
all_pins[9]	values[0x0]	2793039	1			T22	1		T23	33		T24	71
all_pins[9]	values[0x1]	1705292	1			T23	36		T24	31		T25	49
all_pins[9]	transitions[0x0=>0x1]	1024056	1			T23	17		T24	23		T25	27
all_pins[9]	transitions[0x1=>0x0]	1019211	1			T23	13		T24	7		T25	16
all_pins[10]	values[0x0]	2791650	1			T22	1		T23	37		T24	80
all_pins[10]	values[0x1]	1706681	1			T23	32		T24	22		T25	51
all_pins[10]	transitions[0x0=>0x1]	1020554	1			T23	17		T24	6		T25	25
all_pins[10]	transitions[0x1=>0x0]	1019165	1			T23	21		T24	15		T25	23
all_pins[11]	values[0x0]	2797246	1			T22	1		T23	32		T24	89
all_pins[11]	values[0x1]	1701085	1			T23	37		T24	13		T25	56
all_pins[11]	transitions[0x0=>0x1]	1014855	1			T23	21		T24	7		T25	26
all_pins[11]	transitions[0x1=>0x0]	1020451	1			T23	16		T24	16		T25	21
all_pins[12]	values[0x0]	2799039	1			T22	1		T23	38		T24	79
all_pins[12]	values[0x1]	1699292	1			T23	31		T24	23		T25	59
all_pins[12]	transitions[0x0=>0x1]	1017402	1			T23	14		T24	15		T25	22
all_pins[12]	transitions[0x1=>0x0]	1019195	1			T23	20		T24	5		T25	19
all_pins[13]	values[0x0]	2796049	1			T22	1		T23	33		T24	94
all_pins[13]	values[0x1]	1702282	1			T23	36		T24	8		T25	38
all_pins[13]	transitions[0x0=>0x1]	1019237	1			T23	21		T24	5		T25	15
all_pins[13]	transitions[0x1=>0x0]	1016247	1			T23	16		T24	20		T25	36
all_pins[14]	values[0x0]	2791898	1			T22	1		T23	29		T24	94
all_pins[14]	values[0x1]	1706433	1			T23	40		T24	8		T25	41
all_pins[14]	transitions[0x0=>0x1]	1022729	1			T23	15		T24	6		T25	23
all_pins[14]	transitions[0x1=>0x0]	1018578	1			T23	11		T24	6		T25	20
all_pins[15]	values[0x0]	2791768	1			T22	1		T23	31		T24	87
all_pins[15]	values[0x1]	1706563	1			T23	38		T24	15		T25	42
all_pins[15]	transitions[0x0=>0x1]	1018128	1			T23	16		T24	13		T25	21
all_pins[15]	transitions[0x1=>0x0]	1017998	1			T23	18		T24	6		T25	20
all_pins[16]	values[0x0]	2794014	1			T22	1		T23	36		T24	87
all_pins[16]	values[0x1]	1704317	1			T23	33		T24	15		T25	44
all_pins[16]	transitions[0x0=>0x1]	1017480	1			T23	14		T24	13		T25	27
all_pins[16]	transitions[0x1=>0x0]	1019726	1			T23	19		T24	13		T25	25
all_pins[17]	values[0x0]	2794672	1			T22	1		T23	28		T24	78
all_pins[17]	values[0x1]	1703659	1			T23	41		T24	24		T25	45
all_pins[17]	transitions[0x0=>0x1]	1015334	1			T23	24		T24	19		T25	22
all_pins[17]	transitions[0x1=>0x0]	1015992	1			T23	16		T24	10		T25	21
all_pins[18]	values[0x0]	2790354	1			T22	1		T23	43		T24	94
all_pins[18]	values[0x1]	1707977	1			T23	26		T24	8		T25	38
all_pins[18]	transitions[0x0=>0x1]	1022997	1			T23	12		T24	2		T25	23
all_pins[18]	transitions[0x1=>0x0]	1018679	1			T23	27		T24	18		T25	30
all_pins[19]	values[0x0]	2792822	1			T22	1		T23	40		T24	83
all_pins[19]	values[0x1]	1705509	1			T23	29		T24	19		T25	57
all_pins[19]	transitions[0x0=>0x1]	1017411	1			T23	16		T24	16		T25	34
all_pins[19]	transitions[0x1=>0x0]	1019879	1			T23	13		T24	5		T25	15
all_pins[20]	values[0x0]	2790976	1			T22	1		T23	29		T24	93
all_pins[20]	values[0x1]	1707355	1			T23	40		T24	9		T25	40
all_pins[20]	transitions[0x0=>0x1]	1019446	1			T23	21		T24	9		T25	22
all_pins[20]	transitions[0x1=>0x0]	1017600	1			T23	10		T24	19		T25	39
all_pins[21]	values[0x0]	2791873	1			T22	1		T23	35		T24	82
all_pins[21]	values[0x1]	1706458	1			T23	34		T24	20		T25	48
all_pins[21]	transitions[0x0=>0x1]	1019664	1			T23	15		T24	19		T25	28
all_pins[21]	transitions[0x1=>0x0]	1020561	1			T23	21		T24	8		T25	20
all_pins[22]	values[0x0]	2797494	1			T22	1		T23	31		T24	90
all_pins[22]	values[0x1]	1700837	1			T23	38		T24	12		T25	36
all_pins[22]	transitions[0x0=>0x1]	1015448	1			T23	17		T24	8		T25	17
all_pins[22]	transitions[0x1=>0x0]	1021069	1			T23	13		T24	16		T25	29
all_pins[23]	values[0x0]	2790947	1			T22	1		T23	36		T24	79
all_pins[23]	values[0x1]	1707384	1			T23	33		T24	23		T25	38
all_pins[23]	transitions[0x0=>0x1]	1024314	1			T23	10		T24	14		T25	23
all_pins[23]	transitions[0x1=>0x0]	1017767	1			T23	15		T24	3		T25	21
all_pins[24]	values[0x0]	2794845	1			T22	1		T23	40		T24	88
all_pins[24]	values[0x1]	1703486	1			T23	29		T24	14		T25	47
all_pins[24]	transitions[0x0=>0x1]	1016769	1			T23	16		T24	10		T25	25
all_pins[24]	transitions[0x1=>0x0]	1020667	1			T23	20		T24	19		T25	16
all_pins[25]	values[0x0]	2792679	1			T22	1		T23	36		T24	87
all_pins[25]	values[0x1]	1705652	1			T23	33		T24	15		T25	46
all_pins[25]	transitions[0x0=>0x1]	1018525	1			T23	18		T24	7		T25	24
all_pins[25]	transitions[0x1=>0x0]	1016359	1			T23	14		T24	6		T25	25
all_pins[26]	values[0x0]	2796584	1			T22	1		T23	29		T24	88
all_pins[26]	values[0x1]	1701747	1			T23	40		T24	14		T25	49
all_pins[26]	transitions[0x0=>0x1]	1017930	1			T23	25		T24	9		T25	25
all_pins[26]	transitions[0x1=>0x0]	1021835	1			T23	18		T24	10		T25	22
all_pins[27]	values[0x0]	2797047	1			T22	1		T23	28		T24	87
all_pins[27]	values[0x1]	1701284	1			T23	41		T24	15		T25	48
all_pins[27]	transitions[0x0=>0x1]	1021385	1			T23	18		T24	14		T25	24
all_pins[27]	transitions[0x1=>0x0]	1021848	1			T23	17		T24	13		T25	25
all_pins[28]	values[0x0]	2795448	1			T22	1		T23	43		T24	79
all_pins[28]	values[0x1]	1702883	1			T23	26		T24	23		T25	43
all_pins[28]	transitions[0x0=>0x1]	1020786	1			T23	7		T24	15		T25	16
all_pins[28]	transitions[0x1=>0x0]	1019187	1			T23	22		T24	7		T25	21
all_pins[29]	values[0x0]	2795539	1			T22	1		T23	27		T24	76
all_pins[29]	values[0x1]	1702792	1			T23	42		T24	26		T25	55
all_pins[29]	transitions[0x0=>0x1]	1019757	1			T23	29		T24	13		T25	26
all_pins[29]	transitions[0x1=>0x0]	1019848	1			T23	13		T24	10		T25	14
all_pins[30]	values[0x0]	2790483	1			T22	1		T23	35		T24	83
all_pins[30]	values[0x1]	1707848	1			T23	34		T24	19		T25	42
all_pins[30]	transitions[0x0=>0x1]	1023626	1			T23	12		T24	16		T25	20
all_pins[30]	transitions[0x1=>0x0]	1018570	1			T23	20		T24	23		T25	33
all_pins[31]	values[0x0]	2788167	1			T22	1		T23	35		T24	86
all_pins[31]	values[0x1]	1710164	1			T23	34		T24	16		T25	57
all_pins[31]	transitions[0x0=>0x1]	1022044	1			T23	17		T24	7		T25	30
all_pins[31]	transitions[0x1=>0x0]	1019728	1			T23	17		T24	10		T25	15