Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[1]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[2]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[3]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[4]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[5]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[6]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[7]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[8]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[9]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[10]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[11]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[12]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[13]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[14]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[15]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[16]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[17]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[18]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[19]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[20]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[21]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[22]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[23]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[24]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[25]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[26]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[27]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[28]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[29]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[30]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[31]	14750705	1			T22	687		T23	32439		T24	211

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

280273657

1

T22

4700

T23

525951

T24

3542

auto[1]

191748903

1

T22

17284

T23

512097

T24

3210

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

378540888

1

T22

16757

T23

103804

T24

6250

auto[1]

93481672

1

T22

5227

T24

502

T1

100866

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351733506

1

T22

11424

T23

103804

T24

5058

auto[1]

120289054

1

T22

10560

T24

1694

T1

125862

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5449958	1			T22	29		T23	16115		T24	91
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4070425	1			T22	286		T23	16324		T24	68
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1468573	1			T22	88		T1	16117		T12	126
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1831641	1			T22	17		T24	31		T1	22420
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	472950	1			T22	188		T24	8		T1	1482
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1457158	1			T22	79		T24	13		T1	15530
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5459572	1			T22	31		T23	15882		T24	91
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4069110	1			T22	193		T23	16557		T24	41
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1473248	1			T22	85		T24	5		T1	16004
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1819583	1			T22	32		T24	35		T1	22560
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	473559	1			T22	279		T24	19		T1	1372
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1455633	1			T22	67		T24	20		T1	15336
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5456078	1			T22	61		T23	15698		T24	92
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4067109	1			T22	297		T23	16741		T24	48
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1469152	1			T22	66		T24	10		T1	16899
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1823780	1			T22	13		T24	42		T1	21462
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	473665	1			T22	181		T24	11		T1	1477
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1460921	1			T22	69		T24	8		T1	15643
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5451460	1			T22	18		T23	15926		T24	85
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4069660	1			T22	186		T23	16513		T24	82
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1471770	1			T22	88		T1	16218		T12	72
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1822087	1			T22	41		T24	17		T1	21647
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	474477	1			T22	263		T24	19		T1	1377
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1461251	1			T22	91		T24	8		T1	15612
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5452129	1			T22	29		T23	14530		T24	81
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4069625	1			T22	178		T23	17909		T24	59
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1470967	1			T22	48		T1	16131		T12	78
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1829262	1			T22	35		T24	58		T1	21881
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	470955	1			T22	302		T24	11		T1	1319
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1457767	1			T22	95		T24	2		T1	15705
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5463130	1			T22	40		T23	17647		T24	75
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4055959	1			T22	255		T23	14792		T24	75
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1468492	1			T22	120		T24	5		T1	15890
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1831712	1			T22	21		T24	35		T1	22216
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	473798	1			T22	162		T24	16		T1	1403
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1457614	1			T22	89		T24	5		T1	16054
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5451669	1			T22	38		T23	17379		T24	74
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4063600	1			T22	298		T23	15060		T24	49
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1472497	1			T22	74		T24	5		T1	15933
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1829549	1			T22	19		T24	48		T1	22605
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	474959	1			T22	202		T24	22		T1	1437
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1458431	1			T22	56		T24	13		T1	15789
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5468260	1			T22	25		T23	16524		T24	49
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4059496	1			T22	227		T23	15915		T24	82
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1469099	1			T22	97		T24	6		T1	15889
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1827355	1			T22	37		T24	33		T1	22019
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	475459	1			T22	243		T24	29		T1	1397
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1451036	1			T22	58		T24	12		T1	15471
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5459671	1			T22	42		T23	16477		T24	119
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4059585	1			T22	206		T23	15962		T24	44
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1467964	1			T22	67		T24	4		T1	15639
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1836226	1			T22	23		T24	27		T1	22699
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	474469	1			T22	223		T24	9		T1	1398
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1452790	1			T22	126		T24	8		T1	15170
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5464718	1			T22	50		T23	15987		T24	107
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4064283	1			T22	310		T23	16452		T24	44
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1469508	1			T22	96		T24	5		T1	16175
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1823433	1			T22	11		T24	23		T1	21789
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	472715	1			T22	177		T24	20		T1	1330
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1456048	1			T22	43		T24	12		T1	15719
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5471925	1			T22	42		T23	16981		T24	107
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4056234	1			T22	255		T23	15458		T24	58
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1467169	1			T22	113		T24	6		T1	15423
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1828250	1			T22	23		T24	26		T1	21890
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	471763	1			T22	181		T24	8		T1	1299
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1455364	1			T22	73		T24	6		T1	15932
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5462494	1			T22	31		T23	16866		T24	21
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4056902	1			T22	274		T23	15573		T24	110
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1471271	1			T22	61		T24	2		T1	15912
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1826994	1			T22	17		T24	28		T1	21684
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	475180	1			T22	214		T24	24		T1	1358
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1457864	1			T22	90		T24	26		T1	15933
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5461969	1			T22	33		T23	17179		T24	49
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4054390	1			T22	260		T23	15260		T24	78
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1471572	1			T22	78		T24	11		T1	16013
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1831203	1			T22	35		T24	16		T1	22151
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	472884	1			T22	220		T24	23		T1	1412
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1458687	1			T22	61		T24	34		T1	15788
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5454514	1			T22	38		T23	16627		T24	114
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4060702	1			T22	340		T23	15812		T24	26
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1466508	1			T22	60		T24	2		T1	16312
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1834050	1			T22	15		T24	29		T1	22217
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	473364	1			T22	160		T24	19		T1	1333
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1461567	1			T22	74		T24	21		T1	15005
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5460670	1			T22	40		T23	14892		T24	83
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4060971	1			T22	206		T23	17547		T24	56
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1469465	1			T22	109		T24	7		T1	15189
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1828272	1			T22	30		T24	52		T1	22662
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	473331	1			T22	222		T24	8		T1	1338
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1457996	1			T22	80		T24	5		T1	15715
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5456099	1			T22	41		T23	15576		T24	89
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4063055	1			T22	234		T23	16863		T24	55
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1469816	1			T22	80		T24	9		T1	15798
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1830723	1			T22	21		T24	45		T1	22679
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	476074	1			T22	212		T24	9		T1	1442
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1454938	1			T22	99		T24	4		T1	16141
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5458482	1			T22	24		T23	16255		T24	76
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4067453	1			T22	238		T23	16184		T24	98
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1462353	1			T22	102		T24	4		T1	15355
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1833095	1			T22	40		T24	12		T1	22825
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	475699	1			T22	219		T24	15		T1	1356
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1453623	1			T22	64		T24	6		T1	15769
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5473082	1			T22	41		T23	16279		T24	78
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4062354	1			T22	233		T23	16160		T24	74
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1464797	1			T22	54		T24	8		T1	15512
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1832515	1			T22	21		T24	20		T1	22712
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	472357	1			T22	242		T24	13		T1	1406
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1445600	1			T22	96		T24	18		T1	15871
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5452802	1			T22	37		T23	16368		T24	69
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4069982	1			T22	269		T23	16071		T24	96
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1465687	1			T22	94		T24	3		T1	15382
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1832892	1			T22	33		T24	16		T1	22477
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	472544	1			T22	168		T24	15		T1	1298
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1456798	1			T22	86		T24	12		T1	16156
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5450477	1			T22	41		T23	16238		T24	71
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4077591	1			T22	298		T23	16201		T24	84
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1464018	1			T22	132		T24	1		T1	15373
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1832279	1			T22	17		T24	30		T1	22231
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	473709	1			T22	135		T24	16		T1	1398
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1452631	1			T22	64		T24	9		T1	15895
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5462588	1			T22	26		T23	17622		T24	96
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4063042	1			T22	177		T23	14817		T24	75
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1464059	1			T22	93		T24	2		T1	15516
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1831383	1			T22	38		T24	20		T1	22646
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	475502	1			T22	260		T24	13		T1	1329
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1454131	1			T22	93		T24	5		T1	15946
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5469558	1			T22	15		T23	16280		T24	93
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4059997	1			T22	135		T23	16159		T24	67
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1464348	1			T22	40		T24	17		T1	15810
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1830703	1			T22	40		T24	24		T1	21800
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	475585	1			T22	365		T24	8		T1	1388
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1450514	1			T22	92		T24	2		T1	15865
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5471050	1			T22	28		T23	15713		T24	72
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4060911	1			T22	228		T23	16726		T24	85
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1462977	1			T22	92		T24	8		T1	15583
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1830604	1			T22	28		T24	23		T1	22370
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	472319	1			T22	226		T24	17		T1	1303
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1452844	1			T22	85		T24	6		T1	15181
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5465801	1			T22	36		T23	17106		T24	82
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4058684	1			T22	193		T23	15333		T24	96
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1461887	1			T22	66		T24	7		T1	15977
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1835007	1			T22	44		T24	13		T1	22282
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	475588	1			T22	224		T24	11		T1	1340
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1453738	1			T22	124		T24	2		T1	15580
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5466919	1			T22	29		T23	17651		T24	70
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4062888	1			T22	236		T23	14788		T24	89
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1458909	1			T22	103		T24	10		T1	15537
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1833332	1			T22	47		T24	8		T1	22414
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	477416	1			T22	195		T24	24		T1	1339
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1451241	1			T22	77		T24	10		T1	15011
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5463396	1			T22	37		T23	16167		T24	83
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4065192	1			T22	242		T23	16272		T24	83
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1463336	1			T22	87		T24	2		T1	16050
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1832554	1			T22	29		T24	24		T1	22171
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	473177	1			T22	219		T24	12		T1	1327
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1453050	1			T22	73		T24	7		T1	15832
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5455760	1			T22	37		T23	16606		T24	63
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4066916	1			T22	257		T23	15833		T24	99
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1468739	1			T22	70		T24	7		T1	15756
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1827025	1			T22	27		T24	12		T1	22412
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	477287	1			T22	218		T24	25		T1	1365
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1454978	1			T22	78		T24	5		T1	15648
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5463648	1			T22	52		T23	15833		T24	62
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4063343	1			T22	291		T23	16606		T24	72
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1465345	1			T22	106		T24	5		T1	16129
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1833666	1			T22	20		T24	20		T1	22134
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	472764	1			T22	164		T24	32		T1	1470
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1451939	1			T22	54		T24	20		T1	15756
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5464238	1			T22	26		T23	16359		T24	78
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4060574	1			T22	172		T23	16080		T24	79
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1461700	1			T22	47		T24	5		T1	15283
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1837292	1			T22	36		T24	29		T1	22090
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	476580	1			T22	323		T24	16		T1	1404
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1450321	1			T22	83		T24	4		T1	15772
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5453314	1			T22	28		T23	17399		T24	75
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4067416	1			T22	222		T23	15040		T24	83
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1467758	1			T22	102		T24	4		T1	15975
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1834502	1			T22	39		T24	14		T1	22015
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	475187	1			T22	233		T24	14		T1	1386
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1452528	1			T22	63		T24	21		T1	15874
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5472533	1			T22	25		T23	17468		T24	45
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4067123	1			T22	201		T23	14971		T24	138
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1462375	1			T22	66		T24	2		T1	15692
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1832186	1			T22	33		T24	13		T1	22138
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	472483	1			T22	274		T24	10		T1	1320
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1444005	1			T22	88		T24	3		T1	15978
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5473064	1			T22	29		T23	16321		T24	86
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4057414	1			T22	250		T23	16118		T24	71
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1465133	1			T22	94		T24	6		T1	15485
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1828982	1			T22	41		T24	25		T1	22595
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	477938	1			T22	194		T24	16		T1	1417
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1448174	1			T22	79		T24	7		T1	16032

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal