Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[1]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[2]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[3]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[4]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[5]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[6]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[7]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[8]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[9]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[10]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[11]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[12]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[13]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[14]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[15]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[16]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[17]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[18]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[19]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[20]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[21]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[22]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[23]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[24]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[25]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[26]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[27]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[28]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[29]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[30]	14750705	1			T22	687		T23	32439		T24	211
bins_for_gpio_bits[31]	14750705	1			T22	687		T23	32439		T24	211

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

280273657

1

T22

4700

T23

525951

T24

3542

auto[1]

191748903

1

T22

17284

T23

512097

T24

3210

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

280265885

1

T22

4708

T23

525951

T24

3543

auto[1]

191756675

1

T22

17276

T23

512097

T24

3209

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8489877	1			T22	120		T23	16115		T24	122
bins_for_gpio_bits[0]	auto[0]	auto[1]	260030	1			T22	15		T24	1		T1	2657
bins_for_gpio_bits[0]	auto[1]	auto[0]	260295	1			T22	14		T1	2657		T12	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	5740503	1			T22	538		T23	16324		T24	88
bins_for_gpio_bits[1]	auto[0]	auto[0]	8492474	1			T22	132		T23	15882		T24	130
bins_for_gpio_bits[1]	auto[0]	auto[1]	259658	1			T22	16		T24	1		T1	2670
bins_for_gpio_bits[1]	auto[1]	auto[0]	259929	1			T22	16		T24	1		T1	2670
bins_for_gpio_bits[1]	auto[1]	auto[1]	5738644	1			T22	523		T23	16557		T24	79
bins_for_gpio_bits[2]	auto[0]	auto[0]	8488387	1			T22	122		T23	15698		T24	144
bins_for_gpio_bits[2]	auto[0]	auto[1]	260405	1			T22	19		T1	2706		T12	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	260623	1			T22	18		T1	2706		T12	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	5741290	1			T22	528		T23	16741		T24	67
bins_for_gpio_bits[3]	auto[0]	auto[0]	8485202	1			T22	134		T23	15926		T24	102
bins_for_gpio_bits[3]	auto[0]	auto[1]	259823	1			T22	13		T1	2661		T12	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	260115	1			T22	13		T1	2661		T12	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	5745565	1			T22	527		T23	16513		T24	109
bins_for_gpio_bits[4]	auto[0]	auto[0]	8491962	1			T22	104		T23	14530		T24	139
bins_for_gpio_bits[4]	auto[0]	auto[1]	260193	1			T22	9		T1	2728		T12	19
bins_for_gpio_bits[4]	auto[1]	auto[0]	260396	1			T22	8		T1	2728		T12	19
bins_for_gpio_bits[4]	auto[1]	auto[1]	5738154	1			T22	566		T23	17909		T24	72
bins_for_gpio_bits[5]	auto[0]	auto[0]	8502986	1			T22	165		T23	17647		T24	115
bins_for_gpio_bits[5]	auto[0]	auto[1]	260130	1			T22	16		T1	2731		T12	18
bins_for_gpio_bits[5]	auto[1]	auto[0]	260348	1			T22	16		T1	2731		T12	18
bins_for_gpio_bits[5]	auto[1]	auto[1]	5727241	1			T22	490		T23	14792		T24	96
bins_for_gpio_bits[6]	auto[0]	auto[0]	8493826	1			T22	117		T23	17379		T24	127
bins_for_gpio_bits[6]	auto[0]	auto[1]	259635	1			T22	14		T1	2711		T12	22
bins_for_gpio_bits[6]	auto[1]	auto[0]	259889	1			T22	14		T1	2711		T12	22
bins_for_gpio_bits[6]	auto[1]	auto[1]	5737355	1			T22	542		T23	15060		T24	84
bins_for_gpio_bits[7]	auto[0]	auto[0]	8504840	1			T22	146		T23	16524		T24	87
bins_for_gpio_bits[7]	auto[0]	auto[1]	259581	1			T22	13		T1	2656		T12	18
bins_for_gpio_bits[7]	auto[1]	auto[0]	259874	1			T22	13		T24	1		T1	2656
bins_for_gpio_bits[7]	auto[1]	auto[1]	5726410	1			T22	515		T23	15915		T24	123
bins_for_gpio_bits[8]	auto[0]	auto[0]	8503502	1			T22	120		T23	16477		T24	150
bins_for_gpio_bits[8]	auto[0]	auto[1]	260116	1			T22	12		T1	2667		T12	16
bins_for_gpio_bits[8]	auto[1]	auto[0]	260359	1			T22	12		T1	2668		T12	16
bins_for_gpio_bits[8]	auto[1]	auto[1]	5726728	1			T22	543		T23	15962		T24	61
bins_for_gpio_bits[9]	auto[0]	auto[0]	8497515	1			T22	140		T23	15987		T24	135
bins_for_gpio_bits[9]	auto[0]	auto[1]	259907	1			T22	17		T1	2722		T12	18
bins_for_gpio_bits[9]	auto[1]	auto[0]	260144	1			T22	17		T1	2723		T12	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	5733139	1			T22	513		T23	16452		T24	76
bins_for_gpio_bits[10]	auto[0]	auto[0]	8507978	1			T22	160		T23	16981		T24	139
bins_for_gpio_bits[10]	auto[0]	auto[1]	259091	1			T22	18		T1	2638		T12	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	259366	1			T22	18		T1	2638		T12	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	5724270	1			T22	491		T23	15458		T24	72
bins_for_gpio_bits[11]	auto[0]	auto[0]	8500971	1			T22	94		T23	16866		T24	51
bins_for_gpio_bits[11]	auto[0]	auto[1]	259532	1			T22	15		T24	1		T1	2679
bins_for_gpio_bits[11]	auto[1]	auto[0]	259788	1			T22	15		T1	2680		T12	20
bins_for_gpio_bits[11]	auto[1]	auto[1]	5730414	1			T22	563		T23	15573		T24	159
bins_for_gpio_bits[12]	auto[0]	auto[0]	8504914	1			T22	134		T23	17179		T24	76
bins_for_gpio_bits[12]	auto[0]	auto[1]	259590	1			T22	12		T24	1		T1	2702
bins_for_gpio_bits[12]	auto[1]	auto[0]	259830	1			T22	12		T1	2702		T12	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	5726371	1			T22	529		T23	15260		T24	134
bins_for_gpio_bits[13]	auto[0]	auto[0]	8494346	1			T22	102		T23	16627		T24	144
bins_for_gpio_bits[13]	auto[0]	auto[1]	260490	1			T22	11		T1	2700		T12	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	260726	1			T22	11		T24	1		T1	2701
bins_for_gpio_bits[13]	auto[1]	auto[1]	5735143	1			T22	563		T23	15812		T24	66
bins_for_gpio_bits[14]	auto[0]	auto[0]	8498295	1			T22	158		T23	14892		T24	142
bins_for_gpio_bits[14]	auto[0]	auto[1]	259876	1			T22	21		T1	2684		T12	12
bins_for_gpio_bits[14]	auto[1]	auto[0]	260112	1			T22	21		T1	2684		T12	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	5732422	1			T22	487		T23	17547		T24	69
bins_for_gpio_bits[15]	auto[0]	auto[0]	8496103	1			T22	128		T23	15576		T24	143
bins_for_gpio_bits[15]	auto[0]	auto[1]	260334	1			T22	15		T1	2729		T12	22
bins_for_gpio_bits[15]	auto[1]	auto[0]	260535	1			T22	14		T1	2730		T12	22
bins_for_gpio_bits[15]	auto[1]	auto[1]	5733733	1			T22	530		T23	16863		T24	68
bins_for_gpio_bits[16]	auto[0]	auto[0]	8493504	1			T22	152		T23	16255		T24	92
bins_for_gpio_bits[16]	auto[0]	auto[1]	260171	1			T22	14		T1	2716		T12	19
bins_for_gpio_bits[16]	auto[1]	auto[0]	260426	1			T22	14		T1	2717		T12	19
bins_for_gpio_bits[16]	auto[1]	auto[1]	5736604	1			T22	507		T23	16184		T24	119
bins_for_gpio_bits[17]	auto[0]	auto[0]	8510348	1			T22	105		T23	16279		T24	106
bins_for_gpio_bits[17]	auto[0]	auto[1]	259771	1			T22	11		T1	2717		T12	20
bins_for_gpio_bits[17]	auto[1]	auto[0]	260046	1			T22	11		T1	2717		T12	20
bins_for_gpio_bits[17]	auto[1]	auto[1]	5720540	1			T22	560		T23	16160		T24	105
bins_for_gpio_bits[18]	auto[0]	auto[0]	8490641	1			T22	146		T23	16368		T24	88
bins_for_gpio_bits[18]	auto[0]	auto[1]	260480	1			T22	18		T1	2748		T12	29
bins_for_gpio_bits[18]	auto[1]	auto[0]	260740	1			T22	18		T1	2749		T12	29
bins_for_gpio_bits[18]	auto[1]	auto[1]	5738844	1			T22	505		T23	16071		T24	123
bins_for_gpio_bits[19]	auto[0]	auto[0]	8486335	1			T22	169		T23	16238		T24	102
bins_for_gpio_bits[19]	auto[0]	auto[1]	260210	1			T22	21		T1	2691		T12	17
bins_for_gpio_bits[19]	auto[1]	auto[0]	260439	1			T22	21		T1	2692		T12	17
bins_for_gpio_bits[19]	auto[1]	auto[1]	5743721	1			T22	476		T23	16201		T24	109
bins_for_gpio_bits[20]	auto[0]	auto[0]	8497657	1			T22	143		T23	17622		T24	118
bins_for_gpio_bits[20]	auto[0]	auto[1]	260170	1			T22	15		T1	2741		T12	13
bins_for_gpio_bits[20]	auto[1]	auto[0]	260373	1			T22	14		T1	2741		T12	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	5732505	1			T22	515		T23	14817		T24	93
bins_for_gpio_bits[21]	auto[0]	auto[0]	8504739	1			T22	86		T23	16280		T24	134
bins_for_gpio_bits[21]	auto[0]	auto[1]	259661	1			T22	10		T1	2760		T12	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	259870	1			T22	9		T1	2760		T12	16
bins_for_gpio_bits[21]	auto[1]	auto[1]	5726435	1			T22	582		T23	16159		T24	77
bins_for_gpio_bits[22]	auto[0]	auto[0]	8504031	1			T22	130		T23	15713		T24	103
bins_for_gpio_bits[22]	auto[0]	auto[1]	260347	1			T22	19		T1	2690		T12	18
bins_for_gpio_bits[22]	auto[1]	auto[0]	260600	1			T22	18		T1	2690		T12	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	5725727	1			T22	520		T23	16726		T24	108
bins_for_gpio_bits[23]	auto[0]	auto[0]	8501747	1			T22	130		T23	17106		T24	102
bins_for_gpio_bits[23]	auto[0]	auto[1]	260750	1			T22	16		T1	2716		T12	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	260948	1			T22	16		T1	2716		T12	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	5727260	1			T22	525		T23	15333		T24	109
bins_for_gpio_bits[24]	auto[0]	auto[0]	8499310	1			T22	164		T23	17651		T24	88
bins_for_gpio_bits[24]	auto[0]	auto[1]	259579	1			T22	15		T1	2651		T12	20
bins_for_gpio_bits[24]	auto[1]	auto[0]	259850	1			T22	15		T1	2651		T12	20
bins_for_gpio_bits[24]	auto[1]	auto[1]	5731966	1			T22	493		T23	14788		T24	123
bins_for_gpio_bits[25]	auto[0]	auto[0]	8499559	1			T22	137		T23	16167		T24	109
bins_for_gpio_bits[25]	auto[0]	auto[1]	259492	1			T22	16		T1	2708		T12	20
bins_for_gpio_bits[25]	auto[1]	auto[0]	259727	1			T22	16		T1	2710		T12	20
bins_for_gpio_bits[25]	auto[1]	auto[1]	5731927	1			T22	518		T23	16272		T24	102
bins_for_gpio_bits[26]	auto[0]	auto[0]	8491169	1			T22	120		T23	16606		T24	82
bins_for_gpio_bits[26]	auto[0]	auto[1]	260115	1			T22	14		T1	2654		T12	18
bins_for_gpio_bits[26]	auto[1]	auto[0]	260355	1			T22	14		T1	2655		T12	18
bins_for_gpio_bits[26]	auto[1]	auto[1]	5739066	1			T22	539		T23	15833		T24	129
bins_for_gpio_bits[27]	auto[0]	auto[0]	8502738	1			T22	159		T23	15833		T24	87
bins_for_gpio_bits[27]	auto[0]	auto[1]	259654	1			T22	19		T1	2740		T12	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	259921	1			T22	19		T1	2740		T12	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	5728392	1			T22	490		T23	16606		T24	124
bins_for_gpio_bits[28]	auto[0]	auto[0]	8503328	1			T22	97		T23	16359		T24	112
bins_for_gpio_bits[28]	auto[0]	auto[1]	259676	1			T22	12		T1	2704		T12	18
bins_for_gpio_bits[28]	auto[1]	auto[0]	259902	1			T22	12		T1	2704		T12	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	5727799	1			T22	566		T23	16080		T24	99
bins_for_gpio_bits[29]	auto[0]	auto[0]	8495572	1			T22	154		T23	17399		T24	93
bins_for_gpio_bits[29]	auto[0]	auto[1]	259800	1			T22	15		T1	2695		T12	15
bins_for_gpio_bits[29]	auto[1]	auto[0]	260002	1			T22	15		T1	2695		T12	15
bins_for_gpio_bits[29]	auto[1]	auto[1]	5735331	1			T22	503		T23	15040		T24	118
bins_for_gpio_bits[30]	auto[0]	auto[0]	8507427	1			T22	111		T23	17468		T24	60
bins_for_gpio_bits[30]	auto[0]	auto[1]	259390	1			T22	13		T1	2737		T12	12
bins_for_gpio_bits[30]	auto[1]	auto[0]	259667	1			T22	13		T1	2737		T12	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	5724221	1			T22	550		T23	14971		T24	151
bins_for_gpio_bits[31]	auto[0]	auto[0]	8507361	1			T22	148		T23	16321		T24	117
bins_for_gpio_bits[31]	auto[0]	auto[1]	259584	1			T22	17		T1	2721		T12	27
bins_for_gpio_bits[31]	auto[1]	auto[0]	259818	1			T22	16		T1	2721		T12	27
bins_for_gpio_bits[31]	auto[1]	auto[1]	5723942	1			T22	506		T23	16118		T24	94