Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8693257 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
103 |
| auto[1] |
6339103 |
1 |
|
|
T24 |
53 |
|
T1 |
63794 |
|
T14 |
29822 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14226397 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
805963 |
1 |
|
|
T1 |
8430 |
|
T14 |
3949 |
|
T19 |
143 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8693043 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
103 |
| auto[1] |
6339317 |
1 |
|
|
T24 |
53 |
|
T1 |
68044 |
|
T14 |
28928 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2768340 |
1 |
|
|
T24 |
31 |
|
T1 |
32512 |
|
T14 |
11894 |
| auto[1] |
auto[0] |
auto[1] |
404433 |
1 |
|
|
T1 |
4599 |
|
T14 |
1827 |
|
T19 |
71 |
| auto[1] |
auto[1] |
auto[0] |
2765014 |
1 |
|
|
T24 |
22 |
|
T1 |
27102 |
|
T14 |
13085 |
| auto[1] |
auto[1] |
auto[1] |
401530 |
1 |
|
|
T1 |
3831 |
|
T14 |
2122 |
|
T19 |
72 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8703594 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
114 |
| auto[1] |
6328766 |
1 |
|
|
T24 |
42 |
|
T1 |
66807 |
|
T14 |
29392 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14225925 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
806435 |
1 |
|
|
T1 |
8127 |
|
T14 |
3648 |
|
T19 |
148 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8691254 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
100 |
| auto[1] |
6341106 |
1 |
|
|
T24 |
56 |
|
T1 |
65370 |
|
T14 |
27209 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2783908 |
1 |
|
|
T24 |
38 |
|
T1 |
28619 |
|
T14 |
11512 |
| auto[1] |
auto[0] |
auto[1] |
405342 |
1 |
|
|
T1 |
4097 |
|
T14 |
1800 |
|
T19 |
56 |
| auto[1] |
auto[1] |
auto[0] |
2750763 |
1 |
|
|
T24 |
18 |
|
T1 |
28624 |
|
T14 |
12049 |
| auto[1] |
auto[1] |
auto[1] |
401093 |
1 |
|
|
T1 |
4030 |
|
T14 |
1848 |
|
T19 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8699897 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
112 |
| auto[1] |
6332463 |
1 |
|
|
T24 |
44 |
|
T1 |
64449 |
|
T14 |
26677 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14226937 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
805423 |
1 |
|
|
T1 |
8131 |
|
T14 |
4108 |
|
T19 |
144 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8696099 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
84 |
| auto[1] |
6336261 |
1 |
|
|
T24 |
72 |
|
T1 |
65976 |
|
T14 |
29851 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2767255 |
1 |
|
|
T24 |
54 |
|
T1 |
29935 |
|
T14 |
13934 |
| auto[1] |
auto[0] |
auto[1] |
403354 |
1 |
|
|
T1 |
4305 |
|
T14 |
2287 |
|
T19 |
62 |
| auto[1] |
auto[1] |
auto[0] |
2763583 |
1 |
|
|
T24 |
18 |
|
T1 |
27910 |
|
T14 |
11809 |
| auto[1] |
auto[1] |
auto[1] |
402069 |
1 |
|
|
T1 |
3826 |
|
T14 |
1821 |
|
T19 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8698311 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
107 |
| auto[1] |
6334049 |
1 |
|
|
T24 |
49 |
|
T1 |
65797 |
|
T14 |
29795 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14224662 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
807698 |
1 |
|
|
T1 |
8611 |
|
T14 |
3933 |
|
T19 |
177 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8684086 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
105 |
| auto[1] |
6348274 |
1 |
|
|
T24 |
51 |
|
T1 |
68862 |
|
T14 |
29363 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2780668 |
1 |
|
|
T24 |
32 |
|
T1 |
31283 |
|
T14 |
12630 |
| auto[1] |
auto[0] |
auto[1] |
405469 |
1 |
|
|
T1 |
4644 |
|
T14 |
1945 |
|
T19 |
86 |
| auto[1] |
auto[1] |
auto[0] |
2759908 |
1 |
|
|
T24 |
19 |
|
T1 |
28968 |
|
T14 |
12800 |
| auto[1] |
auto[1] |
auto[1] |
402229 |
1 |
|
|
T1 |
3967 |
|
T14 |
1988 |
|
T19 |
91 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8719214 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
109 |
| auto[1] |
6313146 |
1 |
|
|
T24 |
47 |
|
T1 |
69668 |
|
T14 |
29638 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14221885 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
154 |
| auto[1] |
810475 |
1 |
|
|
T24 |
2 |
|
T1 |
8157 |
|
T14 |
4057 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8660933 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
115 |
| auto[1] |
6371427 |
1 |
|
|
T24 |
41 |
|
T1 |
65923 |
|
T14 |
29394 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2792755 |
1 |
|
|
T24 |
29 |
|
T1 |
28270 |
|
T14 |
12417 |
| auto[1] |
auto[0] |
auto[1] |
407266 |
1 |
|
|
T24 |
1 |
|
T1 |
3881 |
|
T14 |
1949 |
| auto[1] |
auto[1] |
auto[0] |
2768197 |
1 |
|
|
T24 |
10 |
|
T1 |
29496 |
|
T14 |
12920 |
| auto[1] |
auto[1] |
auto[1] |
403209 |
1 |
|
|
T24 |
1 |
|
T1 |
4276 |
|
T14 |
2108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8687704 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
102 |
| auto[1] |
6344656 |
1 |
|
|
T24 |
54 |
|
T1 |
67978 |
|
T14 |
26591 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14219380 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
812980 |
1 |
|
|
T24 |
1 |
|
T1 |
8255 |
|
T14 |
3835 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8660310 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
84 |
| auto[1] |
6372050 |
1 |
|
|
T24 |
72 |
|
T1 |
67188 |
|
T14 |
28436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2788194 |
1 |
|
|
T24 |
38 |
|
T1 |
28584 |
|
T14 |
12803 |
| auto[1] |
auto[0] |
auto[1] |
407194 |
1 |
|
|
T24 |
1 |
|
T1 |
4039 |
|
T14 |
1959 |
| auto[1] |
auto[1] |
auto[0] |
2770876 |
1 |
|
|
T24 |
33 |
|
T1 |
30349 |
|
T14 |
11798 |
| auto[1] |
auto[1] |
auto[1] |
405786 |
1 |
|
|
T1 |
4216 |
|
T14 |
1876 |
|
T19 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683374 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
135 |
| auto[1] |
6348986 |
1 |
|
|
T24 |
21 |
|
T1 |
69889 |
|
T14 |
28444 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14227692 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
804668 |
1 |
|
|
T1 |
8361 |
|
T14 |
3845 |
|
T19 |
143 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8701101 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
125 |
| auto[1] |
6331259 |
1 |
|
|
T24 |
31 |
|
T1 |
68365 |
|
T14 |
28808 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2752876 |
1 |
|
|
T24 |
26 |
|
T1 |
28336 |
|
T14 |
12693 |
| auto[1] |
auto[0] |
auto[1] |
400223 |
1 |
|
|
T1 |
3830 |
|
T14 |
1956 |
|
T19 |
43 |
| auto[1] |
auto[1] |
auto[0] |
2773715 |
1 |
|
|
T24 |
5 |
|
T1 |
31668 |
|
T14 |
12270 |
| auto[1] |
auto[1] |
auto[1] |
404445 |
1 |
|
|
T1 |
4531 |
|
T14 |
1889 |
|
T19 |
100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8715639 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
98 |
| auto[1] |
6316721 |
1 |
|
|
T24 |
58 |
|
T1 |
70223 |
|
T14 |
29749 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14225934 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
806426 |
1 |
|
|
T24 |
1 |
|
T1 |
7804 |
|
T14 |
3634 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8691878 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
90 |
| auto[1] |
6340482 |
1 |
|
|
T24 |
66 |
|
T1 |
64230 |
|
T14 |
27415 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2778220 |
1 |
|
|
T24 |
29 |
|
T1 |
28038 |
|
T14 |
11576 |
| auto[1] |
auto[0] |
auto[1] |
403876 |
1 |
|
|
T1 |
3876 |
|
T14 |
1821 |
|
T19 |
47 |
| auto[1] |
auto[1] |
auto[0] |
2755836 |
1 |
|
|
T24 |
36 |
|
T1 |
28388 |
|
T14 |
12205 |
| auto[1] |
auto[1] |
auto[1] |
402550 |
1 |
|
|
T24 |
1 |
|
T1 |
3928 |
|
T14 |
1813 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8692829 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
107 |
| auto[1] |
6339531 |
1 |
|
|
T24 |
49 |
|
T1 |
67237 |
|
T14 |
29145 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14223216 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
809144 |
1 |
|
|
T24 |
1 |
|
T1 |
9005 |
|
T14 |
3921 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8681301 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
96 |
| auto[1] |
6351059 |
1 |
|
|
T24 |
60 |
|
T1 |
71062 |
|
T14 |
29424 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2784195 |
1 |
|
|
T24 |
30 |
|
T1 |
31615 |
|
T14 |
12651 |
| auto[1] |
auto[0] |
auto[1] |
406780 |
1 |
|
|
T24 |
1 |
|
T1 |
4666 |
|
T14 |
1912 |
| auto[1] |
auto[1] |
auto[0] |
2757720 |
1 |
|
|
T24 |
29 |
|
T1 |
30442 |
|
T14 |
12852 |
| auto[1] |
auto[1] |
auto[1] |
402364 |
1 |
|
|
T1 |
4339 |
|
T14 |
2009 |
|
T19 |
84 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683030 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
92 |
| auto[1] |
6349330 |
1 |
|
|
T24 |
64 |
|
T1 |
69699 |
|
T14 |
28422 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14226495 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
805865 |
1 |
|
|
T1 |
7808 |
|
T14 |
4012 |
|
T19 |
157 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8694653 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
89 |
| auto[1] |
6337707 |
1 |
|
|
T24 |
67 |
|
T1 |
62814 |
|
T14 |
29024 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2773347 |
1 |
|
|
T24 |
34 |
|
T1 |
26514 |
|
T14 |
12538 |
| auto[1] |
auto[0] |
auto[1] |
404186 |
1 |
|
|
T1 |
3742 |
|
T14 |
2005 |
|
T19 |
87 |
| auto[1] |
auto[1] |
auto[0] |
2758495 |
1 |
|
|
T24 |
33 |
|
T1 |
28492 |
|
T14 |
12474 |
| auto[1] |
auto[1] |
auto[1] |
401679 |
1 |
|
|
T1 |
4066 |
|
T14 |
2007 |
|
T19 |
70 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8667208 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
113 |
| auto[1] |
6365152 |
1 |
|
|
T24 |
43 |
|
T1 |
67100 |
|
T14 |
28235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14223514 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
808846 |
1 |
|
|
T24 |
1 |
|
T1 |
8314 |
|
T14 |
4180 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683546 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
81 |
| auto[1] |
6348814 |
1 |
|
|
T24 |
75 |
|
T1 |
67399 |
|
T14 |
30977 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2759808 |
1 |
|
|
T24 |
41 |
|
T1 |
29089 |
|
T14 |
13915 |
| auto[1] |
auto[0] |
auto[1] |
401730 |
1 |
|
|
T24 |
1 |
|
T1 |
4001 |
|
T14 |
2193 |
| auto[1] |
auto[1] |
auto[0] |
2780160 |
1 |
|
|
T24 |
33 |
|
T1 |
29996 |
|
T14 |
12882 |
| auto[1] |
auto[1] |
auto[1] |
407116 |
1 |
|
|
T1 |
4313 |
|
T14 |
1987 |
|
T19 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8701442 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
103 |
| auto[1] |
6330918 |
1 |
|
|
T24 |
53 |
|
T1 |
66528 |
|
T14 |
29050 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14234467 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
797893 |
1 |
|
|
T1 |
8162 |
|
T14 |
4095 |
|
T19 |
111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8740543 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
120 |
| auto[1] |
6291817 |
1 |
|
|
T24 |
36 |
|
T1 |
65654 |
|
T14 |
29675 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2753330 |
1 |
|
|
T24 |
15 |
|
T1 |
29513 |
|
T14 |
12865 |
| auto[1] |
auto[0] |
auto[1] |
399066 |
1 |
|
|
T1 |
4244 |
|
T14 |
2028 |
|
T19 |
65 |
| auto[1] |
auto[1] |
auto[0] |
2740594 |
1 |
|
|
T24 |
21 |
|
T1 |
27979 |
|
T14 |
12715 |
| auto[1] |
auto[1] |
auto[1] |
398827 |
1 |
|
|
T1 |
3918 |
|
T14 |
2067 |
|
T19 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8672497 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
129 |
| auto[1] |
6359863 |
1 |
|
|
T24 |
27 |
|
T1 |
67510 |
|
T14 |
28590 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14227704 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
804656 |
1 |
|
|
T1 |
8041 |
|
T14 |
3960 |
|
T19 |
132 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8712465 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
105 |
| auto[1] |
6319895 |
1 |
|
|
T24 |
51 |
|
T1 |
63836 |
|
T14 |
28979 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2747587 |
1 |
|
|
T24 |
43 |
|
T1 |
27371 |
|
T14 |
12793 |
| auto[1] |
auto[0] |
auto[1] |
399461 |
1 |
|
|
T1 |
3979 |
|
T14 |
2021 |
|
T19 |
40 |
| auto[1] |
auto[1] |
auto[0] |
2767652 |
1 |
|
|
T24 |
8 |
|
T1 |
28424 |
|
T14 |
12226 |
| auto[1] |
auto[1] |
auto[1] |
405195 |
1 |
|
|
T1 |
4062 |
|
T14 |
1939 |
|
T19 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8680234 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
127 |
| auto[1] |
6352126 |
1 |
|
|
T24 |
29 |
|
T1 |
63325 |
|
T14 |
27677 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14222169 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
810191 |
1 |
|
|
T24 |
1 |
|
T1 |
8546 |
|
T14 |
3859 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8658829 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
101 |
| auto[1] |
6373531 |
1 |
|
|
T24 |
55 |
|
T1 |
67819 |
|
T14 |
29092 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2762851 |
1 |
|
|
T24 |
43 |
|
T1 |
32183 |
|
T14 |
13371 |
| auto[1] |
auto[0] |
auto[1] |
401715 |
1 |
|
|
T24 |
1 |
|
T1 |
4886 |
|
T14 |
2073 |
| auto[1] |
auto[1] |
auto[0] |
2800489 |
1 |
|
|
T24 |
11 |
|
T1 |
27090 |
|
T14 |
11862 |
| auto[1] |
auto[1] |
auto[1] |
408476 |
1 |
|
|
T1 |
3660 |
|
T14 |
1786 |
|
T19 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8691951 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
101 |
| auto[1] |
6340409 |
1 |
|
|
T24 |
55 |
|
T1 |
67285 |
|
T14 |
27582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14225196 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
807164 |
1 |
|
|
T1 |
8867 |
|
T14 |
3838 |
|
T19 |
129 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8692850 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
100 |
| auto[1] |
6339510 |
1 |
|
|
T24 |
56 |
|
T1 |
69820 |
|
T14 |
28466 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2768438 |
1 |
|
|
T24 |
34 |
|
T1 |
31986 |
|
T14 |
12560 |
| auto[1] |
auto[0] |
auto[1] |
402153 |
1 |
|
|
T1 |
4599 |
|
T14 |
1941 |
|
T19 |
68 |
| auto[1] |
auto[1] |
auto[0] |
2763908 |
1 |
|
|
T24 |
22 |
|
T1 |
28967 |
|
T14 |
12068 |
| auto[1] |
auto[1] |
auto[1] |
405011 |
1 |
|
|
T1 |
4268 |
|
T14 |
1897 |
|
T19 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8691705 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
123 |
| auto[1] |
6340655 |
1 |
|
|
T24 |
33 |
|
T1 |
62191 |
|
T14 |
28842 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14223468 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
808892 |
1 |
|
|
T1 |
8390 |
|
T14 |
3890 |
|
T19 |
119 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8677330 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
105 |
| auto[1] |
6355030 |
1 |
|
|
T24 |
51 |
|
T1 |
67704 |
|
T14 |
28883 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2765054 |
1 |
|
|
T24 |
43 |
|
T1 |
30030 |
|
T14 |
12702 |
| auto[1] |
auto[0] |
auto[1] |
403942 |
1 |
|
|
T1 |
4335 |
|
T14 |
1955 |
|
T19 |
82 |
| auto[1] |
auto[1] |
auto[0] |
2781084 |
1 |
|
|
T24 |
8 |
|
T1 |
29284 |
|
T14 |
12291 |
| auto[1] |
auto[1] |
auto[1] |
404950 |
1 |
|
|
T1 |
4055 |
|
T14 |
1935 |
|
T19 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8673700 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
104 |
| auto[1] |
6358660 |
1 |
|
|
T24 |
52 |
|
T1 |
67116 |
|
T14 |
29316 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14220284 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
812076 |
1 |
|
|
T1 |
8627 |
|
T14 |
4001 |
|
T19 |
104 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8666897 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
107 |
| auto[1] |
6365463 |
1 |
|
|
T24 |
49 |
|
T1 |
69261 |
|
T14 |
29245 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2791336 |
1 |
|
|
T24 |
33 |
|
T1 |
30715 |
|
T14 |
12691 |
| auto[1] |
auto[0] |
auto[1] |
407676 |
1 |
|
|
T1 |
4374 |
|
T14 |
1967 |
|
T19 |
44 |
| auto[1] |
auto[1] |
auto[0] |
2762051 |
1 |
|
|
T24 |
16 |
|
T1 |
29919 |
|
T14 |
12553 |
| auto[1] |
auto[1] |
auto[1] |
404400 |
1 |
|
|
T1 |
4253 |
|
T14 |
2034 |
|
T19 |
60 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8717016 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
94 |
| auto[1] |
6315344 |
1 |
|
|
T24 |
62 |
|
T1 |
65497 |
|
T14 |
28496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14229967 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
802393 |
1 |
|
|
T1 |
8520 |
|
T14 |
3941 |
|
T19 |
154 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8709993 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
130 |
| auto[1] |
6322367 |
1 |
|
|
T24 |
26 |
|
T1 |
68301 |
|
T14 |
28648 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2767354 |
1 |
|
|
T24 |
23 |
|
T1 |
30989 |
|
T14 |
12160 |
| auto[1] |
auto[0] |
auto[1] |
403141 |
1 |
|
|
T1 |
4442 |
|
T14 |
1900 |
|
T19 |
69 |
| auto[1] |
auto[1] |
auto[0] |
2752620 |
1 |
|
|
T24 |
3 |
|
T1 |
28792 |
|
T14 |
12547 |
| auto[1] |
auto[1] |
auto[1] |
399252 |
1 |
|
|
T1 |
4078 |
|
T14 |
2041 |
|
T19 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8654844 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
93 |
| auto[1] |
6377516 |
1 |
|
|
T24 |
63 |
|
T1 |
66795 |
|
T14 |
29159 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14225178 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
807182 |
1 |
|
|
T1 |
8689 |
|
T14 |
3829 |
|
T19 |
137 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683645 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
117 |
| auto[1] |
6348715 |
1 |
|
|
T24 |
39 |
|
T1 |
69864 |
|
T14 |
28265 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2761983 |
1 |
|
|
T24 |
15 |
|
T1 |
29677 |
|
T14 |
12540 |
| auto[1] |
auto[0] |
auto[1] |
402605 |
1 |
|
|
T1 |
4326 |
|
T14 |
1978 |
|
T19 |
57 |
| auto[1] |
auto[1] |
auto[0] |
2779550 |
1 |
|
|
T24 |
24 |
|
T1 |
31498 |
|
T14 |
11896 |
| auto[1] |
auto[1] |
auto[1] |
404577 |
1 |
|
|
T1 |
4363 |
|
T14 |
1851 |
|
T19 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8677151 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
114 |
| auto[1] |
6355209 |
1 |
|
|
T24 |
42 |
|
T1 |
62117 |
|
T14 |
27381 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14231599 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
800761 |
1 |
|
|
T1 |
8284 |
|
T14 |
3991 |
|
T19 |
163 |