Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8684850 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
93 |
| auto[1] |
6347510 |
1 |
|
|
T24 |
63 |
|
T1 |
68356 |
|
T14 |
28170 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14225812 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
806548 |
1 |
|
|
T24 |
1 |
|
T1 |
8633 |
|
T14 |
3747 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8697328 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
111 |
| auto[1] |
6335032 |
1 |
|
|
T24 |
45 |
|
T1 |
68740 |
|
T14 |
27591 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2768828 |
1 |
|
|
T24 |
17 |
|
T1 |
29732 |
|
T14 |
12722 |
| auto[1] |
auto[0] |
auto[1] |
402991 |
1 |
|
|
T1 |
4232 |
|
T14 |
1994 |
|
T19 |
51 |
| auto[1] |
auto[1] |
auto[0] |
2759656 |
1 |
|
|
T24 |
27 |
|
T1 |
30375 |
|
T14 |
11122 |
| auto[1] |
auto[1] |
auto[1] |
403557 |
1 |
|
|
T24 |
1 |
|
T1 |
4401 |
|
T14 |
1753 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |