Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8665343 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
105 |
auto[1] |
6367017 |
1 |
|
|
T24 |
51 |
|
T1 |
67913 |
|
T14 |
28768 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14231590 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
auto[1] |
800770 |
1 |
|
|
T1 |
7919 |
|
T14 |
3963 |
|
T19 |
175 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8719488 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
96 |
auto[1] |
6312872 |
1 |
|
|
T24 |
60 |
|
T1 |
65816 |
|
T14 |
29090 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2757830 |
1 |
|
|
T24 |
34 |
|
T1 |
28952 |
|
T14 |
12120 |
auto[1] |
auto[0] |
auto[1] |
400999 |
1 |
|
|
T1 |
4074 |
|
T14 |
1854 |
|
T19 |
97 |
auto[1] |
auto[1] |
auto[0] |
2754272 |
1 |
|
|
T24 |
26 |
|
T1 |
28945 |
|
T14 |
13007 |
auto[1] |
auto[1] |
auto[1] |
399771 |
1 |
|
|
T1 |
3845 |
|
T14 |
2109 |
|
T19 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |