Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8715572 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
123 |
| auto[1] |
6316788 |
1 |
|
|
T24 |
33 |
|
T1 |
69829 |
|
T14 |
27323 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14226251 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
806109 |
1 |
|
|
T24 |
1 |
|
T1 |
8529 |
|
T14 |
3846 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8691832 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
110 |
| auto[1] |
6340528 |
1 |
|
|
T24 |
46 |
|
T1 |
68366 |
|
T14 |
28323 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2782139 |
1 |
|
|
T24 |
32 |
|
T1 |
28280 |
|
T14 |
12870 |
| auto[1] |
auto[0] |
auto[1] |
405569 |
1 |
|
|
T1 |
3964 |
|
T14 |
2067 |
|
T19 |
77 |
| auto[1] |
auto[1] |
auto[0] |
2752280 |
1 |
|
|
T24 |
13 |
|
T1 |
31557 |
|
T14 |
11607 |
| auto[1] |
auto[1] |
auto[1] |
400540 |
1 |
|
|
T24 |
1 |
|
T1 |
4565 |
|
T14 |
1779 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |