Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8693257 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
103 |
| auto[1] |
6339103 |
1 |
|
|
T24 |
53 |
|
T1 |
63794 |
|
T14 |
29822 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12415337 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
146 |
| auto[1] |
2617023 |
1 |
|
|
T24 |
10 |
|
T1 |
23680 |
|
T14 |
18091 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8686041 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
121 |
| auto[1] |
6346319 |
1 |
|
|
T24 |
35 |
|
T1 |
64020 |
|
T14 |
29827 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1862760 |
1 |
|
|
T24 |
14 |
|
T1 |
20150 |
|
T14 |
6061 |
| auto[1] |
auto[0] |
auto[1] |
1314107 |
1 |
|
|
T24 |
8 |
|
T1 |
11947 |
|
T14 |
9490 |
| auto[1] |
auto[1] |
auto[0] |
1866536 |
1 |
|
|
T24 |
11 |
|
T1 |
20190 |
|
T14 |
5675 |
| auto[1] |
auto[1] |
auto[1] |
1302916 |
1 |
|
|
T24 |
2 |
|
T1 |
11733 |
|
T14 |
8601 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |