Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8699897 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
112 |
| auto[1] |
6332463 |
1 |
|
|
T24 |
44 |
|
T1 |
64449 |
|
T14 |
26677 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12414919 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
139 |
| auto[1] |
2617441 |
1 |
|
|
T24 |
17 |
|
T1 |
24929 |
|
T14 |
16659 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8690915 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
112 |
| auto[1] |
6341445 |
1 |
|
|
T24 |
44 |
|
T1 |
66864 |
|
T14 |
27870 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1865795 |
1 |
|
|
T24 |
24 |
|
T1 |
20435 |
|
T14 |
5889 |
| auto[1] |
auto[0] |
auto[1] |
1310280 |
1 |
|
|
T24 |
10 |
|
T1 |
12447 |
|
T14 |
8766 |
| auto[1] |
auto[1] |
auto[0] |
1858209 |
1 |
|
|
T24 |
3 |
|
T1 |
21500 |
|
T14 |
5322 |
| auto[1] |
auto[1] |
auto[1] |
1307161 |
1 |
|
|
T24 |
7 |
|
T1 |
12482 |
|
T14 |
7893 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |