Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8698311 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
107 |
| auto[1] |
6334049 |
1 |
|
|
T24 |
49 |
|
T1 |
65797 |
|
T14 |
29795 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12424298 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
130 |
| auto[1] |
2608062 |
1 |
|
|
T24 |
26 |
|
T1 |
25197 |
|
T14 |
16838 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8724027 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
127 |
| auto[1] |
6308333 |
1 |
|
|
T24 |
29 |
|
T1 |
66788 |
|
T14 |
28789 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1857463 |
1 |
|
|
T24 |
3 |
|
T1 |
19986 |
|
T14 |
5751 |
| auto[1] |
auto[0] |
auto[1] |
1306756 |
1 |
|
|
T24 |
10 |
|
T1 |
12335 |
|
T14 |
8606 |
| auto[1] |
auto[1] |
auto[0] |
1842808 |
1 |
|
|
T1 |
21605 |
|
T14 |
6200 |
|
T19 |
118 |
| auto[1] |
auto[1] |
auto[1] |
1301306 |
1 |
|
|
T24 |
16 |
|
T1 |
12862 |
|
T14 |
8232 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |