Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8719214 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
109 |
| auto[1] |
6313146 |
1 |
|
|
T24 |
47 |
|
T1 |
69668 |
|
T14 |
29638 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12413460 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
126 |
| auto[1] |
2618900 |
1 |
|
|
T24 |
30 |
|
T1 |
24535 |
|
T14 |
16600 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8692345 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
115 |
| auto[1] |
6340015 |
1 |
|
|
T24 |
41 |
|
T1 |
68511 |
|
T14 |
27443 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1879573 |
1 |
|
|
T24 |
10 |
|
T1 |
21743 |
|
T14 |
4978 |
| auto[1] |
auto[0] |
auto[1] |
1318503 |
1 |
|
|
T24 |
12 |
|
T1 |
12149 |
|
T14 |
7845 |
| auto[1] |
auto[1] |
auto[0] |
1841542 |
1 |
|
|
T24 |
1 |
|
T1 |
22233 |
|
T14 |
5865 |
| auto[1] |
auto[1] |
auto[1] |
1300397 |
1 |
|
|
T24 |
18 |
|
T1 |
12386 |
|
T14 |
8755 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |