Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8720706 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
105 |
| auto[1] |
6311654 |
1 |
|
|
T24 |
51 |
|
T1 |
67382 |
|
T14 |
29676 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2756667 |
1 |
|
|
T24 |
27 |
|
T1 |
31113 |
|
T14 |
13359 |
| auto[1] |
auto[0] |
auto[1] |
400121 |
1 |
|
|
T1 |
4373 |
|
T14 |
2107 |
|
T19 |
88 |
| auto[1] |
auto[1] |
auto[0] |
2754226 |
1 |
|
|
T24 |
24 |
|
T1 |
27985 |
|
T14 |
12326 |
| auto[1] |
auto[1] |
auto[1] |
400640 |
1 |
|
|
T1 |
3911 |
|
T14 |
1884 |
|
T19 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |