Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8687704 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
102 |
| auto[1] |
6344656 |
1 |
|
|
T24 |
54 |
|
T1 |
67978 |
|
T14 |
26591 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12408091 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
153 |
| auto[1] |
2624269 |
1 |
|
|
T24 |
3 |
|
T1 |
23326 |
|
T14 |
16856 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8678808 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
117 |
| auto[1] |
6353552 |
1 |
|
|
T24 |
39 |
|
T1 |
65323 |
|
T14 |
28382 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1866837 |
1 |
|
|
T24 |
28 |
|
T1 |
20215 |
|
T14 |
6344 |
| auto[1] |
auto[0] |
auto[1] |
1310637 |
1 |
|
|
T24 |
3 |
|
T1 |
11278 |
|
T14 |
9640 |
| auto[1] |
auto[1] |
auto[0] |
1862446 |
1 |
|
|
T24 |
8 |
|
T1 |
21782 |
|
T14 |
5182 |
| auto[1] |
auto[1] |
auto[1] |
1313632 |
1 |
|
|
T1 |
12048 |
|
T14 |
7216 |
|
T19 |
158 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |