Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8683374 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
135 |
auto[1] |
6348986 |
1 |
|
|
T24 |
21 |
|
T1 |
69889 |
|
T14 |
28444 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12425206 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
142 |
auto[1] |
2607154 |
1 |
|
|
T24 |
14 |
|
T1 |
23434 |
|
T14 |
18120 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8716817 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
118 |
auto[1] |
6315543 |
1 |
|
|
T24 |
38 |
|
T1 |
62583 |
|
T14 |
30464 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1845382 |
1 |
|
|
T24 |
19 |
|
T1 |
18483 |
|
T14 |
6381 |
auto[1] |
auto[0] |
auto[1] |
1298941 |
1 |
|
|
T24 |
14 |
|
T1 |
11375 |
|
T14 |
9705 |
auto[1] |
auto[1] |
auto[0] |
1863007 |
1 |
|
|
T24 |
5 |
|
T1 |
20666 |
|
T14 |
5963 |
auto[1] |
auto[1] |
auto[1] |
1308213 |
1 |
|
|
T1 |
12059 |
|
T14 |
8415 |
|
T19 |
273 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |