Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8715639 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
98 |
| auto[1] |
6316721 |
1 |
|
|
T24 |
58 |
|
T1 |
70223 |
|
T14 |
29749 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12413222 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
137 |
| auto[1] |
2619138 |
1 |
|
|
T24 |
19 |
|
T1 |
25331 |
|
T14 |
15526 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8682084 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
115 |
| auto[1] |
6350276 |
1 |
|
|
T24 |
41 |
|
T1 |
68613 |
|
T14 |
26161 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1883795 |
1 |
|
|
T24 |
9 |
|
T1 |
20109 |
|
T14 |
5246 |
| auto[1] |
auto[0] |
auto[1] |
1317830 |
1 |
|
|
T24 |
17 |
|
T1 |
11982 |
|
T14 |
7075 |
| auto[1] |
auto[1] |
auto[0] |
1847343 |
1 |
|
|
T24 |
13 |
|
T1 |
23173 |
|
T14 |
5389 |
| auto[1] |
auto[1] |
auto[1] |
1301308 |
1 |
|
|
T24 |
2 |
|
T1 |
13349 |
|
T14 |
8451 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |