Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8692829 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
107 |
| auto[1] |
6339531 |
1 |
|
|
T24 |
49 |
|
T1 |
67237 |
|
T14 |
29145 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12404734 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
136 |
| auto[1] |
2627626 |
1 |
|
|
T24 |
20 |
|
T1 |
25065 |
|
T14 |
17586 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8657901 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
131 |
| auto[1] |
6374459 |
1 |
|
|
T24 |
25 |
|
T1 |
68536 |
|
T14 |
29031 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1876668 |
1 |
|
|
T24 |
3 |
|
T1 |
21327 |
|
T14 |
5404 |
| auto[1] |
auto[0] |
auto[1] |
1317405 |
1 |
|
|
T24 |
18 |
|
T1 |
12564 |
|
T14 |
8712 |
| auto[1] |
auto[1] |
auto[0] |
1870165 |
1 |
|
|
T24 |
2 |
|
T1 |
22144 |
|
T14 |
6041 |
| auto[1] |
auto[1] |
auto[1] |
1310221 |
1 |
|
|
T24 |
2 |
|
T1 |
12501 |
|
T14 |
8874 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |