Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683030 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
92 |
| auto[1] |
6349330 |
1 |
|
|
T24 |
64 |
|
T1 |
69699 |
|
T14 |
28422 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12407040 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
126 |
| auto[1] |
2625320 |
1 |
|
|
T24 |
30 |
|
T1 |
24860 |
|
T14 |
17506 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8667650 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
116 |
| auto[1] |
6364710 |
1 |
|
|
T24 |
40 |
|
T1 |
68195 |
|
T14 |
28917 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1872434 |
1 |
|
|
T24 |
5 |
|
T1 |
21066 |
|
T14 |
5649 |
| auto[1] |
auto[0] |
auto[1] |
1315117 |
1 |
|
|
T24 |
11 |
|
T1 |
12203 |
|
T14 |
8753 |
| auto[1] |
auto[1] |
auto[0] |
1866956 |
1 |
|
|
T24 |
5 |
|
T1 |
22269 |
|
T14 |
5762 |
| auto[1] |
auto[1] |
auto[1] |
1310203 |
1 |
|
|
T24 |
19 |
|
T1 |
12657 |
|
T14 |
8753 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |