Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8667208 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
113 |
auto[1] |
6365152 |
1 |
|
|
T24 |
43 |
|
T1 |
67100 |
|
T14 |
28235 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12419890 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
140 |
auto[1] |
2612470 |
1 |
|
|
T24 |
16 |
|
T1 |
24828 |
|
T14 |
17555 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8712561 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
113 |
auto[1] |
6319799 |
1 |
|
|
T24 |
43 |
|
T1 |
65980 |
|
T14 |
28779 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1844376 |
1 |
|
|
T24 |
21 |
|
T1 |
20745 |
|
T14 |
5515 |
auto[1] |
auto[0] |
auto[1] |
1303945 |
1 |
|
|
T24 |
13 |
|
T1 |
12027 |
|
T14 |
8888 |
auto[1] |
auto[1] |
auto[0] |
1862953 |
1 |
|
|
T24 |
6 |
|
T1 |
20407 |
|
T14 |
5709 |
auto[1] |
auto[1] |
auto[1] |
1308525 |
1 |
|
|
T24 |
3 |
|
T1 |
12801 |
|
T14 |
8667 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |