Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8701442 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
103 |
| auto[1] |
6330918 |
1 |
|
|
T24 |
53 |
|
T1 |
66528 |
|
T14 |
29050 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12406535 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
129 |
| auto[1] |
2625825 |
1 |
|
|
T24 |
27 |
|
T1 |
25446 |
|
T14 |
17916 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683092 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
119 |
| auto[1] |
6349268 |
1 |
|
|
T24 |
37 |
|
T1 |
68295 |
|
T14 |
29187 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1867119 |
1 |
|
|
T24 |
5 |
|
T1 |
22275 |
|
T14 |
5156 |
| auto[1] |
auto[0] |
auto[1] |
1316615 |
1 |
|
|
T24 |
13 |
|
T1 |
12759 |
|
T14 |
8639 |
| auto[1] |
auto[1] |
auto[0] |
1856324 |
1 |
|
|
T24 |
5 |
|
T1 |
20574 |
|
T14 |
6115 |
| auto[1] |
auto[1] |
auto[1] |
1309210 |
1 |
|
|
T24 |
14 |
|
T1 |
12687 |
|
T14 |
9277 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |