Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8673700 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
104 |
| auto[1] |
6358660 |
1 |
|
|
T24 |
52 |
|
T1 |
67116 |
|
T14 |
29316 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12391266 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
144 |
| auto[1] |
2641094 |
1 |
|
|
T24 |
12 |
|
T1 |
25318 |
|
T14 |
17248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8633083 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
121 |
| auto[1] |
6399277 |
1 |
|
|
T24 |
35 |
|
T1 |
68663 |
|
T14 |
29159 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1870805 |
1 |
|
|
T24 |
9 |
|
T1 |
21291 |
|
T14 |
6183 |
| auto[1] |
auto[0] |
auto[1] |
1317994 |
1 |
|
|
T24 |
8 |
|
T1 |
12404 |
|
T14 |
8552 |
| auto[1] |
auto[1] |
auto[0] |
1887378 |
1 |
|
|
T24 |
14 |
|
T1 |
22054 |
|
T14 |
5728 |
| auto[1] |
auto[1] |
auto[1] |
1323100 |
1 |
|
|
T24 |
4 |
|
T1 |
12914 |
|
T14 |
8696 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |