Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8717016 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
94 |
| auto[1] |
6315344 |
1 |
|
|
T24 |
62 |
|
T1 |
65497 |
|
T14 |
28496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12409469 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
135 |
| auto[1] |
2622891 |
1 |
|
|
T24 |
21 |
|
T1 |
24430 |
|
T14 |
17190 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8678476 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
126 |
| auto[1] |
6353884 |
1 |
|
|
T24 |
30 |
|
T1 |
66629 |
|
T14 |
28902 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1877066 |
1 |
|
|
T24 |
5 |
|
T1 |
22118 |
|
T14 |
5681 |
| auto[1] |
auto[0] |
auto[1] |
1319214 |
1 |
|
|
T24 |
16 |
|
T1 |
12731 |
|
T14 |
8747 |
| auto[1] |
auto[1] |
auto[0] |
1853927 |
1 |
|
|
T24 |
4 |
|
T1 |
20081 |
|
T14 |
6031 |
| auto[1] |
auto[1] |
auto[1] |
1303677 |
1 |
|
|
T24 |
5 |
|
T1 |
11699 |
|
T14 |
8443 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |