Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8683709 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
116 |
| auto[1] |
6348651 |
1 |
|
|
T24 |
40 |
|
T1 |
67444 |
|
T14 |
29204 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14224213 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
156 |
| auto[1] |
808147 |
1 |
|
|
T1 |
8205 |
|
T14 |
4022 |
|
T19 |
155 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8685184 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
124 |
| auto[1] |
6347176 |
1 |
|
|
T24 |
32 |
|
T1 |
65945 |
|
T14 |
29695 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2765768 |
1 |
|
|
T24 |
23 |
|
T1 |
28597 |
|
T14 |
12934 |
| auto[1] |
auto[0] |
auto[1] |
402597 |
1 |
|
|
T1 |
4121 |
|
T14 |
1969 |
|
T19 |
86 |
| auto[1] |
auto[1] |
auto[0] |
2773261 |
1 |
|
|
T24 |
9 |
|
T1 |
29143 |
|
T14 |
12739 |
| auto[1] |
auto[1] |
auto[1] |
405550 |
1 |
|
|
T1 |
4084 |
|
T14 |
2053 |
|
T19 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |