Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8708520 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
117 |
| auto[1] |
6323840 |
1 |
|
|
T24 |
39 |
|
T1 |
65061 |
|
T14 |
26597 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14219273 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
813087 |
1 |
|
|
T24 |
1 |
|
T1 |
8373 |
|
T14 |
3697 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8655160 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
100 |
| auto[1] |
6377200 |
1 |
|
|
T24 |
56 |
|
T1 |
66699 |
|
T14 |
27277 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2807222 |
1 |
|
|
T24 |
34 |
|
T1 |
30725 |
|
T14 |
12767 |
| auto[1] |
auto[0] |
auto[1] |
412140 |
1 |
|
|
T24 |
1 |
|
T1 |
4463 |
|
T14 |
2013 |
| auto[1] |
auto[1] |
auto[0] |
2756891 |
1 |
|
|
T24 |
21 |
|
T1 |
27601 |
|
T14 |
10813 |
| auto[1] |
auto[1] |
auto[1] |
400947 |
1 |
|
|
T1 |
3910 |
|
T14 |
1684 |
|
T19 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |