Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8651283 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
100 |
| auto[1] |
6381077 |
1 |
|
|
T24 |
56 |
|
T1 |
66066 |
|
T14 |
29659 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14231627 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
800733 |
1 |
|
|
T24 |
1 |
|
T1 |
8058 |
|
T14 |
3747 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8728965 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
117 |
| auto[1] |
6303395 |
1 |
|
|
T24 |
39 |
|
T1 |
64946 |
|
T14 |
27517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2725775 |
1 |
|
|
T24 |
15 |
|
T1 |
29888 |
|
T14 |
11663 |
| auto[1] |
auto[0] |
auto[1] |
396213 |
1 |
|
|
T1 |
4097 |
|
T14 |
1833 |
|
T19 |
99 |
| auto[1] |
auto[1] |
auto[0] |
2776887 |
1 |
|
|
T24 |
23 |
|
T1 |
27000 |
|
T14 |
12107 |
| auto[1] |
auto[1] |
auto[1] |
404520 |
1 |
|
|
T24 |
1 |
|
T1 |
3961 |
|
T14 |
1914 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |