Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8722914 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
113 |
| auto[1] |
6309446 |
1 |
|
|
T24 |
43 |
|
T1 |
63016 |
|
T14 |
28788 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14224062 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
155 |
| auto[1] |
808298 |
1 |
|
|
T24 |
1 |
|
T1 |
8168 |
|
T14 |
4079 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8675650 |
1 |
|
|
T22 |
355 |
|
T23 |
32439 |
|
T24 |
81 |
| auto[1] |
6356710 |
1 |
|
|
T24 |
75 |
|
T1 |
65336 |
|
T14 |
29583 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2785071 |
1 |
|
|
T24 |
47 |
|
T1 |
30579 |
|
T14 |
12787 |
| auto[1] |
auto[0] |
auto[1] |
406036 |
1 |
|
|
T1 |
4564 |
|
T14 |
2014 |
|
T19 |
57 |
| auto[1] |
auto[1] |
auto[0] |
2763341 |
1 |
|
|
T24 |
27 |
|
T1 |
26589 |
|
T14 |
12717 |
| auto[1] |
auto[1] |
auto[1] |
402262 |
1 |
|
|
T24 |
1 |
|
T1 |
3604 |
|
T14 |
2065 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |