Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T96 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3116831459 Jul 06 04:45:59 PM PDT 24 Jul 06 04:46:00 PM PDT 24 166991689 ps
T764 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1749575140 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:14 PM PDT 24 25184832 ps
T765 /workspace/coverage/cover_reg_top/19.gpio_intr_test.633092160 Jul 06 04:46:10 PM PDT 24 Jul 06 04:46:11 PM PDT 24 13663968 ps
T97 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1394116721 Jul 06 04:46:10 PM PDT 24 Jul 06 04:46:12 PM PDT 24 32313153 ps
T766 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2276948850 Jul 06 04:46:04 PM PDT 24 Jul 06 04:46:05 PM PDT 24 37359586 ps
T767 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2339311409 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:18 PM PDT 24 39732459 ps
T103 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2480799230 Jul 06 04:46:04 PM PDT 24 Jul 06 04:46:06 PM PDT 24 369343604 ps
T768 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.578950666 Jul 06 04:46:08 PM PDT 24 Jul 06 04:46:09 PM PDT 24 91958555 ps
T769 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3915055686 Jul 06 04:46:10 PM PDT 24 Jul 06 04:46:12 PM PDT 24 35030389 ps
T770 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1278411143 Jul 06 04:46:10 PM PDT 24 Jul 06 04:46:12 PM PDT 24 653375801 ps
T771 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2153484118 Jul 06 04:45:52 PM PDT 24 Jul 06 04:45:56 PM PDT 24 710612582 ps
T772 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1599621533 Jul 06 04:46:01 PM PDT 24 Jul 06 04:46:04 PM PDT 24 157123767 ps
T773 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3669911488 Jul 06 04:46:00 PM PDT 24 Jul 06 04:46:01 PM PDT 24 13670503 ps
T774 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.893116328 Jul 06 04:45:52 PM PDT 24 Jul 06 04:45:54 PM PDT 24 25737563 ps
T775 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.135523122 Jul 06 04:46:04 PM PDT 24 Jul 06 04:46:05 PM PDT 24 153889620 ps
T776 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1100842263 Jul 06 04:45:59 PM PDT 24 Jul 06 04:46:00 PM PDT 24 30347396 ps
T777 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1745076806 Jul 06 04:45:56 PM PDT 24 Jul 06 04:46:00 PM PDT 24 875440540 ps
T778 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.719351178 Jul 06 04:46:07 PM PDT 24 Jul 06 04:46:10 PM PDT 24 42928871 ps
T104 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3188956587 Jul 06 04:45:59 PM PDT 24 Jul 06 04:46:01 PM PDT 24 102369743 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2318866342 Jul 06 04:46:11 PM PDT 24 Jul 06 04:46:13 PM PDT 24 22374676 ps
T780 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1636899222 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:15 PM PDT 24 71460410 ps
T781 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.850856078 Jul 06 04:46:01 PM PDT 24 Jul 06 04:46:02 PM PDT 24 72711458 ps
T782 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3253661573 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:18 PM PDT 24 99023395 ps
T783 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2918549701 Jul 06 04:45:46 PM PDT 24 Jul 06 04:45:47 PM PDT 24 319882304 ps
T784 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.270589734 Jul 06 04:46:08 PM PDT 24 Jul 06 04:46:11 PM PDT 24 585630537 ps
T785 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1584673471 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:14 PM PDT 24 37210332 ps
T786 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2734046298 Jul 06 04:45:54 PM PDT 24 Jul 06 04:45:56 PM PDT 24 47493093 ps
T787 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3401751635 Jul 06 04:46:19 PM PDT 24 Jul 06 04:46:21 PM PDT 24 14237656 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1758429181 Jul 06 04:45:56 PM PDT 24 Jul 06 04:45:57 PM PDT 24 40994456 ps
T789 /workspace/coverage/cover_reg_top/9.gpio_intr_test.642008675 Jul 06 04:46:07 PM PDT 24 Jul 06 04:46:08 PM PDT 24 30358692 ps
T790 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1845562725 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:20 PM PDT 24 76691881 ps
T791 /workspace/coverage/cover_reg_top/49.gpio_intr_test.611419362 Jul 06 04:46:18 PM PDT 24 Jul 06 04:46:19 PM PDT 24 14429262 ps
T107 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3286775877 Jul 06 04:45:54 PM PDT 24 Jul 06 04:45:56 PM PDT 24 69582157 ps
T792 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1005834797 Jul 06 04:45:53 PM PDT 24 Jul 06 04:45:55 PM PDT 24 14678359 ps
T793 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.878038022 Jul 06 04:46:05 PM PDT 24 Jul 06 04:46:08 PM PDT 24 190732995 ps
T794 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1493361228 Jul 06 04:46:19 PM PDT 24 Jul 06 04:46:21 PM PDT 24 38338243 ps
T795 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3887959600 Jul 06 04:46:09 PM PDT 24 Jul 06 04:46:11 PM PDT 24 416146122 ps
T105 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.469245846 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:14 PM PDT 24 182766858 ps
T796 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3972014636 Jul 06 04:46:06 PM PDT 24 Jul 06 04:46:08 PM PDT 24 317223398 ps
T797 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2420553005 Jul 06 04:45:58 PM PDT 24 Jul 06 04:45:58 PM PDT 24 55692528 ps
T798 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.200482028 Jul 06 04:46:06 PM PDT 24 Jul 06 04:46:08 PM PDT 24 48989728 ps
T799 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.25873306 Jul 06 04:46:06 PM PDT 24 Jul 06 04:46:07 PM PDT 24 80902236 ps
T800 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.909757205 Jul 06 04:46:28 PM PDT 24 Jul 06 04:46:29 PM PDT 24 92144994 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2710014631 Jul 06 04:45:51 PM PDT 24 Jul 06 04:45:53 PM PDT 24 25783053 ps
T802 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2062938225 Jul 06 04:46:11 PM PDT 24 Jul 06 04:46:12 PM PDT 24 15275734 ps
T803 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3362705323 Jul 06 04:46:04 PM PDT 24 Jul 06 04:46:05 PM PDT 24 40303839 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2396733563 Jul 06 04:45:48 PM PDT 24 Jul 06 04:45:49 PM PDT 24 128385573 ps
T805 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3578796407 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:13 PM PDT 24 23983799 ps
T806 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1409768295 Jul 06 04:46:11 PM PDT 24 Jul 06 04:46:12 PM PDT 24 65770466 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1705989805 Jul 06 04:45:52 PM PDT 24 Jul 06 04:45:54 PM PDT 24 17268390 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2047432609 Jul 06 04:46:03 PM PDT 24 Jul 06 04:46:04 PM PDT 24 21934258 ps
T809 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3265253652 Jul 06 04:45:54 PM PDT 24 Jul 06 04:45:56 PM PDT 24 26863297 ps
T810 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2031124194 Jul 06 04:46:05 PM PDT 24 Jul 06 04:46:08 PM PDT 24 76167892 ps
T811 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2754161504 Jul 06 04:45:52 PM PDT 24 Jul 06 04:45:55 PM PDT 24 99535437 ps
T812 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3569696960 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:19 PM PDT 24 42586880 ps
T813 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2560446050 Jul 06 04:45:51 PM PDT 24 Jul 06 04:45:54 PM PDT 24 274461842 ps
T814 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.676116932 Jul 06 04:46:10 PM PDT 24 Jul 06 04:46:12 PM PDT 24 63094779 ps
T815 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1165368150 Jul 06 04:45:57 PM PDT 24 Jul 06 04:45:58 PM PDT 24 18708579 ps
T84 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2885236587 Jul 06 04:45:54 PM PDT 24 Jul 06 04:45:56 PM PDT 24 23477726 ps
T816 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.336527604 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:14 PM PDT 24 46546674 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1358960682 Jul 06 04:45:58 PM PDT 24 Jul 06 04:46:00 PM PDT 24 26321475 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3684072820 Jul 06 04:45:58 PM PDT 24 Jul 06 04:46:00 PM PDT 24 407247764 ps
T819 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2196546890 Jul 06 04:46:27 PM PDT 24 Jul 06 04:46:28 PM PDT 24 36955684 ps
T85 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3765114556 Jul 06 04:46:14 PM PDT 24 Jul 06 04:46:15 PM PDT 24 37601004 ps
T820 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2331602798 Jul 06 04:46:00 PM PDT 24 Jul 06 04:46:03 PM PDT 24 168835413 ps
T821 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1963254591 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:14 PM PDT 24 174667100 ps
T822 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4137472788 Jul 06 04:45:53 PM PDT 24 Jul 06 04:45:56 PM PDT 24 47372472 ps
T823 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1347579895 Jul 06 04:46:16 PM PDT 24 Jul 06 04:46:17 PM PDT 24 86269148 ps
T824 /workspace/coverage/cover_reg_top/14.gpio_intr_test.430019934 Jul 06 04:46:08 PM PDT 24 Jul 06 04:46:09 PM PDT 24 54015440 ps
T825 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1522356652 Jul 06 04:46:11 PM PDT 24 Jul 06 04:46:13 PM PDT 24 150175423 ps
T86 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.234862147 Jul 06 04:45:52 PM PDT 24 Jul 06 04:45:54 PM PDT 24 13981946 ps
T826 /workspace/coverage/cover_reg_top/40.gpio_intr_test.857005527 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:18 PM PDT 24 34828582 ps
T827 /workspace/coverage/cover_reg_top/34.gpio_intr_test.145259667 Jul 06 04:46:22 PM PDT 24 Jul 06 04:46:23 PM PDT 24 98291175 ps
T828 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.359221127 Jul 06 04:45:51 PM PDT 24 Jul 06 04:45:53 PM PDT 24 38029710 ps
T829 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1825008694 Jul 06 04:46:02 PM PDT 24 Jul 06 04:46:04 PM PDT 24 353214295 ps
T830 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1924855275 Jul 06 04:45:52 PM PDT 24 Jul 06 04:45:54 PM PDT 24 20310558 ps
T831 /workspace/coverage/cover_reg_top/48.gpio_intr_test.27647894 Jul 06 04:46:20 PM PDT 24 Jul 06 04:46:21 PM PDT 24 14602761 ps
T832 /workspace/coverage/cover_reg_top/10.gpio_intr_test.4023402625 Jul 06 04:46:04 PM PDT 24 Jul 06 04:46:05 PM PDT 24 15207431 ps
T833 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2061723314 Jul 06 04:46:18 PM PDT 24 Jul 06 04:46:20 PM PDT 24 33722352 ps
T834 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2188581761 Jul 06 04:46:06 PM PDT 24 Jul 06 04:46:07 PM PDT 24 48227581 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1785164867 Jul 06 04:46:03 PM PDT 24 Jul 06 04:46:04 PM PDT 24 17001103 ps
T835 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3634986512 Jul 06 04:45:50 PM PDT 24 Jul 06 04:45:51 PM PDT 24 23333487 ps
T87 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.881001072 Jul 06 04:46:08 PM PDT 24 Jul 06 04:46:09 PM PDT 24 16317796 ps
T88 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.336381641 Jul 06 04:45:55 PM PDT 24 Jul 06 04:45:57 PM PDT 24 36622285 ps
T836 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2805711589 Jul 06 04:45:59 PM PDT 24 Jul 06 04:46:02 PM PDT 24 2264651988 ps
T837 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1542134168 Jul 06 04:46:14 PM PDT 24 Jul 06 04:46:15 PM PDT 24 56294785 ps
T89 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.200289640 Jul 06 04:46:02 PM PDT 24 Jul 06 04:46:03 PM PDT 24 116269480 ps
T838 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2859024112 Jul 06 04:46:12 PM PDT 24 Jul 06 04:46:14 PM PDT 24 16992097 ps
T839 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2958865257 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:18 PM PDT 24 15720275 ps
T840 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4064925076 Jul 06 04:46:26 PM PDT 24 Jul 06 04:46:27 PM PDT 24 128171932 ps
T841 /workspace/coverage/cover_reg_top/32.gpio_intr_test.589441469 Jul 06 04:46:16 PM PDT 24 Jul 06 04:46:17 PM PDT 24 29160343 ps
T842 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1931607442 Jul 06 04:46:09 PM PDT 24 Jul 06 04:46:10 PM PDT 24 87264452 ps
T843 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.666775726 Jul 06 04:46:06 PM PDT 24 Jul 06 04:46:07 PM PDT 24 162285222 ps
T844 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3134968256 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:37 PM PDT 24 522330050 ps
T845 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3454279350 Jul 06 04:46:34 PM PDT 24 Jul 06 04:46:35 PM PDT 24 44891521 ps
T846 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1751306692 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:37 PM PDT 24 64239668 ps
T847 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3593369368 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 50491420 ps
T848 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.752515411 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:36 PM PDT 24 112602930 ps
T849 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3979139559 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:33 PM PDT 24 71728559 ps
T850 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1226740063 Jul 06 04:46:21 PM PDT 24 Jul 06 04:46:23 PM PDT 24 158118634 ps
T851 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2880383232 Jul 06 04:46:21 PM PDT 24 Jul 06 04:46:22 PM PDT 24 61953601 ps
T852 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2681197972 Jul 06 04:46:26 PM PDT 24 Jul 06 04:46:28 PM PDT 24 36071785 ps
T853 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1690404204 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 43087284 ps
T854 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2936011711 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 135877441 ps
T855 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2057180751 Jul 06 04:46:34 PM PDT 24 Jul 06 04:46:36 PM PDT 24 53827064 ps
T856 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880622215 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:34 PM PDT 24 140037004 ps
T857 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3760864409 Jul 06 04:46:19 PM PDT 24 Jul 06 04:46:21 PM PDT 24 37836076 ps
T858 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2546085675 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 148547022 ps
T859 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3342247898 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 194985662 ps
T860 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1762080564 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:26 PM PDT 24 28102171 ps
T861 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1163182216 Jul 06 04:46:20 PM PDT 24 Jul 06 04:46:21 PM PDT 24 208869925 ps
T862 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4166554633 Jul 06 04:46:20 PM PDT 24 Jul 06 04:46:22 PM PDT 24 30037218 ps
T863 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3625494832 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 130414478 ps
T864 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2937240191 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 50355839 ps
T865 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2235787326 Jul 06 04:46:30 PM PDT 24 Jul 06 04:46:31 PM PDT 24 53260898 ps
T866 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3922628123 Jul 06 04:46:27 PM PDT 24 Jul 06 04:46:29 PM PDT 24 331493874 ps
T867 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2616044657 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:33 PM PDT 24 231887003 ps
T868 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1039420127 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 84389333 ps
T869 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1564436021 Jul 06 04:46:26 PM PDT 24 Jul 06 04:46:28 PM PDT 24 315240333 ps
T870 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3290666708 Jul 06 04:46:22 PM PDT 24 Jul 06 04:46:23 PM PDT 24 108645366 ps
T871 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.246631905 Jul 06 04:46:34 PM PDT 24 Jul 06 04:46:35 PM PDT 24 117984245 ps
T872 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.255572337 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:18 PM PDT 24 232769274 ps
T873 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1926472955 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:19 PM PDT 24 60618287 ps
T874 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.572026522 Jul 06 04:46:22 PM PDT 24 Jul 06 04:46:24 PM PDT 24 55622894 ps
T875 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.440650490 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 29075975 ps
T876 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.887547526 Jul 06 04:46:21 PM PDT 24 Jul 06 04:46:23 PM PDT 24 275689264 ps
T877 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4021390136 Jul 06 04:46:34 PM PDT 24 Jul 06 04:46:36 PM PDT 24 96264846 ps
T878 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1317345661 Jul 06 04:46:18 PM PDT 24 Jul 06 04:46:20 PM PDT 24 773639880 ps
T879 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224747729 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:36 PM PDT 24 70590261 ps
T880 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3781105195 Jul 06 04:46:36 PM PDT 24 Jul 06 04:46:38 PM PDT 24 36575939 ps
T881 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1072305374 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:26 PM PDT 24 141750976 ps
T882 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164948552 Jul 06 04:46:20 PM PDT 24 Jul 06 04:46:22 PM PDT 24 102688658 ps
T883 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1764513862 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 77242993 ps
T884 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1366774555 Jul 06 04:46:26 PM PDT 24 Jul 06 04:46:28 PM PDT 24 57011606 ps
T885 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3721637501 Jul 06 04:46:33 PM PDT 24 Jul 06 04:46:34 PM PDT 24 122097648 ps
T886 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1687810017 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 73021647 ps
T887 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2897061833 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 91992215 ps
T888 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3468354553 Jul 06 04:46:28 PM PDT 24 Jul 06 04:46:29 PM PDT 24 47482767 ps
T889 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707633167 Jul 06 04:46:27 PM PDT 24 Jul 06 04:46:28 PM PDT 24 480862498 ps
T890 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1258489828 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:34 PM PDT 24 52089065 ps
T891 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.663505854 Jul 06 04:47:38 PM PDT 24 Jul 06 04:47:40 PM PDT 24 66246523 ps
T892 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1790981474 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 103729325 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1057420267 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:34 PM PDT 24 162197458 ps
T894 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2552286013 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 120917043 ps
T895 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3258299826 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 41337329 ps
T896 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3920546212 Jul 06 04:46:19 PM PDT 24 Jul 06 04:46:21 PM PDT 24 34562533 ps
T897 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.214483148 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:26 PM PDT 24 97451312 ps
T898 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.890973554 Jul 06 04:46:19 PM PDT 24 Jul 06 04:46:21 PM PDT 24 249331155 ps
T899 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4081449599 Jul 06 04:46:33 PM PDT 24 Jul 06 04:46:34 PM PDT 24 55327294 ps
T900 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1015039372 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:26 PM PDT 24 35296775 ps
T901 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3278102239 Jul 06 04:46:18 PM PDT 24 Jul 06 04:46:21 PM PDT 24 120565083 ps
T902 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1848145555 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 39883721 ps
T903 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4260628122 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:33 PM PDT 24 191384781 ps
T904 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1059207781 Jul 06 04:46:21 PM PDT 24 Jul 06 04:46:23 PM PDT 24 42008519 ps
T905 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1761238035 Jul 06 04:46:18 PM PDT 24 Jul 06 04:46:21 PM PDT 24 41851454 ps
T906 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2611023418 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 52349333 ps
T907 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463521854 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 244745306 ps
T908 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3046236240 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:33 PM PDT 24 77859853 ps
T909 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1051502154 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:27 PM PDT 24 52116092 ps
T910 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.20155151 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 117846536 ps
T911 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1331994696 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 131809748 ps
T912 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.383889971 Jul 06 04:46:33 PM PDT 24 Jul 06 04:46:34 PM PDT 24 67155479 ps
T913 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3162937732 Jul 06 04:46:29 PM PDT 24 Jul 06 04:46:30 PM PDT 24 88362255 ps
T914 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398958820 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 46627192 ps
T915 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3347015617 Jul 06 04:46:20 PM PDT 24 Jul 06 04:46:22 PM PDT 24 122948935 ps
T916 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2090593748 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:36 PM PDT 24 250149578 ps
T917 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.398615116 Jul 06 04:46:20 PM PDT 24 Jul 06 04:46:22 PM PDT 24 107142487 ps
T918 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1638531760 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:36 PM PDT 24 77180157 ps
T919 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1715363770 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 319349289 ps
T920 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2014909123 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:36 PM PDT 24 223641827 ps
T921 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.989931044 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 114568582 ps
T922 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154864561 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 207273141 ps
T923 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4139186230 Jul 06 04:46:37 PM PDT 24 Jul 06 04:46:38 PM PDT 24 50099946 ps
T924 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3875080777 Jul 06 04:46:17 PM PDT 24 Jul 06 04:46:19 PM PDT 24 99436599 ps
T925 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.614827262 Jul 06 04:46:28 PM PDT 24 Jul 06 04:46:30 PM PDT 24 1821228865 ps
T926 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2612341229 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 37225433 ps
T927 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304667542 Jul 06 04:46:34 PM PDT 24 Jul 06 04:46:36 PM PDT 24 184950173 ps
T928 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3586130244 Jul 06 04:46:35 PM PDT 24 Jul 06 04:46:37 PM PDT 24 42264963 ps
T929 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1187608158 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 378610446 ps
T930 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3810886053 Jul 06 04:46:22 PM PDT 24 Jul 06 04:46:24 PM PDT 24 279198079 ps
T931 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1178093699 Jul 06 04:46:23 PM PDT 24 Jul 06 04:46:25 PM PDT 24 520855793 ps
T932 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.393438318 Jul 06 04:46:31 PM PDT 24 Jul 06 04:46:33 PM PDT 24 176490568 ps
T933 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.563752504 Jul 06 04:46:28 PM PDT 24 Jul 06 04:46:29 PM PDT 24 303022826 ps
T934 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.353206711 Jul 06 04:46:26 PM PDT 24 Jul 06 04:46:28 PM PDT 24 89621939 ps
T935 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1279466744 Jul 06 04:46:27 PM PDT 24 Jul 06 04:46:28 PM PDT 24 133912397 ps
T936 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4272551958 Jul 06 04:46:33 PM PDT 24 Jul 06 04:46:35 PM PDT 24 629860637 ps
T937 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1548846291 Jul 06 04:46:22 PM PDT 24 Jul 06 04:46:24 PM PDT 24 44492544 ps
T938 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3020226459 Jul 06 04:46:25 PM PDT 24 Jul 06 04:46:27 PM PDT 24 229967610 ps
T939 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1313230780 Jul 06 04:46:19 PM PDT 24 Jul 06 04:46:21 PM PDT 24 121212119 ps
T940 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.775747449 Jul 06 04:46:33 PM PDT 24 Jul 06 04:46:34 PM PDT 24 66759835 ps
T941 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.519270525 Jul 06 04:46:21 PM PDT 24 Jul 06 04:46:22 PM PDT 24 84164479 ps
T942 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3588285201 Jul 06 04:46:24 PM PDT 24 Jul 06 04:46:26 PM PDT 24 25981678 ps
T943 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3181786857 Jul 06 04:46:32 PM PDT 24 Jul 06 04:46:34 PM PDT 24 50105609 ps

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3907565561
Short name T1
Test name
Test status
Simulation time 358597866085 ps
CPU time 588.25 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:59:45 PM PDT 24
Peak memory 207072 kb
Host smart-93306d46-d7f2-4555-9aa2-ee47ce835dd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3907565561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3907565561
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.4253447399
Short name T11
Test name
Test status
Simulation time 44484209 ps
CPU time 1.83 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 198576 kb
Host smart-7ee52434-0109-485c-8da6-427befc34d38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253447399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.4253447399
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1538964975
Short name T31
Test name
Test status
Simulation time 148604629 ps
CPU time 0.98 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 215368 kb
Host smart-faba3d00-b96b-4b8d-8de8-23349dd87ecc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538964975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1538964975
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4037592776
Short name T67
Test name
Test status
Simulation time 17507539 ps
CPU time 0.76 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 196936 kb
Host smart-eddaf7c8-58b8-459a-b582-168c739bee16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037592776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4037592776
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2820413633
Short name T37
Test name
Test status
Simulation time 148946682 ps
CPU time 1.16 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198532 kb
Host smart-98e4db0f-eb80-48be-8f97-5aa3de0e1ab5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820413633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2820413633
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3984684681
Short name T51
Test name
Test status
Simulation time 182973260 ps
CPU time 0.57 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 195276 kb
Host smart-42f5d173-1006-441b-ba05-94ee8674491c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984684681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3984684681
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.3887959600
Short name T795
Test name
Test status
Simulation time 416146122 ps
CPU time 1.4 seconds
Started Jul 06 04:46:09 PM PDT 24
Finished Jul 06 04:46:11 PM PDT 24
Peak memory 198636 kb
Host smart-940ed987-9edf-4312-90e5-20467e158c74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887959600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.3887959600
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2756864177
Short name T70
Test name
Test status
Simulation time 282053147 ps
CPU time 0.83 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 196784 kb
Host smart-9c781ea6-d163-4301-a350-4f30708297a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756864177 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2756864177
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2480799230
Short name T103
Test name
Test status
Simulation time 369343604 ps
CPU time 1.52 seconds
Started Jul 06 04:46:04 PM PDT 24
Finished Jul 06 04:46:06 PM PDT 24
Peak memory 198604 kb
Host smart-dac1ddaa-fbe3-4c59-b6f4-54510130414d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480799230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2480799230
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2396733563
Short name T804
Test name
Test status
Simulation time 128385573 ps
CPU time 0.66 seconds
Started Jul 06 04:45:48 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 194844 kb
Host smart-f90b41d5-51a1-424e-9fd1-38fdd2982376
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396733563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2396733563
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2153484118
Short name T771
Test name
Test status
Simulation time 710612582 ps
CPU time 2.3 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 197172 kb
Host smart-11927347-669a-4475-ab12-150b67387cf0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153484118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2153484118
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1924855275
Short name T830
Test name
Test status
Simulation time 20310558 ps
CPU time 0.71 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 195376 kb
Host smart-6c2c5ffe-826e-448a-9492-95af4958f6f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924855275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1924855275
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3043363530
Short name T743
Test name
Test status
Simulation time 41108660 ps
CPU time 1.16 seconds
Started Jul 06 04:45:55 PM PDT 24
Finished Jul 06 04:45:57 PM PDT 24
Peak memory 198496 kb
Host smart-958399c6-2f72-403b-9884-113491879f48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043363530 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3043363530
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.699891294
Short name T750
Test name
Test status
Simulation time 14724456 ps
CPU time 0.62 seconds
Started Jul 06 04:45:48 PM PDT 24
Finished Jul 06 04:45:49 PM PDT 24
Peak memory 196036 kb
Host smart-18774279-f1df-4a5f-b023-4ca07d654d9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699891294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.699891294
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1645860866
Short name T746
Test name
Test status
Simulation time 30343554 ps
CPU time 0.58 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 194340 kb
Host smart-c8babd3c-a7e0-4be6-9fca-d532497c0c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645860866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1645860866
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2918549701
Short name T783
Test name
Test status
Simulation time 319882304 ps
CPU time 0.86 seconds
Started Jul 06 04:45:46 PM PDT 24
Finished Jul 06 04:45:47 PM PDT 24
Peak memory 197468 kb
Host smart-ebcd8380-1c81-4abd-8b6d-e02316c30f8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918549701 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2918549701
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2754161504
Short name T811
Test name
Test status
Simulation time 99535437 ps
CPU time 1.29 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:55 PM PDT 24
Peak memory 198588 kb
Host smart-df79651d-d7fc-4d09-b627-85dbe1d67779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754161504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2754161504
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4215224693
Short name T38
Test name
Test status
Simulation time 240198332 ps
CPU time 1.15 seconds
Started Jul 06 04:45:53 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198700 kb
Host smart-547d392c-2771-48fa-af2a-8872a0532a89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215224693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4215224693
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2560446050
Short name T813
Test name
Test status
Simulation time 274461842 ps
CPU time 2.08 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 197044 kb
Host smart-fa7074fb-8b48-44d4-9ac9-18f0ae25de01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560446050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2560446050
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.359221127
Short name T828
Test name
Test status
Simulation time 38029710 ps
CPU time 0.61 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:53 PM PDT 24
Peak memory 195872 kb
Host smart-5af8d384-5084-4232-a648-bdf7f7a2c485
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359221127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.359221127
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3860996035
Short name T734
Test name
Test status
Simulation time 67742643 ps
CPU time 0.83 seconds
Started Jul 06 04:45:54 PM PDT 24
Finished Jul 06 04:45:55 PM PDT 24
Peak memory 198492 kb
Host smart-239b2f19-3345-4248-86ed-769dced46f42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860996035 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3860996035
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2885236587
Short name T84
Test name
Test status
Simulation time 23477726 ps
CPU time 0.61 seconds
Started Jul 06 04:45:54 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 195308 kb
Host smart-79dc5746-f91b-4962-b2a0-0b0684ca3749
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885236587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2885236587
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1705989805
Short name T807
Test name
Test status
Simulation time 17268390 ps
CPU time 0.61 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 194236 kb
Host smart-b45d72ac-4dfe-47bc-8091-6d342d616c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705989805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1705989805
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3634986512
Short name T835
Test name
Test status
Simulation time 23333487 ps
CPU time 0.72 seconds
Started Jul 06 04:45:50 PM PDT 24
Finished Jul 06 04:45:51 PM PDT 24
Peak memory 196648 kb
Host smart-a571f2e9-042e-456c-8eae-ab5c820db684
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634986512 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3634986512
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3817790671
Short name T742
Test name
Test status
Simulation time 41226423 ps
CPU time 2.12 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198580 kb
Host smart-31c15166-2e81-4023-9fe2-0c068c331084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817790671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3817790671
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.332842934
Short name T29
Test name
Test status
Simulation time 123516702 ps
CPU time 1.47 seconds
Started Jul 06 04:45:53 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198592 kb
Host smart-e3134f6a-b90f-449e-a353-5ddfef2aeedb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332842934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.332842934
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.578950666
Short name T768
Test name
Test status
Simulation time 91958555 ps
CPU time 1.01 seconds
Started Jul 06 04:46:08 PM PDT 24
Finished Jul 06 04:46:09 PM PDT 24
Peak memory 198488 kb
Host smart-7c8c77f0-9b5b-4033-9b46-3132a09c3b6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578950666 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.578950666
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.881001072
Short name T87
Test name
Test status
Simulation time 16317796 ps
CPU time 0.62 seconds
Started Jul 06 04:46:08 PM PDT 24
Finished Jul 06 04:46:09 PM PDT 24
Peak memory 195264 kb
Host smart-b75f6a80-e6e7-4ec3-a186-b16ceb71d621
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881001072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.881001072
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4023402625
Short name T832
Test name
Test status
Simulation time 15207431 ps
CPU time 0.6 seconds
Started Jul 06 04:46:04 PM PDT 24
Finished Jul 06 04:46:05 PM PDT 24
Peak memory 194972 kb
Host smart-98fd0fdb-52c6-460e-9c48-9e201f6298f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023402625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4023402625
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.25873306
Short name T799
Test name
Test status
Simulation time 80902236 ps
CPU time 0.7 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:07 PM PDT 24
Peak memory 195528 kb
Host smart-c99688b2-ecf7-409c-ab84-c755db393978
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873306 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.gpio_same_csr_outstanding.25873306
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.200482028
Short name T798
Test name
Test status
Simulation time 48989728 ps
CPU time 1.28 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198640 kb
Host smart-095913c1-7017-4b13-a62d-83af2c462bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200482028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.200482028
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1931607442
Short name T842
Test name
Test status
Simulation time 87264452 ps
CPU time 0.65 seconds
Started Jul 06 04:46:09 PM PDT 24
Finished Jul 06 04:46:10 PM PDT 24
Peak memory 196972 kb
Host smart-c112e243-80ba-41fe-9e72-3cb1e9f702ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931607442 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1931607442
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.336527604
Short name T816
Test name
Test status
Simulation time 46546674 ps
CPU time 0.66 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 195924 kb
Host smart-709a8562-7209-438c-b222-28e0b6a5f4cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336527604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.336527604
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.123539190
Short name T726
Test name
Test status
Simulation time 47681023 ps
CPU time 0.57 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 194844 kb
Host smart-4a58039b-e2ad-4cf8-a6bf-a54ad976eee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123539190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.123539190
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1584673471
Short name T785
Test name
Test status
Simulation time 37210332 ps
CPU time 0.85 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 197440 kb
Host smart-85c3940f-f2c5-40df-bf15-da31c7a908b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584673471 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1584673471
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2031124194
Short name T810
Test name
Test status
Simulation time 76167892 ps
CPU time 1.92 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198696 kb
Host smart-e312532b-95f1-40ff-b826-e14f8ed55fa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031124194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2031124194
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.135523122
Short name T775
Test name
Test status
Simulation time 153889620 ps
CPU time 0.93 seconds
Started Jul 06 04:46:04 PM PDT 24
Finished Jul 06 04:46:05 PM PDT 24
Peak memory 198492 kb
Host smart-d8e039e8-9d71-4dd8-b430-dbe85187db71
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135523122 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.135523122
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.641401183
Short name T68
Test name
Test status
Simulation time 48958149 ps
CPU time 0.58 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:07 PM PDT 24
Peak memory 195480 kb
Host smart-26c2e9ef-573a-48ff-98fc-19f3ac175592
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641401183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.641401183
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2030564724
Short name T740
Test name
Test status
Simulation time 55816418 ps
CPU time 0.6 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:06 PM PDT 24
Peak memory 194840 kb
Host smart-2a11f77c-8809-4849-8929-bf8a44c3c7f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030564724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2030564724
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2866137735
Short name T759
Test name
Test status
Simulation time 561748009 ps
CPU time 2.79 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:10 PM PDT 24
Peak memory 198628 kb
Host smart-424ed99f-7f90-4c66-9cee-0589282582c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866137735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2866137735
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.909757205
Short name T800
Test name
Test status
Simulation time 92144994 ps
CPU time 1.14 seconds
Started Jul 06 04:46:28 PM PDT 24
Finished Jul 06 04:46:29 PM PDT 24
Peak memory 198576 kb
Host smart-a75ab48b-11eb-4d8e-b9ae-4c2bb049e79e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909757205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.909757205
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1278411143
Short name T770
Test name
Test status
Simulation time 653375801 ps
CPU time 1.1 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 198492 kb
Host smart-efc53b7e-84dc-4def-bb7d-c0ddd40b738c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278411143 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1278411143
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3362705323
Short name T803
Test name
Test status
Simulation time 40303839 ps
CPU time 0.58 seconds
Started Jul 06 04:46:04 PM PDT 24
Finished Jul 06 04:46:05 PM PDT 24
Peak memory 194480 kb
Host smart-45f3360d-ee75-413e-b520-9bd8331c4eba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362705323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3362705323
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.87617614
Short name T749
Test name
Test status
Simulation time 17935856 ps
CPU time 0.59 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 194272 kb
Host smart-dfc61ce1-fdeb-44f4-8dde-b01d5e634b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87617614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.87617614
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1394116721
Short name T97
Test name
Test status
Simulation time 32313153 ps
CPU time 0.88 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 196836 kb
Host smart-fbd8afaf-e322-4f16-8097-6a58ad836508
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394116721 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1394116721
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2270186235
Short name T747
Test name
Test status
Simulation time 2441516614 ps
CPU time 2.03 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198632 kb
Host smart-b6335ed0-fdb4-462b-a878-ff76be2944d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270186235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2270186235
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1771923219
Short name T763
Test name
Test status
Simulation time 33103924 ps
CPU time 1.54 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198704 kb
Host smart-83bd2049-37d6-4636-8444-9ea3fe79eeb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771923219 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1771923219
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1749575140
Short name T764
Test name
Test status
Simulation time 25184832 ps
CPU time 0.59 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 195048 kb
Host smart-f00888a7-0c46-48bd-b3c6-b2c115ffb006
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749575140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1749575140
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.430019934
Short name T824
Test name
Test status
Simulation time 54015440 ps
CPU time 0.56 seconds
Started Jul 06 04:46:08 PM PDT 24
Finished Jul 06 04:46:09 PM PDT 24
Peak memory 194212 kb
Host smart-f243c8b5-5f4a-4fb3-826f-657be272f3d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430019934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.430019934
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1886292158
Short name T91
Test name
Test status
Simulation time 27030557 ps
CPU time 0.92 seconds
Started Jul 06 04:46:07 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198384 kb
Host smart-ed797a68-12fa-4d8e-afaf-54a15448ecf6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886292158 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1886292158
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.878038022
Short name T793
Test name
Test status
Simulation time 190732995 ps
CPU time 2.15 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198652 kb
Host smart-9a92aecf-5956-4808-bf10-119a66ed4bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878038022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.878038022
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3972014636
Short name T796
Test name
Test status
Simulation time 317223398 ps
CPU time 1.19 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 198624 kb
Host smart-d126e011-163d-453f-afba-9f3cfc4ae502
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972014636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3972014636
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3621586671
Short name T756
Test name
Test status
Simulation time 26661181 ps
CPU time 0.69 seconds
Started Jul 06 04:46:13 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 197300 kb
Host smart-8fc187de-0f98-48b3-b797-2e9265b6e205
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621586671 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3621586671
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1495570140
Short name T66
Test name
Test status
Simulation time 13353744 ps
CPU time 0.56 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 194484 kb
Host smart-7935f5f0-74d3-4a93-a15a-711b84d3257f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495570140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1495570140
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.753792956
Short name T737
Test name
Test status
Simulation time 31548211 ps
CPU time 0.59 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 194276 kb
Host smart-1bc37381-6d6a-4855-93e4-5a9683fc6247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753792956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.753792956
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2062938225
Short name T802
Test name
Test status
Simulation time 15275734 ps
CPU time 0.66 seconds
Started Jul 06 04:46:11 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 196060 kb
Host smart-bdb049b9-83ab-44c5-a9dd-e8067e7c5d66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062938225 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2062938225
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3707887926
Short name T732
Test name
Test status
Simulation time 48635397 ps
CPU time 2.52 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:16 PM PDT 24
Peak memory 198588 kb
Host smart-a8eb6427-803e-47be-b3ca-bdc41bb51580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707887926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3707887926
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3473448725
Short name T28
Test name
Test status
Simulation time 208548106 ps
CPU time 1.16 seconds
Started Jul 06 04:46:13 PM PDT 24
Finished Jul 06 04:46:15 PM PDT 24
Peak memory 198560 kb
Host smart-e7a40b4d-871a-4097-91ef-10ee90299813
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473448725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3473448725
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1963254591
Short name T821
Test name
Test status
Simulation time 174667100 ps
CPU time 0.9 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 198472 kb
Host smart-08541fd6-66ea-4078-80b0-2a1a05592d83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963254591 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1963254591
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3765114556
Short name T85
Test name
Test status
Simulation time 37601004 ps
CPU time 0.6 seconds
Started Jul 06 04:46:14 PM PDT 24
Finished Jul 06 04:46:15 PM PDT 24
Peak memory 195376 kb
Host smart-626dd625-f683-4061-937b-231b7cd9c58f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765114556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3765114556
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3437031513
Short name T754
Test name
Test status
Simulation time 49195407 ps
CPU time 0.62 seconds
Started Jul 06 04:46:15 PM PDT 24
Finished Jul 06 04:46:16 PM PDT 24
Peak memory 194176 kb
Host smart-4376d6b4-dd53-4885-bb98-da2872742336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437031513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3437031513
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3382053360
Short name T94
Test name
Test status
Simulation time 91177605 ps
CPU time 0.73 seconds
Started Jul 06 04:46:13 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 196312 kb
Host smart-8f6bc7a3-127b-484f-bd0c-742559cccac1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382053360 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3382053360
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1522356652
Short name T825
Test name
Test status
Simulation time 150175423 ps
CPU time 1.17 seconds
Started Jul 06 04:46:11 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 198608 kb
Host smart-bb627142-b155-4658-aac7-170569caaa4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522356652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1522356652
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.469245846
Short name T105
Test name
Test status
Simulation time 182766858 ps
CPU time 1.41 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 198592 kb
Host smart-2f9c00f6-73ff-4b57-ae2b-8b11bc309887
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469245846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.469245846
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2318866342
Short name T779
Test name
Test status
Simulation time 22374676 ps
CPU time 0.8 seconds
Started Jul 06 04:46:11 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 198400 kb
Host smart-556a5e72-f3c7-4cfd-aa37-3cb8aff97cb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318866342 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2318866342
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2553482516
Short name T102
Test name
Test status
Simulation time 13822428 ps
CPU time 0.59 seconds
Started Jul 06 04:46:13 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 195724 kb
Host smart-e27f1a54-a9a6-489f-8737-353bcfe92926
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553482516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2553482516
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2859024112
Short name T838
Test name
Test status
Simulation time 16992097 ps
CPU time 0.61 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 194940 kb
Host smart-cd68cdc6-8ba2-48d9-a017-fb768eff9273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859024112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2859024112
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3915055686
Short name T769
Test name
Test status
Simulation time 35030389 ps
CPU time 0.67 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 195312 kb
Host smart-dc4b296b-e616-45c7-b66f-6e5213eebcac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915055686 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3915055686
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1636899222
Short name T780
Test name
Test status
Simulation time 71460410 ps
CPU time 1.91 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:15 PM PDT 24
Peak memory 198552 kb
Host smart-46bd1329-36be-44a6-a537-c97794935343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636899222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1636899222
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.999785393
Short name T723
Test name
Test status
Simulation time 193147592 ps
CPU time 0.87 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 197480 kb
Host smart-d0bb9ce9-bbb6-4849-a6bc-eba7d68d18f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999785393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.999785393
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.676116932
Short name T814
Test name
Test status
Simulation time 63094779 ps
CPU time 0.74 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 198476 kb
Host smart-f9a2972b-eb20-4977-a530-4a203456095a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676116932 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.676116932
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2339311409
Short name T767
Test name
Test status
Simulation time 39732459 ps
CPU time 0.62 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:18 PM PDT 24
Peak memory 194492 kb
Host smart-f7ef572c-6ded-4ed2-aaff-3166e3d39959
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339311409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2339311409
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3578796407
Short name T805
Test name
Test status
Simulation time 23983799 ps
CPU time 0.59 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 194196 kb
Host smart-9602b803-61d2-4138-93d8-80ef2428b57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578796407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3578796407
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3253661573
Short name T782
Test name
Test status
Simulation time 99023395 ps
CPU time 0.75 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:18 PM PDT 24
Peak memory 196684 kb
Host smart-2f9eb32a-db9b-46e9-8ae6-42bdcc98d498
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253661573 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3253661573
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1845562725
Short name T790
Test name
Test status
Simulation time 76691881 ps
CPU time 1.66 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 198672 kb
Host smart-ce7f6021-5167-4087-883c-813469026929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845562725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1845562725
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1347579895
Short name T823
Test name
Test status
Simulation time 86269148 ps
CPU time 0.9 seconds
Started Jul 06 04:46:16 PM PDT 24
Finished Jul 06 04:46:17 PM PDT 24
Peak memory 197696 kb
Host smart-7ee15002-f3b4-492b-8500-aa5abc6ef6de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347579895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1347579895
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3939536242
Short name T745
Test name
Test status
Simulation time 57631190 ps
CPU time 0.87 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 198436 kb
Host smart-99a31d04-e4bb-461a-ac81-bf90a7523df3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939536242 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3939536242
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1770692435
Short name T100
Test name
Test status
Simulation time 13861697 ps
CPU time 0.6 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 194948 kb
Host smart-bcba22bd-d829-4f9d-9dba-c486e2bf61d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770692435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1770692435
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.633092160
Short name T765
Test name
Test status
Simulation time 13663968 ps
CPU time 0.6 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:11 PM PDT 24
Peak memory 194944 kb
Host smart-91ed108f-c837-49dc-8801-f1d170cd9862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633092160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.633092160
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1568348797
Short name T93
Test name
Test status
Simulation time 168294085 ps
CPU time 0.92 seconds
Started Jul 06 04:46:13 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 196976 kb
Host smart-52f5c443-addb-41e3-9739-af2784cfd78e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568348797 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1568348797
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4214230501
Short name T735
Test name
Test status
Simulation time 173286810 ps
CPU time 1.18 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 198588 kb
Host smart-27714c6c-4e00-48d4-8282-dcb855417c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214230501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.4214230501
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.921369892
Short name T106
Test name
Test status
Simulation time 224980676 ps
CPU time 1.53 seconds
Started Jul 06 04:46:10 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 198576 kb
Host smart-00da5739-069d-4eb5-a818-ee89eba697a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921369892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.921369892
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.665072824
Short name T73
Test name
Test status
Simulation time 91587853 ps
CPU time 0.89 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:07 PM PDT 24
Peak memory 197228 kb
Host smart-4bc1780c-1b14-4680-ac96-908b1cba98f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665072824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.665072824
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1083476092
Short name T755
Test name
Test status
Simulation time 36645272 ps
CPU time 1.42 seconds
Started Jul 06 04:45:53 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198536 kb
Host smart-1fc01b8e-a66c-4888-9620-6742cf87e8ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083476092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1083476092
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4280119807
Short name T83
Test name
Test status
Simulation time 62757613 ps
CPU time 0.66 seconds
Started Jul 06 04:45:56 PM PDT 24
Finished Jul 06 04:45:57 PM PDT 24
Peak memory 195396 kb
Host smart-3b6fbdd8-9ead-48a6-a328-7c6abd397f3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280119807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4280119807
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1758429181
Short name T788
Test name
Test status
Simulation time 40994456 ps
CPU time 1.02 seconds
Started Jul 06 04:45:56 PM PDT 24
Finished Jul 06 04:45:57 PM PDT 24
Peak memory 198508 kb
Host smart-3968612e-5d4f-4b13-9eee-f98c93f33ca4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758429181 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1758429181
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.336381641
Short name T88
Test name
Test status
Simulation time 36622285 ps
CPU time 0.62 seconds
Started Jul 06 04:45:55 PM PDT 24
Finished Jul 06 04:45:57 PM PDT 24
Peak memory 195288 kb
Host smart-d01d9fc8-6a25-47df-bd94-c8f0cde23d44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336381641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.336381641
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2779169048
Short name T739
Test name
Test status
Simulation time 33832168 ps
CPU time 0.61 seconds
Started Jul 06 04:45:55 PM PDT 24
Finished Jul 06 04:45:57 PM PDT 24
Peak memory 194216 kb
Host smart-3de4b955-833f-4aa0-a6a5-38bd72545089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779169048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2779169048
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2710014631
Short name T801
Test name
Test status
Simulation time 25783053 ps
CPU time 0.7 seconds
Started Jul 06 04:45:51 PM PDT 24
Finished Jul 06 04:45:53 PM PDT 24
Peak memory 196048 kb
Host smart-d909fe13-9ab8-4ae5-b4f5-cfdab3522a57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710014631 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2710014631
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4137472788
Short name T822
Test name
Test status
Simulation time 47372472 ps
CPU time 1.37 seconds
Started Jul 06 04:45:53 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198608 kb
Host smart-0f414285-8005-4742-8420-dcf4932280d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137472788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4137472788
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3286775877
Short name T107
Test name
Test status
Simulation time 69582157 ps
CPU time 1.15 seconds
Started Jul 06 04:45:54 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198616 kb
Host smart-bdacd8f7-7722-4ce6-b9a6-2de1c76e6da5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286775877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3286775877
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3864929079
Short name T744
Test name
Test status
Simulation time 120397908 ps
CPU time 0.63 seconds
Started Jul 06 04:46:11 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 194864 kb
Host smart-d7e0ed49-4596-437f-8a28-6964a7e63dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864929079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3864929079
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1409768295
Short name T806
Test name
Test status
Simulation time 65770466 ps
CPU time 0.63 seconds
Started Jul 06 04:46:11 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 194332 kb
Host smart-9f1341f9-ff32-4f18-8a40-37ec032dfcae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409768295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1409768295
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1086220899
Short name T727
Test name
Test status
Simulation time 14068200 ps
CPU time 0.59 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:19 PM PDT 24
Peak memory 194220 kb
Host smart-ba2ef7dc-e757-49c9-9a34-d96ce6e34f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086220899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1086220899
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1743089733
Short name T752
Test name
Test status
Simulation time 21026819 ps
CPU time 0.61 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 194192 kb
Host smart-60bc66ec-8efc-4ec0-9ae2-7faacc08330c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743089733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1743089733
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1542134168
Short name T837
Test name
Test status
Simulation time 56294785 ps
CPU time 0.64 seconds
Started Jul 06 04:46:14 PM PDT 24
Finished Jul 06 04:46:15 PM PDT 24
Peak memory 194236 kb
Host smart-3d1b447c-ff1e-481d-94df-826dda0327de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542134168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1542134168
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2474476076
Short name T725
Test name
Test status
Simulation time 26063579 ps
CPU time 0.61 seconds
Started Jul 06 04:46:16 PM PDT 24
Finished Jul 06 04:46:17 PM PDT 24
Peak memory 194852 kb
Host smart-4002ddc5-cee5-424d-a173-d0a63334405d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474476076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2474476076
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2088835917
Short name T753
Test name
Test status
Simulation time 15621660 ps
CPU time 0.61 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:14 PM PDT 24
Peak memory 194292 kb
Host smart-5d02f5a2-147b-451f-9ce8-f7b87accef4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088835917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2088835917
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3999743324
Short name T722
Test name
Test status
Simulation time 56836971 ps
CPU time 0.63 seconds
Started Jul 06 04:46:11 PM PDT 24
Finished Jul 06 04:46:12 PM PDT 24
Peak memory 194912 kb
Host smart-d5868f6c-0708-451f-8237-3f7c7869dc5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999743324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3999743324
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.356001751
Short name T731
Test name
Test status
Simulation time 11636654 ps
CPU time 0.68 seconds
Started Jul 06 04:46:12 PM PDT 24
Finished Jul 06 04:46:13 PM PDT 24
Peak memory 194172 kb
Host smart-eda4f4e9-ad94-4a9f-9ecc-47c86543476d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356001751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.356001751
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3401751635
Short name T787
Test name
Test status
Simulation time 14237656 ps
CPU time 0.6 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 194192 kb
Host smart-59fddba3-827c-4820-8f72-0706d045eea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401751635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3401751635
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.234862147
Short name T86
Test name
Test status
Simulation time 13981946 ps
CPU time 0.75 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 196612 kb
Host smart-4dcd8878-b49d-4bd4-89cc-4540b9048df4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234862147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.234862147
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1745076806
Short name T777
Test name
Test status
Simulation time 875440540 ps
CPU time 3.21 seconds
Started Jul 06 04:45:56 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 198000 kb
Host smart-116fade8-1349-43e6-9ce4-934829b0331c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745076806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1745076806
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.893116328
Short name T774
Test name
Test status
Simulation time 25737563 ps
CPU time 0.64 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 195268 kb
Host smart-f3e3b6d3-f377-41a9-b6dc-3f8635a701ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893116328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.893116328
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2037645344
Short name T751
Test name
Test status
Simulation time 38338251 ps
CPU time 0.9 seconds
Started Jul 06 04:45:54 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 198504 kb
Host smart-801dfd95-21b6-4517-9e46-adc102e947dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037645344 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2037645344
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3265253652
Short name T809
Test name
Test status
Simulation time 26863297 ps
CPU time 0.62 seconds
Started Jul 06 04:45:54 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 195480 kb
Host smart-6e9c9f00-5234-45d7-bc56-7de5b91a12d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265253652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3265253652
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2734046298
Short name T786
Test name
Test status
Simulation time 47493093 ps
CPU time 0.58 seconds
Started Jul 06 04:45:54 PM PDT 24
Finished Jul 06 04:45:56 PM PDT 24
Peak memory 194272 kb
Host smart-79795bf3-60b6-461d-b22f-9279d421dc07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734046298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2734046298
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1416012551
Short name T95
Test name
Test status
Simulation time 42118107 ps
CPU time 0.86 seconds
Started Jul 06 04:45:53 PM PDT 24
Finished Jul 06 04:45:55 PM PDT 24
Peak memory 196832 kb
Host smart-2f5cbdff-323d-4fcc-a0a7-181921256d12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416012551 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1416012551
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3684072820
Short name T818
Test name
Test status
Simulation time 407247764 ps
CPU time 2.34 seconds
Started Jul 06 04:45:58 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 198592 kb
Host smart-35cc7987-64be-483a-8176-61c210504e15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684072820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3684072820
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3812749119
Short name T40
Test name
Test status
Simulation time 146051642 ps
CPU time 1.41 seconds
Started Jul 06 04:45:52 PM PDT 24
Finished Jul 06 04:45:54 PM PDT 24
Peak memory 198608 kb
Host smart-df67769a-1db8-4d61-b3d5-70cb092bba8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812749119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3812749119
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1832852246
Short name T730
Test name
Test status
Simulation time 63039512 ps
CPU time 0.6 seconds
Started Jul 06 04:46:21 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 194208 kb
Host smart-d379162b-44f0-4985-8e86-a96592901e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832852246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1832852246
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2487383970
Short name T724
Test name
Test status
Simulation time 21355936 ps
CPU time 0.61 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 194856 kb
Host smart-84cc1f1d-9321-4000-a5de-11eca09f96ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487383970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2487383970
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.589441469
Short name T841
Test name
Test status
Simulation time 29160343 ps
CPU time 0.62 seconds
Started Jul 06 04:46:16 PM PDT 24
Finished Jul 06 04:46:17 PM PDT 24
Peak memory 194268 kb
Host smart-3f8bcf8b-1b76-487c-9d54-a68c4006e56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589441469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.589441469
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3569696960
Short name T812
Test name
Test status
Simulation time 42586880 ps
CPU time 0.58 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:19 PM PDT 24
Peak memory 194324 kb
Host smart-ca3d9d28-4fd9-4cd7-83f1-d41111c47328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569696960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3569696960
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.145259667
Short name T827
Test name
Test status
Simulation time 98291175 ps
CPU time 0.6 seconds
Started Jul 06 04:46:22 PM PDT 24
Finished Jul 06 04:46:23 PM PDT 24
Peak memory 194856 kb
Host smart-520953c7-54e3-4458-a5bc-7fff795c0568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145259667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.145259667
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.853747771
Short name T721
Test name
Test status
Simulation time 13658760 ps
CPU time 0.58 seconds
Started Jul 06 04:46:27 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 194148 kb
Host smart-438c51b7-2b0a-406a-a676-f3c02bd1f667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853747771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.853747771
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4065641678
Short name T757
Test name
Test status
Simulation time 12962223 ps
CPU time 0.56 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 194224 kb
Host smart-65e24b6a-c5c4-4a81-8d6d-0f4e05ee5606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065641678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4065641678
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4064925076
Short name T840
Test name
Test status
Simulation time 128171932 ps
CPU time 0.59 seconds
Started Jul 06 04:46:26 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 194892 kb
Host smart-a04468bb-7d49-42b2-b0ed-163bc59bd118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064925076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4064925076
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3644493712
Short name T733
Test name
Test status
Simulation time 40784386 ps
CPU time 0.63 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 194416 kb
Host smart-17070321-0126-40b8-bf87-5ccaff0ed01a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644493712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3644493712
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.657560530
Short name T738
Test name
Test status
Simulation time 33999481 ps
CPU time 0.62 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 194216 kb
Host smart-501e2493-637f-47e4-9137-8a0bd49d811c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657560530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.657560530
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.200289640
Short name T89
Test name
Test status
Simulation time 116269480 ps
CPU time 0.84 seconds
Started Jul 06 04:46:02 PM PDT 24
Finished Jul 06 04:46:03 PM PDT 24
Peak memory 196660 kb
Host smart-55b3382a-6ccf-497f-ae6a-62d0c8465e46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200289640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.200289640
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.613294342
Short name T720
Test name
Test status
Simulation time 94417109 ps
CPU time 1.51 seconds
Started Jul 06 04:46:03 PM PDT 24
Finished Jul 06 04:46:05 PM PDT 24
Peak memory 197444 kb
Host smart-33adf4ae-721f-4da6-874b-fcb9bc1243b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613294342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.613294342
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1785164867
Short name T90
Test name
Test status
Simulation time 17001103 ps
CPU time 0.72 seconds
Started Jul 06 04:46:03 PM PDT 24
Finished Jul 06 04:46:04 PM PDT 24
Peak memory 195580 kb
Host smart-431838d8-241e-4b32-979a-858633064412
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785164867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1785164867
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1358960682
Short name T817
Test name
Test status
Simulation time 26321475 ps
CPU time 1.09 seconds
Started Jul 06 04:45:58 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 198492 kb
Host smart-48bcc9bb-cda9-4292-977e-dbde0b231da6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358960682 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1358960682
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1005834797
Short name T792
Test name
Test status
Simulation time 14678359 ps
CPU time 0.65 seconds
Started Jul 06 04:45:53 PM PDT 24
Finished Jul 06 04:45:55 PM PDT 24
Peak memory 195416 kb
Host smart-696cde9a-9642-4db0-888a-0acbd8b268d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005834797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1005834797
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3754307169
Short name T761
Test name
Test status
Simulation time 12096460 ps
CPU time 0.62 seconds
Started Jul 06 04:45:57 PM PDT 24
Finished Jul 06 04:45:58 PM PDT 24
Peak memory 194312 kb
Host smart-f669171e-1d7c-4d69-bca7-1992e853779b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754307169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3754307169
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.507882266
Short name T92
Test name
Test status
Simulation time 35644804 ps
CPU time 0.83 seconds
Started Jul 06 04:46:01 PM PDT 24
Finished Jul 06 04:46:02 PM PDT 24
Peak memory 196636 kb
Host smart-0dd5a7fc-0b61-4c28-9e8e-a78e76f67728
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507882266 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.507882266
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2805711589
Short name T836
Test name
Test status
Simulation time 2264651988 ps
CPU time 2.93 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:02 PM PDT 24
Peak memory 198632 kb
Host smart-282cc8b9-cd09-42ad-b93a-0f766256789e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805711589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2805711589
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1825008694
Short name T829
Test name
Test status
Simulation time 353214295 ps
CPU time 1.23 seconds
Started Jul 06 04:46:02 PM PDT 24
Finished Jul 06 04:46:04 PM PDT 24
Peak memory 198616 kb
Host smart-47c148c5-b4c2-4ddc-9c18-c8930af7a2d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825008694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1825008694
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.857005527
Short name T826
Test name
Test status
Simulation time 34828582 ps
CPU time 0.58 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:18 PM PDT 24
Peak memory 194196 kb
Host smart-c26d4840-8a1d-4843-a044-aea2fdbba4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857005527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.857005527
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2851246955
Short name T728
Test name
Test status
Simulation time 14208395 ps
CPU time 0.59 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 194200 kb
Host smart-b197c12a-f5e1-4603-aec7-ff9c0f0f2b22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851246955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2851246955
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2061723314
Short name T833
Test name
Test status
Simulation time 33722352 ps
CPU time 0.62 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 194216 kb
Host smart-b531639a-2372-4ca2-81fb-a1cdc906dd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061723314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2061723314
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2196546890
Short name T819
Test name
Test status
Simulation time 36955684 ps
CPU time 0.58 seconds
Started Jul 06 04:46:27 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 194132 kb
Host smart-70d3e3f1-b2e4-4eed-ba0b-6c49e4c9ca7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196546890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2196546890
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1493361228
Short name T794
Test name
Test status
Simulation time 38338243 ps
CPU time 0.6 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 194864 kb
Host smart-28733de0-f6d5-4248-b958-56ef3030c0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493361228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1493361228
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2958865257
Short name T839
Test name
Test status
Simulation time 15720275 ps
CPU time 0.61 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:18 PM PDT 24
Peak memory 194180 kb
Host smart-430bab7d-1ea8-4201-96a4-5ad4376f4bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958865257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2958865257
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.4025044990
Short name T729
Test name
Test status
Simulation time 34069518 ps
CPU time 0.6 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 194240 kb
Host smart-34b5604f-dd1f-452c-b753-61ce611b9946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025044990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.4025044990
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.374287395
Short name T762
Test name
Test status
Simulation time 14560168 ps
CPU time 0.62 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:19 PM PDT 24
Peak memory 194324 kb
Host smart-1e1f56fb-5b57-4040-aa5a-6844dbfc6c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374287395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.374287395
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.27647894
Short name T831
Test name
Test status
Simulation time 14602761 ps
CPU time 0.59 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 194292 kb
Host smart-8f7933d9-791b-44ad-b5c4-8bcf23332cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.27647894
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.611419362
Short name T791
Test name
Test status
Simulation time 14429262 ps
CPU time 0.63 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:19 PM PDT 24
Peak memory 194260 kb
Host smart-b16e02f1-4bd1-40cd-ac50-91548a9b02dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611419362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.611419362
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3219955901
Short name T719
Test name
Test status
Simulation time 40619211 ps
CPU time 1.05 seconds
Started Jul 06 04:46:02 PM PDT 24
Finished Jul 06 04:46:03 PM PDT 24
Peak memory 198492 kb
Host smart-a6999409-e8a9-4d31-a3c5-32702ef5994c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219955901 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3219955901
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.408151738
Short name T72
Test name
Test status
Simulation time 13366056 ps
CPU time 0.63 seconds
Started Jul 06 04:46:00 PM PDT 24
Finished Jul 06 04:46:01 PM PDT 24
Peak memory 196148 kb
Host smart-44fd272f-100c-4889-b5ba-aed9ce94472f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408151738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.408151738
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3035136353
Short name T741
Test name
Test status
Simulation time 23224618 ps
CPU time 0.61 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 194252 kb
Host smart-ff687dde-a821-42b7-99b7-8ad6c0221a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035136353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3035136353
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3116831459
Short name T96
Test name
Test status
Simulation time 166991689 ps
CPU time 0.84 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 196680 kb
Host smart-4a5dd0b7-9e6f-42c3-bdf7-23499766b3f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116831459 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3116831459
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2205072644
Short name T736
Test name
Test status
Simulation time 458723033 ps
CPU time 2.68 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:02 PM PDT 24
Peak memory 198536 kb
Host smart-c00399ea-6dbe-45e8-8f77-a7bb4e80fba2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205072644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2205072644
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3009907424
Short name T39
Test name
Test status
Simulation time 103990006 ps
CPU time 1.16 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 198612 kb
Host smart-f50b6f88-5b4f-4634-9e0a-c6bd8b8a5754
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009907424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3009907424
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.850856078
Short name T781
Test name
Test status
Simulation time 72711458 ps
CPU time 0.95 seconds
Started Jul 06 04:46:01 PM PDT 24
Finished Jul 06 04:46:02 PM PDT 24
Peak memory 198500 kb
Host smart-fe467a65-2819-4aea-a49c-5a14208ead68
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850856078 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.850856078
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3669911488
Short name T773
Test name
Test status
Simulation time 13670503 ps
CPU time 0.61 seconds
Started Jul 06 04:46:00 PM PDT 24
Finished Jul 06 04:46:01 PM PDT 24
Peak memory 195588 kb
Host smart-a9096d10-b467-4ee2-8e1e-6a852ac83d22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669911488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3669911488
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2047432609
Short name T808
Test name
Test status
Simulation time 21934258 ps
CPU time 0.6 seconds
Started Jul 06 04:46:03 PM PDT 24
Finished Jul 06 04:46:04 PM PDT 24
Peak memory 194208 kb
Host smart-29fe655c-d681-4b1a-86b1-afe70e6c3e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047432609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2047432609
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3831772096
Short name T71
Test name
Test status
Simulation time 180368055 ps
CPU time 0.82 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:01 PM PDT 24
Peak memory 197412 kb
Host smart-a7ba1f29-26c1-4807-8f63-1e63b01e3aa1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831772096 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3831772096
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1599621533
Short name T772
Test name
Test status
Simulation time 157123767 ps
CPU time 2.66 seconds
Started Jul 06 04:46:01 PM PDT 24
Finished Jul 06 04:46:04 PM PDT 24
Peak memory 198588 kb
Host smart-9dbdc788-9db5-4a5f-a067-85fa96d718ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599621533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1599621533
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3101074382
Short name T760
Test name
Test status
Simulation time 318074179 ps
CPU time 1.19 seconds
Started Jul 06 04:46:00 PM PDT 24
Finished Jul 06 04:46:01 PM PDT 24
Peak memory 198732 kb
Host smart-e49b5622-74df-4b2d-b074-57ed7b77b311
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101074382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3101074382
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3158824721
Short name T758
Test name
Test status
Simulation time 151502835 ps
CPU time 0.89 seconds
Started Jul 06 04:46:01 PM PDT 24
Finished Jul 06 04:46:03 PM PDT 24
Peak memory 198572 kb
Host smart-633f6d40-5420-4fb7-80a4-93928d51289f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158824721 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3158824721
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1999434919
Short name T101
Test name
Test status
Simulation time 14150235 ps
CPU time 0.61 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 195480 kb
Host smart-fa18ad85-08e7-486d-a9de-345de3a39919
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999434919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1999434919
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1165368150
Short name T815
Test name
Test status
Simulation time 18708579 ps
CPU time 0.66 seconds
Started Jul 06 04:45:57 PM PDT 24
Finished Jul 06 04:45:58 PM PDT 24
Peak memory 194280 kb
Host smart-c0edd36b-b916-4fdc-a10c-c26fb68a133d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165368150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1165368150
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1100842263
Short name T776
Test name
Test status
Simulation time 30347396 ps
CPU time 0.69 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:00 PM PDT 24
Peak memory 195416 kb
Host smart-fbdb3370-7cb7-44e6-aad2-6b2b86ddd933
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100842263 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1100842263
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2331602798
Short name T820
Test name
Test status
Simulation time 168835413 ps
CPU time 2.83 seconds
Started Jul 06 04:46:00 PM PDT 24
Finished Jul 06 04:46:03 PM PDT 24
Peak memory 198648 kb
Host smart-e56993c4-cb1d-467a-acc0-b5da4d247b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331602798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2331602798
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3188956587
Short name T104
Test name
Test status
Simulation time 102369743 ps
CPU time 1.46 seconds
Started Jul 06 04:45:59 PM PDT 24
Finished Jul 06 04:46:01 PM PDT 24
Peak memory 198588 kb
Host smart-4607cfcb-4a99-46ee-8e44-28fc5b69acf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188956587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3188956587
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2276948850
Short name T766
Test name
Test status
Simulation time 37359586 ps
CPU time 0.99 seconds
Started Jul 06 04:46:04 PM PDT 24
Finished Jul 06 04:46:05 PM PDT 24
Peak memory 198460 kb
Host smart-9ff784a6-d809-4af9-9fe4-3b6c48842c63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276948850 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2276948850
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2420553005
Short name T797
Test name
Test status
Simulation time 55692528 ps
CPU time 0.55 seconds
Started Jul 06 04:45:58 PM PDT 24
Finished Jul 06 04:45:58 PM PDT 24
Peak memory 193820 kb
Host smart-73dd0c66-7203-4fc8-9a96-91708216a416
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420553005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2420553005
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4289669756
Short name T748
Test name
Test status
Simulation time 57356053 ps
CPU time 0.61 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:06 PM PDT 24
Peak memory 194328 kb
Host smart-5c85aba2-1e10-478e-8c37-337cb7874948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289669756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4289669756
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1800276806
Short name T69
Test name
Test status
Simulation time 173469491 ps
CPU time 0.88 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:06 PM PDT 24
Peak memory 196912 kb
Host smart-862d4239-4b88-48d0-b766-423ba3dbdd09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800276806 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1800276806
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.719351178
Short name T778
Test name
Test status
Simulation time 42928871 ps
CPU time 2.3 seconds
Started Jul 06 04:46:07 PM PDT 24
Finished Jul 06 04:46:10 PM PDT 24
Peak memory 198608 kb
Host smart-2b7ae49b-6439-4a91-8bb7-bfdecff9aeac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719351178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.719351178
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2858691320
Short name T30
Test name
Test status
Simulation time 345109888 ps
CPU time 1.21 seconds
Started Jul 06 04:46:05 PM PDT 24
Finished Jul 06 04:46:07 PM PDT 24
Peak memory 198552 kb
Host smart-fff91951-0d2c-49e1-a012-b9fa9f8715b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858691320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2858691320
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.666775726
Short name T843
Test name
Test status
Simulation time 162285222 ps
CPU time 1.05 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:07 PM PDT 24
Peak memory 198500 kb
Host smart-7335f65b-50b2-4050-95ee-8bd791a01abe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666775726 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.666775726
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3192939012
Short name T99
Test name
Test status
Simulation time 13492980 ps
CPU time 0.63 seconds
Started Jul 06 04:46:04 PM PDT 24
Finished Jul 06 04:46:05 PM PDT 24
Peak memory 193824 kb
Host smart-a64abf0a-f12d-4755-b3e4-fd45f25938a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192939012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3192939012
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.642008675
Short name T789
Test name
Test status
Simulation time 30358692 ps
CPU time 0.62 seconds
Started Jul 06 04:46:07 PM PDT 24
Finished Jul 06 04:46:08 PM PDT 24
Peak memory 194928 kb
Host smart-79c596ce-b014-4425-85a2-4f31ba064a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642008675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.642008675
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2188581761
Short name T834
Test name
Test status
Simulation time 48227581 ps
CPU time 0.76 seconds
Started Jul 06 04:46:06 PM PDT 24
Finished Jul 06 04:46:07 PM PDT 24
Peak memory 196380 kb
Host smart-a16ed012-4c4d-4725-a09c-d0539692f358
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188581761 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2188581761
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.270589734
Short name T784
Test name
Test status
Simulation time 585630537 ps
CPU time 2.74 seconds
Started Jul 06 04:46:08 PM PDT 24
Finished Jul 06 04:46:11 PM PDT 24
Peak memory 198644 kb
Host smart-5b687b4f-9af9-4517-a975-1c09638a4bee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270589734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.270589734
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1692123476
Short name T41
Test name
Test status
Simulation time 255427251 ps
CPU time 1.24 seconds
Started Jul 06 04:46:07 PM PDT 24
Finished Jul 06 04:46:09 PM PDT 24
Peak memory 198208 kb
Host smart-8f8ce1b7-f5a7-4666-bec8-e5aa06a5d016
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692123476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1692123476
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3676588351
Short name T36
Test name
Test status
Simulation time 39434813 ps
CPU time 0.58 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 193396 kb
Host smart-078f0c70-624c-440f-8813-b0a99bf5300f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676588351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3676588351
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1125507838
Short name T439
Test name
Test status
Simulation time 38809496 ps
CPU time 0.66 seconds
Started Jul 06 04:48:54 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 195376 kb
Host smart-f74d2806-0b3d-409c-a062-5feba39b961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125507838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1125507838
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1447726309
Short name T173
Test name
Test status
Simulation time 985378650 ps
CPU time 28.62 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 197492 kb
Host smart-90abcac7-e1b2-4b09-aa91-5aa4b336c17b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447726309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1447726309
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2928493617
Short name T305
Test name
Test status
Simulation time 37010297 ps
CPU time 0.64 seconds
Started Jul 06 04:48:46 PM PDT 24
Finished Jul 06 04:48:47 PM PDT 24
Peak memory 195088 kb
Host smart-4995b07a-6f59-4d5a-8066-68356f0c2291
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928493617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2928493617
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3243503019
Short name T553
Test name
Test status
Simulation time 93156585 ps
CPU time 1.29 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 196792 kb
Host smart-5c7d0743-5d71-48b0-994a-824a25188de8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243503019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3243503019
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1969863038
Short name T423
Test name
Test status
Simulation time 83899583 ps
CPU time 3.37 seconds
Started Jul 06 04:48:56 PM PDT 24
Finished Jul 06 04:49:00 PM PDT 24
Peak memory 198648 kb
Host smart-a05a8fe6-5c89-4693-84f7-a1fb0104747c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969863038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1969863038
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2947651492
Short name T664
Test name
Test status
Simulation time 525309412 ps
CPU time 1.52 seconds
Started Jul 06 04:49:02 PM PDT 24
Finished Jul 06 04:49:04 PM PDT 24
Peak memory 196448 kb
Host smart-80987880-aca8-4e3c-8963-7086f29f06c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947651492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2947651492
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3813626528
Short name T616
Test name
Test status
Simulation time 110828705 ps
CPU time 0.86 seconds
Started Jul 06 04:48:50 PM PDT 24
Finished Jul 06 04:48:51 PM PDT 24
Peak memory 197172 kb
Host smart-998b4422-c16b-46d4-9c6e-08817610f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813626528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3813626528
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3968309073
Short name T161
Test name
Test status
Simulation time 336246927 ps
CPU time 0.91 seconds
Started Jul 06 04:49:01 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 196692 kb
Host smart-77bba089-515d-4dab-923c-42531b7545f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968309073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3968309073
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.810885711
Short name T685
Test name
Test status
Simulation time 30279838 ps
CPU time 1.34 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 198544 kb
Host smart-b935b6c6-bc97-44d7-ba5d-aafa39991d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810885711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.810885711
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2962531426
Short name T43
Test name
Test status
Simulation time 60739162 ps
CPU time 0.8 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:50 PM PDT 24
Peak memory 214212 kb
Host smart-e5eb93d2-ba1e-4552-ad45-3b1c4c1d8a78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962531426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2962531426
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.388277006
Short name T142
Test name
Test status
Simulation time 75389345 ps
CPU time 1.25 seconds
Started Jul 06 04:48:54 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 196488 kb
Host smart-49096fdb-07f4-4246-8f4b-e44f0bbaf5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388277006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.388277006
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.787120774
Short name T199
Test name
Test status
Simulation time 65408282 ps
CPU time 1.17 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:09 PM PDT 24
Peak memory 196380 kb
Host smart-59de650b-9e36-4f41-8f5a-6c2f80a58665
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787120774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.787120774
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.16195355
Short name T556
Test name
Test status
Simulation time 2860783089 ps
CPU time 67.75 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 198716 kb
Host smart-6bf8b060-ba2c-4cd8-84f4-5e4f23504c75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16195355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpi
o_stress_all.16195355
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.4223268173
Short name T55
Test name
Test status
Simulation time 119008399711 ps
CPU time 943.77 seconds
Started Jul 06 04:48:46 PM PDT 24
Finished Jul 06 05:04:31 PM PDT 24
Peak memory 198856 kb
Host smart-ec798363-2070-4665-8e46-a209528f1b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4223268173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.4223268173
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.40042516
Short name T285
Test name
Test status
Simulation time 18337315 ps
CPU time 0.62 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 194780 kb
Host smart-590f0d24-eef3-4418-9171-f612c16ae183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40042516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.40042516
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3191493947
Short name T150
Test name
Test status
Simulation time 45286095 ps
CPU time 0.63 seconds
Started Jul 06 04:48:48 PM PDT 24
Finished Jul 06 04:48:50 PM PDT 24
Peak memory 194620 kb
Host smart-28c63382-3559-436b-8f97-013f710ebe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191493947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3191493947
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.96307536
Short name T508
Test name
Test status
Simulation time 510059432 ps
CPU time 6.18 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:49:19 PM PDT 24
Peak memory 197636 kb
Host smart-cf1ef5e5-4369-4d67-9ba9-52dedb88e831
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96307536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.96307536
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.263047425
Short name T24
Test name
Test status
Simulation time 280465546 ps
CPU time 0.98 seconds
Started Jul 06 04:48:58 PM PDT 24
Finished Jul 06 04:48:59 PM PDT 24
Peak memory 197116 kb
Host smart-9a0c96ad-c417-43d3-a94a-0cfa138d3574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263047425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.263047425
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.883596127
Short name T469
Test name
Test status
Simulation time 33066904 ps
CPU time 0.99 seconds
Started Jul 06 04:49:17 PM PDT 24
Finished Jul 06 04:49:19 PM PDT 24
Peak memory 196588 kb
Host smart-edf839c1-c28f-4c9f-bd5e-6ca4690ddfc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883596127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.883596127
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2651407595
Short name T110
Test name
Test status
Simulation time 182229873 ps
CPU time 3.48 seconds
Started Jul 06 04:49:05 PM PDT 24
Finished Jul 06 04:49:09 PM PDT 24
Peak memory 198672 kb
Host smart-9ee8e770-0e77-4f27-ae6d-5e96f14bb3b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651407595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2651407595
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1634720801
Short name T217
Test name
Test status
Simulation time 159521094 ps
CPU time 2.42 seconds
Started Jul 06 04:48:57 PM PDT 24
Finished Jul 06 04:49:00 PM PDT 24
Peak memory 197572 kb
Host smart-e5b0bfaf-1643-459e-9109-e98069ffae62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634720801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1634720801
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3677202082
Short name T441
Test name
Test status
Simulation time 157098717 ps
CPU time 1.26 seconds
Started Jul 06 04:48:45 PM PDT 24
Finished Jul 06 04:48:46 PM PDT 24
Peak memory 198636 kb
Host smart-2ff40a3b-01f5-4b03-a35f-b64585bc712e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677202082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3677202082
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1303357294
Short name T511
Test name
Test status
Simulation time 57417960 ps
CPU time 0.8 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 196152 kb
Host smart-7431e34e-72a2-4607-8004-e6b7ac284fc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303357294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1303357294
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3579821794
Short name T435
Test name
Test status
Simulation time 1425930624 ps
CPU time 5.1 seconds
Started Jul 06 04:49:04 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 198564 kb
Host smart-8ef6d68c-6820-4f5f-a64c-365a24ce939a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579821794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3579821794
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3870754393
Short name T44
Test name
Test status
Simulation time 118627845 ps
CPU time 0.98 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 215264 kb
Host smart-33ed6b04-061e-4efc-b74d-24bbc336ad2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870754393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3870754393
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1063345061
Short name T536
Test name
Test status
Simulation time 161139460 ps
CPU time 1.24 seconds
Started Jul 06 04:48:47 PM PDT 24
Finished Jul 06 04:48:49 PM PDT 24
Peak memory 197176 kb
Host smart-49bd9ac8-d56b-4bf8-bd62-9563f468dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063345061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1063345061
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2985771908
Short name T427
Test name
Test status
Simulation time 221974930 ps
CPU time 1.2 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 196844 kb
Host smart-81b52f63-9e91-430c-9029-12cfe5fdbe90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985771908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2985771908
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2312002709
Short name T215
Test name
Test status
Simulation time 81410187138 ps
CPU time 202.85 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:52:15 PM PDT 24
Peak memory 198708 kb
Host smart-abafa94d-b119-40ff-9eaa-605b7f08787d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312002709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2312002709
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3061874015
Short name T540
Test name
Test status
Simulation time 12425618 ps
CPU time 0.6 seconds
Started Jul 06 04:49:18 PM PDT 24
Finished Jul 06 04:49:19 PM PDT 24
Peak memory 194576 kb
Host smart-629892ad-d86f-4a29-a640-a06e6ced9b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061874015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3061874015
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3913021718
Short name T221
Test name
Test status
Simulation time 54523498 ps
CPU time 0.66 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 194752 kb
Host smart-ccf43d85-f0b8-4bab-b6ea-5f4b5bd73466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913021718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3913021718
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2433874994
Short name T286
Test name
Test status
Simulation time 1982294077 ps
CPU time 26.58 seconds
Started Jul 06 04:49:29 PM PDT 24
Finished Jul 06 04:49:56 PM PDT 24
Peak memory 198592 kb
Host smart-731b8411-5ef0-466b-a664-320054b38264
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433874994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2433874994
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2178188908
Short name T546
Test name
Test status
Simulation time 45934833 ps
CPU time 0.79 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:14 PM PDT 24
Peak memory 196344 kb
Host smart-c5ed5440-491d-4fa6-b66a-fdc30bc45068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178188908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2178188908
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1810398018
Short name T176
Test name
Test status
Simulation time 178997447 ps
CPU time 1.31 seconds
Started Jul 06 04:49:27 PM PDT 24
Finished Jul 06 04:49:28 PM PDT 24
Peak memory 197728 kb
Host smart-fd640d81-5a0e-41b2-b760-60bcccd774c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810398018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1810398018
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3223255053
Short name T47
Test name
Test status
Simulation time 110559343 ps
CPU time 2.3 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 198672 kb
Host smart-1e555655-46dd-4eb3-8409-d947be7938c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223255053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3223255053
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3770239819
Short name T424
Test name
Test status
Simulation time 435937258 ps
CPU time 2.62 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:18 PM PDT 24
Peak memory 197356 kb
Host smart-a837f8a0-6d44-4956-96d4-61aec1b1f7e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770239819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3770239819
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.102612361
Short name T361
Test name
Test status
Simulation time 151314251 ps
CPU time 0.82 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 197812 kb
Host smart-c6cf2ce9-1267-4f4b-8aa1-38d8d095fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102612361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.102612361
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3797630776
Short name T229
Test name
Test status
Simulation time 87783633 ps
CPU time 0.74 seconds
Started Jul 06 04:49:05 PM PDT 24
Finished Jul 06 04:49:07 PM PDT 24
Peak memory 195964 kb
Host smart-8d18ecaa-83ef-43fe-893c-fcc906c92cf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797630776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3797630776
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3579450251
Short name T311
Test name
Test status
Simulation time 384054024 ps
CPU time 5.99 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:20 PM PDT 24
Peak memory 198720 kb
Host smart-bbecf30a-1200-4758-aa68-13e76e455501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579450251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3579450251
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3209442020
Short name T654
Test name
Test status
Simulation time 42682626 ps
CPU time 0.94 seconds
Started Jul 06 04:49:11 PM PDT 24
Finished Jul 06 04:49:17 PM PDT 24
Peak memory 197220 kb
Host smart-afd8aa22-01c5-4c8b-af5b-8ac206f4d09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209442020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3209442020
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4195330772
Short name T412
Test name
Test status
Simulation time 44062231 ps
CPU time 1.27 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 196300 kb
Host smart-a6cf6414-203e-4536-8823-51f95fcaa46b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195330772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4195330772
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1408854559
Short name T294
Test name
Test status
Simulation time 8058643914 ps
CPU time 227.05 seconds
Started Jul 06 04:49:14 PM PDT 24
Finished Jul 06 04:53:01 PM PDT 24
Peak memory 198700 kb
Host smart-8b269ec5-9513-4e13-9a00-c4b4d2acb5dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408854559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1408854559
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.709056408
Short name T324
Test name
Test status
Simulation time 13212627 ps
CPU time 0.58 seconds
Started Jul 06 04:49:25 PM PDT 24
Finished Jul 06 04:49:26 PM PDT 24
Peak memory 194772 kb
Host smart-d3b25b54-aa23-461b-b5d2-7b9219c9b3fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709056408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.709056408
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3093594683
Short name T604
Test name
Test status
Simulation time 46922685 ps
CPU time 0.92 seconds
Started Jul 06 04:49:11 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 197184 kb
Host smart-57236ea1-d821-4273-b7a6-90c51e0a9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093594683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3093594683
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.4272731941
Short name T122
Test name
Test status
Simulation time 477486371 ps
CPU time 8.27 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:32 PM PDT 24
Peak memory 197532 kb
Host smart-fc5a1613-0a03-4540-9cb5-cb879ccb2ec9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272731941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.4272731941
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3236632673
Short name T471
Test name
Test status
Simulation time 56515022 ps
CPU time 1.03 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 197196 kb
Host smart-65df0537-5aef-471b-b8e6-bce906ed352a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236632673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3236632673
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3637187579
Short name T377
Test name
Test status
Simulation time 84791853 ps
CPU time 0.94 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:17 PM PDT 24
Peak memory 197392 kb
Host smart-76c70b73-031d-40d2-8c57-05565d192e6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637187579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3637187579
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2667358490
Short name T642
Test name
Test status
Simulation time 74796674 ps
CPU time 3 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 198696 kb
Host smart-0d11e09f-c603-4dcd-a8db-fbd6943917af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667358490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2667358490
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2409461763
Short name T204
Test name
Test status
Simulation time 488776945 ps
CPU time 2.22 seconds
Started Jul 06 04:49:21 PM PDT 24
Finished Jul 06 04:49:23 PM PDT 24
Peak memory 198744 kb
Host smart-bf085558-236c-481e-bbff-084959029188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409461763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2409461763
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2430138077
Short name T349
Test name
Test status
Simulation time 42786723 ps
CPU time 0.67 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 195568 kb
Host smart-ead1a7c1-9d70-4dcb-b897-aea9e29e0ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430138077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2430138077
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.4214829516
Short name T694
Test name
Test status
Simulation time 24048096 ps
CPU time 0.87 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 196784 kb
Host smart-be958f41-fa92-4fd6-93b9-db4dc8a26c96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214829516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.4214829516
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.689356888
Short name T535
Test name
Test status
Simulation time 2637328020 ps
CPU time 7.05 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 198656 kb
Host smart-0f1eab28-77ad-4d67-96ec-e6210d2d7859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689356888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.689356888
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3065199319
Short name T383
Test name
Test status
Simulation time 83068621 ps
CPU time 1.43 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 198620 kb
Host smart-eebdfdb5-a54d-4801-9531-2fb8ee2783ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065199319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3065199319
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2472652725
Short name T370
Test name
Test status
Simulation time 18384949 ps
CPU time 0.77 seconds
Started Jul 06 04:49:17 PM PDT 24
Finished Jul 06 04:49:18 PM PDT 24
Peak memory 195808 kb
Host smart-c6028366-7c35-4e3a-a9b5-f016d7227eda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472652725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2472652725
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3338252765
Short name T210
Test name
Test status
Simulation time 5989519841 ps
CPU time 151.72 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 198708 kb
Host smart-2885d747-4086-4414-bdbe-555184bca909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338252765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3338252765
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.254308261
Short name T652
Test name
Test status
Simulation time 42136864 ps
CPU time 0.56 seconds
Started Jul 06 04:49:20 PM PDT 24
Finished Jul 06 04:49:21 PM PDT 24
Peak memory 194580 kb
Host smart-20a99214-dd4f-4fcf-b23a-3f55fea6691b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254308261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.254308261
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3184818100
Short name T491
Test name
Test status
Simulation time 152582033 ps
CPU time 0.88 seconds
Started Jul 06 04:49:18 PM PDT 24
Finished Jul 06 04:49:20 PM PDT 24
Peak memory 196396 kb
Host smart-601e544f-b52b-46e6-8ffb-90bf58c0842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184818100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3184818100
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3070838893
Short name T385
Test name
Test status
Simulation time 625262591 ps
CPU time 7.88 seconds
Started Jul 06 04:49:20 PM PDT 24
Finished Jul 06 04:49:28 PM PDT 24
Peak memory 197148 kb
Host smart-7c551ea2-1998-4600-9a7e-af7895618dfd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070838893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3070838893
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2245207884
Short name T709
Test name
Test status
Simulation time 127998123 ps
CPU time 0.76 seconds
Started Jul 06 04:49:39 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 197060 kb
Host smart-34b08ed8-9198-4329-87a6-23b0171b07e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245207884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2245207884
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.229356666
Short name T171
Test name
Test status
Simulation time 81228327 ps
CPU time 0.94 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 196620 kb
Host smart-178d9873-eb0f-46dc-9b38-0ef3d9c6eaf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229356666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.229356666
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1190491326
Short name T336
Test name
Test status
Simulation time 387046308 ps
CPU time 3.56 seconds
Started Jul 06 04:49:27 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 198596 kb
Host smart-34105394-7022-445a-b2d6-172ea83a25aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190491326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1190491326
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.119226905
Short name T459
Test name
Test status
Simulation time 661553654 ps
CPU time 3.4 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:17 PM PDT 24
Peak memory 197584 kb
Host smart-18be183a-7ad3-41f4-83c4-e3719bef93f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119226905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
119226905
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3830351532
Short name T182
Test name
Test status
Simulation time 124791001 ps
CPU time 1.17 seconds
Started Jul 06 04:49:25 PM PDT 24
Finished Jul 06 04:49:26 PM PDT 24
Peak memory 197504 kb
Host smart-741ed2aa-b1d4-44c5-b093-1e827c64e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830351532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3830351532
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3032586515
Short name T288
Test name
Test status
Simulation time 131478114 ps
CPU time 1.32 seconds
Started Jul 06 04:49:27 PM PDT 24
Finished Jul 06 04:49:29 PM PDT 24
Peak memory 197740 kb
Host smart-6e6cb96d-a23b-4b96-bc77-791cd61f4145
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032586515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3032586515
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1762620934
Short name T683
Test name
Test status
Simulation time 714479890 ps
CPU time 3.3 seconds
Started Jul 06 04:49:26 PM PDT 24
Finished Jul 06 04:49:30 PM PDT 24
Peak memory 198596 kb
Host smart-909f52e9-630b-47bc-a4ef-0269e1362743
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762620934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1762620934
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1598422654
Short name T64
Test name
Test status
Simulation time 448037730 ps
CPU time 1.25 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 196228 kb
Host smart-42cb5fbb-6bc1-4c04-ab14-2dfea9121860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598422654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1598422654
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2344104853
Short name T15
Test name
Test status
Simulation time 40753528 ps
CPU time 0.85 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:35 PM PDT 24
Peak memory 196076 kb
Host smart-8629d311-9944-434b-bcd4-30afdb4bb7ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344104853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2344104853
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2347624081
Short name T7
Test name
Test status
Simulation time 6823055673 ps
CPU time 78.73 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:50:29 PM PDT 24
Peak memory 198672 kb
Host smart-61dfe9bf-04d6-4d4e-a366-2aab5acdec41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347624081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2347624081
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.413885291
Short name T429
Test name
Test status
Simulation time 50795070823 ps
CPU time 1046.84 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 05:06:50 PM PDT 24
Peak memory 198856 kb
Host smart-feaad175-439c-460a-b4ac-b720218d8bab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=413885291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.413885291
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2814852974
Short name T315
Test name
Test status
Simulation time 23647205 ps
CPU time 0.61 seconds
Started Jul 06 04:49:32 PM PDT 24
Finished Jul 06 04:49:33 PM PDT 24
Peak memory 194580 kb
Host smart-a1c5cfee-230a-4415-afa6-6b1d026892fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814852974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2814852974
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1046458107
Short name T306
Test name
Test status
Simulation time 42668168 ps
CPU time 0.79 seconds
Started Jul 06 04:49:31 PM PDT 24
Finished Jul 06 04:49:32 PM PDT 24
Peak memory 196036 kb
Host smart-31cbb649-7cc8-4b20-87d1-ad0f230a1216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046458107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1046458107
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3689262511
Short name T529
Test name
Test status
Simulation time 269755485 ps
CPU time 12.98 seconds
Started Jul 06 04:49:17 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 196212 kb
Host smart-1168dc04-6f9b-45fc-9350-d86b9eaf2b9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689262511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3689262511
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.4087975832
Short name T220
Test name
Test status
Simulation time 25115771 ps
CPU time 0.69 seconds
Started Jul 06 04:49:24 PM PDT 24
Finished Jul 06 04:49:25 PM PDT 24
Peak memory 195052 kb
Host smart-84c51e9a-f27a-439c-a471-954fe83ca4b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087975832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.4087975832
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2720553315
Short name T338
Test name
Test status
Simulation time 321117169 ps
CPU time 1.3 seconds
Started Jul 06 04:49:39 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 197704 kb
Host smart-2a751a29-405d-4980-afa1-2a98766ce8b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720553315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2720553315
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3085558021
Short name T547
Test name
Test status
Simulation time 113179423 ps
CPU time 2.36 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 196932 kb
Host smart-8dd8c304-4b9d-425f-a4a1-463104b8e7f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085558021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3085558021
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2269260795
Short name T670
Test name
Test status
Simulation time 55090819 ps
CPU time 1.3 seconds
Started Jul 06 04:49:20 PM PDT 24
Finished Jul 06 04:49:21 PM PDT 24
Peak memory 197252 kb
Host smart-9eb801dd-c19b-405d-ae9f-e2716bac6ce2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269260795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2269260795
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2700281654
Short name T606
Test name
Test status
Simulation time 30942263 ps
CPU time 1.14 seconds
Started Jul 06 04:49:22 PM PDT 24
Finished Jul 06 04:49:23 PM PDT 24
Peak memory 197140 kb
Host smart-430d3746-9253-4f0a-b8d6-18080e97b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700281654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2700281654
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3582785355
Short name T607
Test name
Test status
Simulation time 88526493 ps
CPU time 1.02 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:37 PM PDT 24
Peak memory 196536 kb
Host smart-a7293e7f-4d00-4675-95c8-503677123984
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582785355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3582785355
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4209200947
Short name T125
Test name
Test status
Simulation time 1439440202 ps
CPU time 3.27 seconds
Started Jul 06 04:49:17 PM PDT 24
Finished Jul 06 04:49:21 PM PDT 24
Peak memory 198616 kb
Host smart-e88d06cf-6bbb-47ea-9af6-9fe2be71490c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209200947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4209200947
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2809495712
Short name T18
Test name
Test status
Simulation time 156191718 ps
CPU time 0.91 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:49:13 PM PDT 24
Peak memory 196176 kb
Host smart-94af5411-2db7-42e8-a631-b3327e833960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809495712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2809495712
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.427260622
Short name T138
Test name
Test status
Simulation time 84543631 ps
CPU time 1.02 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 197900 kb
Host smart-b91d74d7-6faf-4fb1-936f-3c234aaf2844
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427260622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.427260622
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.262791877
Short name T609
Test name
Test status
Simulation time 71409481824 ps
CPU time 174 seconds
Started Jul 06 04:49:20 PM PDT 24
Finished Jul 06 04:52:14 PM PDT 24
Peak memory 198792 kb
Host smart-30e4deec-8730-4eaa-825b-5e447e2b8a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262791877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.262791877
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2529455715
Short name T65
Test name
Test status
Simulation time 123809042577 ps
CPU time 2513.03 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 05:31:32 PM PDT 24
Peak memory 198872 kb
Host smart-81108ed0-9826-4de9-bade-1dfd91b893bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2529455715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2529455715
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3790329409
Short name T445
Test name
Test status
Simulation time 26331134 ps
CPU time 0.6 seconds
Started Jul 06 04:49:43 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 195472 kb
Host smart-c89ed2c4-1f73-45b5-a8ae-71c57c82230f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790329409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3790329409
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.984483748
Short name T136
Test name
Test status
Simulation time 28569607 ps
CPU time 0.82 seconds
Started Jul 06 04:49:16 PM PDT 24
Finished Jul 06 04:49:17 PM PDT 24
Peak memory 195868 kb
Host smart-6ee84463-4633-4f64-80ef-db9209633ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984483748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.984483748
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2340348112
Short name T115
Test name
Test status
Simulation time 5735946736 ps
CPU time 25.16 seconds
Started Jul 06 04:49:30 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 197620 kb
Host smart-d636d7f1-a8cc-4a3c-bb3a-429b7123d781
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340348112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2340348112
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1509179580
Short name T615
Test name
Test status
Simulation time 31997986 ps
CPU time 0.73 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 195096 kb
Host smart-4be1c187-d494-4a0d-9a7a-c3de4bd3749c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509179580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1509179580
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1612458987
Short name T214
Test name
Test status
Simulation time 174225389 ps
CPU time 1.35 seconds
Started Jul 06 04:49:26 PM PDT 24
Finished Jul 06 04:49:28 PM PDT 24
Peak memory 197788 kb
Host smart-888edba9-ece9-4654-9241-b8ff2b2d5fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612458987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1612458987
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3944270712
Short name T189
Test name
Test status
Simulation time 85999420 ps
CPU time 3.16 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 198672 kb
Host smart-61645615-43f9-4e6a-9e92-11ca2b704c58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944270712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3944270712
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1750092809
Short name T674
Test name
Test status
Simulation time 314611816 ps
CPU time 2.46 seconds
Started Jul 06 04:49:29 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 197092 kb
Host smart-ecbbb419-9cab-4ad4-81be-7ece36f31259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750092809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1750092809
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2515251035
Short name T301
Test name
Test status
Simulation time 375195657 ps
CPU time 1.11 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:49:47 PM PDT 24
Peak memory 197372 kb
Host smart-b83c4aa8-c0f5-4316-bbb4-d0d818248e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515251035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2515251035
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2921423461
Short name T352
Test name
Test status
Simulation time 20977764 ps
CPU time 0.85 seconds
Started Jul 06 04:49:17 PM PDT 24
Finished Jul 06 04:49:19 PM PDT 24
Peak memory 197020 kb
Host smart-4082be5d-e6ad-492c-8282-e63f2232299e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921423461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2921423461
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.759191348
Short name T387
Test name
Test status
Simulation time 1499643719 ps
CPU time 5.82 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:22 PM PDT 24
Peak memory 198544 kb
Host smart-53d4fc9c-e772-44ba-8f84-f88b67a5c627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759191348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.759191348
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2743141625
Short name T226
Test name
Test status
Simulation time 50959911 ps
CPU time 1.05 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 196396 kb
Host smart-2b52ffa8-1463-46e8-80f4-beefdbbd03c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743141625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2743141625
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2681413891
Short name T153
Test name
Test status
Simulation time 43683830 ps
CPU time 1.04 seconds
Started Jul 06 04:49:21 PM PDT 24
Finished Jul 06 04:49:23 PM PDT 24
Peak memory 196420 kb
Host smart-72cad876-cdac-4c28-b47b-f30fb0ccb395
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681413891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2681413891
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.739006320
Short name T629
Test name
Test status
Simulation time 68647954358 ps
CPU time 196.38 seconds
Started Jul 06 04:49:32 PM PDT 24
Finished Jul 06 04:52:49 PM PDT 24
Peak memory 198700 kb
Host smart-6306bc2a-4ec5-49d2-84ca-3105b150a1ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739006320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.739006320
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1624718264
Short name T293
Test name
Test status
Simulation time 19500218 ps
CPU time 0.58 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 195372 kb
Host smart-440199bd-b269-44d5-bd33-f77b7eb1629c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624718264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1624718264
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1286979283
Short name T684
Test name
Test status
Simulation time 41166302 ps
CPU time 0.73 seconds
Started Jul 06 04:49:33 PM PDT 24
Finished Jul 06 04:49:34 PM PDT 24
Peak memory 195720 kb
Host smart-2e0c6d44-aca8-4ef1-bf01-552a52d141e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286979283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1286979283
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3092129879
Short name T542
Test name
Test status
Simulation time 284186313 ps
CPU time 9.9 seconds
Started Jul 06 04:49:22 PM PDT 24
Finished Jul 06 04:49:32 PM PDT 24
Peak memory 197260 kb
Host smart-ffecf75c-81bb-44c0-a6cb-f27fc1ae0d1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092129879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3092129879
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.834022873
Short name T532
Test name
Test status
Simulation time 62132479 ps
CPU time 0.98 seconds
Started Jul 06 04:49:32 PM PDT 24
Finished Jul 06 04:49:33 PM PDT 24
Peak memory 198636 kb
Host smart-60b97434-55d6-40dc-b50c-4d94ed77ec27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834022873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.834022873
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1169752946
Short name T193
Test name
Test status
Simulation time 148156934 ps
CPU time 1.15 seconds
Started Jul 06 04:49:19 PM PDT 24
Finished Jul 06 04:49:20 PM PDT 24
Peak memory 196752 kb
Host smart-02706c55-0b5a-4267-86e7-5cdd69b333b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169752946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1169752946
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3146768427
Short name T617
Test name
Test status
Simulation time 156985934 ps
CPU time 1.65 seconds
Started Jul 06 04:49:28 PM PDT 24
Finished Jul 06 04:49:30 PM PDT 24
Peak memory 197456 kb
Host smart-2a806279-8d5a-43db-81ec-d6872a33a465
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146768427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3146768427
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1750675820
Short name T449
Test name
Test status
Simulation time 37599504 ps
CPU time 0.97 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 196156 kb
Host smart-2ec73be5-eaf9-40c0-9329-3a05a013a158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750675820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1750675820
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.484702502
Short name T497
Test name
Test status
Simulation time 44235176 ps
CPU time 0.67 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:35 PM PDT 24
Peak memory 194860 kb
Host smart-56e07668-1a05-484a-bf5d-ed351443c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484702502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.484702502
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1121503159
Short name T266
Test name
Test status
Simulation time 36299947 ps
CPU time 0.6 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 195464 kb
Host smart-2c909814-5988-49de-9af7-7693f4e5af07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121503159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1121503159
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2700354727
Short name T516
Test name
Test status
Simulation time 2273336307 ps
CPU time 6.48 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 198720 kb
Host smart-edad9ab6-8571-4237-9358-b5dc2706e8c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700354727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2700354727
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2048627002
Short name T414
Test name
Test status
Simulation time 146406404 ps
CPU time 0.92 seconds
Started Jul 06 04:49:24 PM PDT 24
Finished Jul 06 04:49:25 PM PDT 24
Peak memory 196056 kb
Host smart-742b3f91-8d95-4691-a22c-ecd6d3fb2e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048627002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2048627002
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2855973952
Short name T558
Test name
Test status
Simulation time 372494126 ps
CPU time 1.17 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 197180 kb
Host smart-9eb4fcbe-d83e-4740-8e1a-d320bafb9239
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855973952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2855973952
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1243120326
Short name T334
Test name
Test status
Simulation time 13816803826 ps
CPU time 197.73 seconds
Started Jul 06 04:49:24 PM PDT 24
Finished Jul 06 04:52:42 PM PDT 24
Peak memory 198828 kb
Host smart-9bc2a286-e62d-4686-a1ef-854a3e66f86a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243120326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1243120326
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.924220235
Short name T448
Test name
Test status
Simulation time 31065894 ps
CPU time 0.61 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:36 PM PDT 24
Peak memory 195432 kb
Host smart-d0079724-90d5-4214-b5a8-cff135ba25ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924220235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.924220235
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.37481238
Short name T651
Test name
Test status
Simulation time 123864707 ps
CPU time 0.84 seconds
Started Jul 06 04:49:26 PM PDT 24
Finished Jul 06 04:49:27 PM PDT 24
Peak memory 196696 kb
Host smart-c27f6e8a-4f2c-425f-aa3c-ad5f77ced4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37481238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.37481238
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3856888780
Short name T240
Test name
Test status
Simulation time 892977354 ps
CPU time 7.76 seconds
Started Jul 06 04:49:19 PM PDT 24
Finished Jul 06 04:49:28 PM PDT 24
Peak memory 198660 kb
Host smart-83c0c72c-76e2-487d-91db-cf876e4efb74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856888780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3856888780
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3983492059
Short name T647
Test name
Test status
Simulation time 72848225 ps
CPU time 0.59 seconds
Started Jul 06 04:49:27 PM PDT 24
Finished Jul 06 04:49:28 PM PDT 24
Peak memory 195464 kb
Host smart-f3fe5d68-e921-43f8-b7af-4f9ec0924d7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983492059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3983492059
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3556186160
Short name T318
Test name
Test status
Simulation time 120944149 ps
CPU time 1.19 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:25 PM PDT 24
Peak memory 197000 kb
Host smart-1fa298e3-ffc2-4649-973b-6b2001fe593a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556186160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3556186160
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1875567836
Short name T440
Test name
Test status
Simulation time 149693940 ps
CPU time 3.25 seconds
Started Jul 06 04:49:26 PM PDT 24
Finished Jul 06 04:49:29 PM PDT 24
Peak memory 198656 kb
Host smart-d931b3c8-b233-4e75-8710-88cad7bc7923
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875567836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1875567836
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.375649007
Short name T527
Test name
Test status
Simulation time 163648071 ps
CPU time 2.63 seconds
Started Jul 06 04:49:25 PM PDT 24
Finished Jul 06 04:49:27 PM PDT 24
Peak memory 197940 kb
Host smart-290daa9d-863a-4e0e-80ea-08e8b9113dce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375649007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
375649007
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3640362460
Short name T133
Test name
Test status
Simulation time 274890150 ps
CPU time 1.21 seconds
Started Jul 06 04:49:17 PM PDT 24
Finished Jul 06 04:49:19 PM PDT 24
Peak memory 197168 kb
Host smart-280c1711-4f57-4a7d-a0d3-c9b391b55bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640362460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3640362460
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3070180166
Short name T126
Test name
Test status
Simulation time 67032768 ps
CPU time 1.24 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 198600 kb
Host smart-fb8e765b-644c-4b71-963a-7ea72ee47273
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070180166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3070180166
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2911635981
Short name T82
Test name
Test status
Simulation time 1341492678 ps
CPU time 5.68 seconds
Started Jul 06 04:49:27 PM PDT 24
Finished Jul 06 04:49:33 PM PDT 24
Peak memory 198500 kb
Host smart-7bd4280a-2e2d-4bf1-b555-df87498c95f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911635981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2911635981
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2315046777
Short name T248
Test name
Test status
Simulation time 230783659 ps
CPU time 1.12 seconds
Started Jul 06 04:49:19 PM PDT 24
Finished Jul 06 04:49:20 PM PDT 24
Peak memory 196388 kb
Host smart-9ecb0cab-8dbd-481a-ad7f-6f9170df2b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315046777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2315046777
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.91202617
Short name T168
Test name
Test status
Simulation time 41215271 ps
CPU time 0.95 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:35 PM PDT 24
Peak memory 196136 kb
Host smart-96261a09-02ed-47ca-bd9b-82d443f82c3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91202617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.91202617
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1838972365
Short name T637
Test name
Test status
Simulation time 15135879484 ps
CPU time 211.79 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:53:08 PM PDT 24
Peak memory 198668 kb
Host smart-541dcdb6-1614-4aa8-bf8b-05a1a8befa72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838972365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1838972365
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3909255605
Short name T437
Test name
Test status
Simulation time 18828236 ps
CPU time 0.57 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 194796 kb
Host smart-6c561b4f-ad1f-4825-b7ad-82a3a2df3b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909255605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3909255605
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3781441897
Short name T366
Test name
Test status
Simulation time 235332418 ps
CPU time 0.79 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:36 PM PDT 24
Peak memory 196000 kb
Host smart-13491a64-5e81-447d-add6-40959c131afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781441897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3781441897
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3862388462
Short name T611
Test name
Test status
Simulation time 307362714 ps
CPU time 15.37 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 198600 kb
Host smart-60dbc3de-d2ff-401b-9293-728fb1bffc6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862388462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3862388462
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1682606343
Short name T360
Test name
Test status
Simulation time 156143397 ps
CPU time 0.69 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:48 PM PDT 24
Peak memory 195304 kb
Host smart-cde0e056-b931-416a-bf8b-37ea05c3a4c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682606343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1682606343
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2800636105
Short name T564
Test name
Test status
Simulation time 549641406 ps
CPU time 1.22 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 196640 kb
Host smart-1c4e98b5-3ae3-4233-a326-5a8e0de1b5fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800636105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2800636105
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2246670444
Short name T563
Test name
Test status
Simulation time 369883600 ps
CPU time 1.75 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 198620 kb
Host smart-713b8916-e66f-4761-a188-bd6c2a13ddd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246670444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2246670444
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3466941988
Short name T77
Test name
Test status
Simulation time 942968746 ps
CPU time 3.33 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 198636 kb
Host smart-971338ec-a1e7-4172-9c3f-5d24e90d29d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466941988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3466941988
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2767867098
Short name T561
Test name
Test status
Simulation time 48268074 ps
CPU time 1.01 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 196592 kb
Host smart-07a3340f-cbe0-4712-8cae-04ad0c08d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767867098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2767867098
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1106549095
Short name T373
Test name
Test status
Simulation time 51257879 ps
CPU time 1.07 seconds
Started Jul 06 04:49:28 PM PDT 24
Finished Jul 06 04:49:29 PM PDT 24
Peak memory 196644 kb
Host smart-8235e78c-1050-4bdf-a1f9-782d052fadee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106549095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1106549095
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.534974824
Short name T673
Test name
Test status
Simulation time 58443196 ps
CPU time 2.5 seconds
Started Jul 06 04:49:29 PM PDT 24
Finished Jul 06 04:49:32 PM PDT 24
Peak memory 198540 kb
Host smart-db8a1750-13dc-4fd1-9656-6635691b09f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534974824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.534974824
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3743559134
Short name T362
Test name
Test status
Simulation time 113000681 ps
CPU time 1.15 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 196076 kb
Host smart-8d25f704-6dab-4567-9403-4a81b7f54baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743559134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3743559134
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2457930143
Short name T141
Test name
Test status
Simulation time 122215369 ps
CPU time 1.12 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 196852 kb
Host smart-2925bef6-cad1-4296-9fd9-9f988cab5fd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457930143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2457930143
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1323830816
Short name T191
Test name
Test status
Simulation time 11142259453 ps
CPU time 155.14 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:52:16 PM PDT 24
Peak memory 198700 kb
Host smart-ba4bbdba-3e58-4d06-909b-09d2b1697e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323830816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1323830816
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1302196500
Short name T59
Test name
Test status
Simulation time 55333893754 ps
CPU time 1297.02 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 05:11:13 PM PDT 24
Peak memory 198880 kb
Host smart-3767748b-5f9b-494d-a17d-3a8eb466356b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1302196500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1302196500
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2067717636
Short name T420
Test name
Test status
Simulation time 348607053 ps
CPU time 0.77 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 195836 kb
Host smart-3f993b13-1702-46f5-984c-e398a3b66873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067717636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2067717636
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3474909515
Short name T382
Test name
Test status
Simulation time 2684556233 ps
CPU time 27.61 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:50:08 PM PDT 24
Peak memory 198656 kb
Host smart-c4a93392-1499-4fcd-baf9-220aa40d1c54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474909515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3474909515
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.90216609
Short name T20
Test name
Test status
Simulation time 47645636 ps
CPU time 0.79 seconds
Started Jul 06 04:49:43 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 196340 kb
Host smart-d1458c4a-24f1-4ca0-ada0-22fa2b3467e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90216609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.90216609
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1430918299
Short name T589
Test name
Test status
Simulation time 52351343 ps
CPU time 1.25 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 198056 kb
Host smart-7f8416b1-dbf0-4f21-b875-b255f11dbb33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430918299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1430918299
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2277469857
Short name T333
Test name
Test status
Simulation time 158070418 ps
CPU time 2.99 seconds
Started Jul 06 04:49:30 PM PDT 24
Finished Jul 06 04:49:33 PM PDT 24
Peak memory 198776 kb
Host smart-b2d1bb6e-23c6-440c-b2d5-d0e5ac3f41f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277469857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2277469857
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3038986203
Short name T462
Test name
Test status
Simulation time 312024494 ps
CPU time 1.51 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 196372 kb
Host smart-a3318249-bda1-4bc1-b988-bf798a9b3ab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038986203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3038986203
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.194841974
Short name T232
Test name
Test status
Simulation time 116191195 ps
CPU time 1.34 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 198704 kb
Host smart-8de2a765-7617-4339-b139-22968d68fcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194841974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.194841974
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1942288850
Short name T296
Test name
Test status
Simulation time 127339806 ps
CPU time 0.86 seconds
Started Jul 06 04:49:26 PM PDT 24
Finished Jul 06 04:49:27 PM PDT 24
Peak memory 197300 kb
Host smart-bdf82c8e-b1e8-4395-ae76-083cd6fdcf3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942288850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1942288850
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3821045966
Short name T367
Test name
Test status
Simulation time 214303818 ps
CPU time 3.08 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 198564 kb
Host smart-c26450da-a6c5-4581-93f3-236c1d4fef3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821045966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3821045966
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.958648836
Short name T192
Test name
Test status
Simulation time 47422572 ps
CPU time 0.83 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:36 PM PDT 24
Peak memory 195844 kb
Host smart-c16a4902-5b8a-4adf-a93f-0c7ec95f45e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958648836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.958648836
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.55564048
Short name T231
Test name
Test status
Simulation time 40040558 ps
CPU time 1.06 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:37 PM PDT 24
Peak memory 196144 kb
Host smart-edd42284-914a-4bb5-b94e-10790914c265
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55564048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.55564048
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.708107567
Short name T347
Test name
Test status
Simulation time 1676838705 ps
CPU time 24.64 seconds
Started Jul 06 04:49:27 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 198460 kb
Host smart-59d64568-4784-4ade-adf2-535faea32e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708107567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.708107567
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2979641520
Short name T341
Test name
Test status
Simulation time 43461385 ps
CPU time 0.57 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 194660 kb
Host smart-c02621a3-b75e-49d6-bd06-8d2dab4d0b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979641520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2979641520
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.498391497
Short name T331
Test name
Test status
Simulation time 28521479 ps
CPU time 0.63 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:37 PM PDT 24
Peak memory 194584 kb
Host smart-4a58c2a6-0ec5-459e-bea0-118933478508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498391497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.498391497
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.65792846
Short name T600
Test name
Test status
Simulation time 762180944 ps
CPU time 23.53 seconds
Started Jul 06 04:49:22 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 197396 kb
Host smart-50000e80-573d-4c36-a0b6-de64f720e617
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65792846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stress
.65792846
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.925618505
Short name T330
Test name
Test status
Simulation time 104842694 ps
CPU time 1 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:43 PM PDT 24
Peak memory 198312 kb
Host smart-05e096b7-5911-4d3a-84a1-da491fa84f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925618505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.925618505
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1700803731
Short name T317
Test name
Test status
Simulation time 161466476 ps
CPU time 0.95 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 197072 kb
Host smart-48230767-c3e9-42f2-ae1d-b9d73cbddffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700803731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1700803731
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3086448137
Short name T661
Test name
Test status
Simulation time 29352966 ps
CPU time 1.24 seconds
Started Jul 06 04:49:24 PM PDT 24
Finished Jul 06 04:49:26 PM PDT 24
Peak memory 197296 kb
Host smart-e8f8dc77-f7e9-4c3f-ba3e-cb414b3799a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086448137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3086448137
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2032836626
Short name T393
Test name
Test status
Simulation time 250606411 ps
CPU time 2.5 seconds
Started Jul 06 04:49:28 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 197700 kb
Host smart-52119194-7475-4695-b26a-90df0a8ed204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032836626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2032836626
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1228051864
Short name T151
Test name
Test status
Simulation time 38498307 ps
CPU time 1.28 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 196520 kb
Host smart-a4938f36-aab4-42ef-a18e-dfd30148b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228051864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1228051864
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2840971131
Short name T179
Test name
Test status
Simulation time 83727181 ps
CPU time 0.89 seconds
Started Jul 06 04:49:26 PM PDT 24
Finished Jul 06 04:49:28 PM PDT 24
Peak memory 196552 kb
Host smart-d8e95ca4-af5a-4a1a-bd87-2ef403fd36cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840971131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2840971131
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2868552722
Short name T379
Test name
Test status
Simulation time 689441515 ps
CPU time 2.72 seconds
Started Jul 06 04:49:28 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 198516 kb
Host smart-681edd27-4ffe-4d47-b0a1-a547a7219349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868552722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2868552722
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3890998952
Short name T496
Test name
Test status
Simulation time 246735700 ps
CPU time 1.11 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 196120 kb
Host smart-ee6db790-1974-4ce0-a6cf-263a9c81a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890998952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3890998952
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4124000083
Short name T400
Test name
Test status
Simulation time 168440692 ps
CPU time 1 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 197172 kb
Host smart-330b57b0-e739-4b30-8b9a-5f78ef9a4a9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124000083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4124000083
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2077138111
Short name T2
Test name
Test status
Simulation time 9296311414 ps
CPU time 52.93 seconds
Started Jul 06 04:49:25 PM PDT 24
Finished Jul 06 04:50:18 PM PDT 24
Peak memory 198688 kb
Host smart-d56054fa-3d4c-48ed-8e6b-6bdf47e4983b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077138111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2077138111
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1166261826
Short name T669
Test name
Test status
Simulation time 13965015 ps
CPU time 0.58 seconds
Started Jul 06 04:49:03 PM PDT 24
Finished Jul 06 04:49:04 PM PDT 24
Peak memory 194560 kb
Host smart-d92d3169-42aa-4e7d-a4d7-319a1f599f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166261826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1166261826
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1955096106
Short name T573
Test name
Test status
Simulation time 32204944 ps
CPU time 0.8 seconds
Started Jul 06 04:48:56 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 195804 kb
Host smart-3f4ef20b-7529-4a0f-94e7-447e2ad25360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955096106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1955096106
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3500732138
Short name T298
Test name
Test status
Simulation time 670089892 ps
CPU time 4.36 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:49:04 PM PDT 24
Peak memory 197160 kb
Host smart-a59ba429-1782-4c1d-a9d9-fa9a2eee3588
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500732138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3500732138
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.4203254224
Short name T636
Test name
Test status
Simulation time 92356937 ps
CPU time 1.07 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 197204 kb
Host smart-4293a4ab-c708-46f0-a90e-f6a5e5f24cdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203254224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.4203254224
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1566578054
Short name T365
Test name
Test status
Simulation time 33876983 ps
CPU time 0.82 seconds
Started Jul 06 04:48:54 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 196832 kb
Host smart-80562165-97f1-4ffd-ae45-a3b43d5c3501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566578054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1566578054
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2245488065
Short name T164
Test name
Test status
Simulation time 278907114 ps
CPU time 3.06 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 196904 kb
Host smart-c8274976-ea95-4539-9537-49838ef610b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245488065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2245488065
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.348855028
Short name T706
Test name
Test status
Simulation time 472280105 ps
CPU time 3.75 seconds
Started Jul 06 04:48:53 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 198632 kb
Host smart-417eafd8-d166-4628-b455-1bded526d726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348855028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.348855028
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1831942439
Short name T123
Test name
Test status
Simulation time 54455300 ps
CPU time 1.19 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 197780 kb
Host smart-6c4ce160-c780-4a84-8300-fe092788caf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831942439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1831942439
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3362189284
Short name T554
Test name
Test status
Simulation time 253500121 ps
CPU time 1.18 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 197816 kb
Host smart-1003ef17-78b5-40ea-b7d2-94a54df0e755
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362189284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3362189284
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1472675553
Short name T680
Test name
Test status
Simulation time 333949535 ps
CPU time 3.03 seconds
Started Jul 06 04:48:53 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 198460 kb
Host smart-b16d340e-91fa-4800-94b5-43472f7a4f38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472675553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1472675553
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.546154120
Short name T32
Test name
Test status
Simulation time 117303862 ps
CPU time 1.05 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 215344 kb
Host smart-cf1a2b45-96c7-4644-9434-6a567df9b58a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546154120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.546154120
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1884977947
Short name T263
Test name
Test status
Simulation time 91355146 ps
CPU time 0.77 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 195928 kb
Host smart-666c99dd-17ad-462b-8b33-9c3c739827ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884977947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1884977947
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2542388557
Short name T287
Test name
Test status
Simulation time 315124046 ps
CPU time 1.03 seconds
Started Jul 06 04:48:57 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 196312 kb
Host smart-988417fc-7428-40da-b609-a8c8f1b5e6bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542388557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2542388557
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4016695208
Short name T544
Test name
Test status
Simulation time 5400940753 ps
CPU time 31.01 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 198680 kb
Host smart-e98cf72b-a74a-4f7f-b085-603f861f15a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016695208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4016695208
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1905957354
Short name T98
Test name
Test status
Simulation time 100547988170 ps
CPU time 1273.57 seconds
Started Jul 06 04:49:05 PM PDT 24
Finished Jul 06 05:10:20 PM PDT 24
Peak memory 198852 kb
Host smart-ba2d992a-c24b-4342-b378-fe610d86259d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1905957354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1905957354
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1698989572
Short name T34
Test name
Test status
Simulation time 39727760 ps
CPU time 0.61 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 195296 kb
Host smart-7e0a31d9-cea1-45a2-85ee-b77871973a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698989572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1698989572
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1523864820
Short name T485
Test name
Test status
Simulation time 291495975 ps
CPU time 0.9 seconds
Started Jul 06 04:49:43 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 196892 kb
Host smart-3626906b-3dc2-4133-aca1-ea50a09084d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523864820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1523864820
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4072293673
Short name T353
Test name
Test status
Simulation time 530701225 ps
CPU time 14.15 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 196196 kb
Host smart-7d0a7b8f-2694-4854-a31d-3eebc8c103c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072293673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4072293673
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.762901884
Short name T408
Test name
Test status
Simulation time 130001273 ps
CPU time 0.72 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 195284 kb
Host smart-96f7da29-a089-4bf4-8c76-41bb35f8f150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762901884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.762901884
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4230875990
Short name T358
Test name
Test status
Simulation time 84059256 ps
CPU time 1.37 seconds
Started Jul 06 04:49:41 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 198652 kb
Host smart-f67eba72-9c0c-48ab-9c47-454ef8cd9c73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230875990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4230875990
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2442572485
Short name T160
Test name
Test status
Simulation time 1030519967 ps
CPU time 2.72 seconds
Started Jul 06 04:49:39 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 197048 kb
Host smart-c434b6e2-70f3-486c-b4c5-b99e24cad0d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442572485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2442572485
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3027443601
Short name T608
Test name
Test status
Simulation time 134701973 ps
CPU time 2.85 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:50:04 PM PDT 24
Peak memory 196416 kb
Host smart-80b18d9f-8206-4559-adae-3f00e51bdb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027443601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3027443601
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1023845766
Short name T506
Test name
Test status
Simulation time 56105483 ps
CPU time 1.07 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 196352 kb
Host smart-b17beff5-91a4-481f-8a9b-91b71c372a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023845766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1023845766
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1958180160
Short name T246
Test name
Test status
Simulation time 30300829 ps
CPU time 1.09 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 196684 kb
Host smart-949d2600-b2da-4d41-aafd-c7e997783119
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958180160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1958180160
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.238052953
Short name T345
Test name
Test status
Simulation time 252035746 ps
CPU time 2.83 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 198556 kb
Host smart-1d790266-1b8b-411c-b078-774bd4e77ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238052953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.238052953
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2236236437
Short name T578
Test name
Test status
Simulation time 37046896 ps
CPU time 1.1 seconds
Started Jul 06 04:49:23 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 196460 kb
Host smart-347505da-e1d1-4e17-8f11-5bc15c944e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236236437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2236236437
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.465018958
Short name T251
Test name
Test status
Simulation time 213625890 ps
CPU time 0.93 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 197052 kb
Host smart-b810eedd-af28-4fcc-8766-6da81928beca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465018958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.465018958
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.370071450
Short name T644
Test name
Test status
Simulation time 57138713020 ps
CPU time 141.91 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:52:21 PM PDT 24
Peak memory 198680 kb
Host smart-0cd4d03b-5eae-4228-ab78-fbb6c12bac9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370071450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.370071450
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.498657874
Short name T625
Test name
Test status
Simulation time 38910162 ps
CPU time 0.57 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:43 PM PDT 24
Peak memory 194596 kb
Host smart-cce536db-766d-487d-a25e-06927daed4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498657874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.498657874
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2130861642
Short name T356
Test name
Test status
Simulation time 92020243 ps
CPU time 1 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 197284 kb
Host smart-9f745926-7da9-47f0-8654-e01b9bc28eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130861642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2130861642
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3791350208
Short name T312
Test name
Test status
Simulation time 461749479 ps
CPU time 23.8 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 198660 kb
Host smart-d240bfb6-ea98-4d5e-adc2-df819569302c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791350208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3791350208
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.4290461223
Short name T10
Test name
Test status
Simulation time 86071328 ps
CPU time 1 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 197244 kb
Host smart-bfef6316-38cb-45a1-b6fa-926cca169ed8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290461223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.4290461223
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.489123236
Short name T323
Test name
Test status
Simulation time 41883071 ps
CPU time 1.08 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 196692 kb
Host smart-a6d88638-9686-45af-bbf4-45ea5e11ddd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489123236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.489123236
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1119808430
Short name T465
Test name
Test status
Simulation time 117191473 ps
CPU time 1.35 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 197304 kb
Host smart-00178570-e0f9-4d47-bf3d-c51b216a39dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119808430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1119808430
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3672205054
Short name T53
Test name
Test status
Simulation time 490349792 ps
CPU time 2.64 seconds
Started Jul 06 04:49:41 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 198648 kb
Host smart-79a84467-3a0b-4821-b84e-265f4be53a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672205054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3672205054
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1412748217
Short name T272
Test name
Test status
Simulation time 45306442 ps
CPU time 1.06 seconds
Started Jul 06 04:49:46 PM PDT 24
Finished Jul 06 04:49:47 PM PDT 24
Peak memory 196576 kb
Host smart-c9b31ffe-a627-4abd-85c4-647f9261d779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412748217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1412748217
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.198526728
Short name T273
Test name
Test status
Simulation time 77529728 ps
CPU time 0.72 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 196088 kb
Host smart-5181d8ed-5dc1-4415-b23f-562fc0b147ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198526728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.198526728
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3995955293
Short name T389
Test name
Test status
Simulation time 4175404554 ps
CPU time 5.21 seconds
Started Jul 06 04:50:14 PM PDT 24
Finished Jul 06 04:50:19 PM PDT 24
Peak memory 198640 kb
Host smart-515cc128-64fb-4552-9951-0a076e7fac70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995955293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3995955293
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2509527567
Short name T170
Test name
Test status
Simulation time 159370583 ps
CPU time 1.2 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 196472 kb
Host smart-9f1a286e-0ec9-4d28-996d-6ae4b4efd452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509527567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2509527567
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3406904128
Short name T17
Test name
Test status
Simulation time 30078296 ps
CPU time 0.89 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 197108 kb
Host smart-bd5cb084-d87e-4842-bf19-d9dc719d2466
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406904128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3406904128
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2729654403
Short name T640
Test name
Test status
Simulation time 28381670751 ps
CPU time 196.51 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:52:55 PM PDT 24
Peak memory 198824 kb
Host smart-63187e77-574d-4f7f-9337-924aa9e63803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729654403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2729654403
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2377779462
Short name T560
Test name
Test status
Simulation time 330467939238 ps
CPU time 1481.11 seconds
Started Jul 06 04:49:46 PM PDT 24
Finished Jul 06 05:14:28 PM PDT 24
Peak memory 198856 kb
Host smart-4d919cbd-95ab-4eaf-b0da-903bce92fd47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2377779462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2377779462
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1612941626
Short name T591
Test name
Test status
Simulation time 27884943 ps
CPU time 0.59 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:37 PM PDT 24
Peak memory 194780 kb
Host smart-6477d981-48b7-43e4-b6c3-9c60697ecab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612941626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1612941626
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.587924344
Short name T235
Test name
Test status
Simulation time 41167962 ps
CPU time 0.87 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 197608 kb
Host smart-b9fc0d16-0889-43fb-92ef-71ea3aab5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587924344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.587924344
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1055289565
Short name T167
Test name
Test status
Simulation time 690974697 ps
CPU time 24.02 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:50:05 PM PDT 24
Peak memory 197492 kb
Host smart-956f798c-0d63-46ee-98d8-102e225a29af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055289565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1055289565
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1258051905
Short name T386
Test name
Test status
Simulation time 46143943 ps
CPU time 0.74 seconds
Started Jul 06 04:49:39 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 196324 kb
Host smart-41490436-353e-4367-a1dd-eda67cc0c8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258051905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1258051905
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3547780563
Short name T274
Test name
Test status
Simulation time 60508053 ps
CPU time 1.17 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 197428 kb
Host smart-3722946d-a852-4b04-bc1b-08788740d816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547780563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3547780563
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3544157150
Short name T310
Test name
Test status
Simulation time 399832448 ps
CPU time 3.29 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 198708 kb
Host smart-aa0bf9e3-a62e-4e52-8881-4b2276e27022
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544157150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3544157150
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1882178570
Short name T717
Test name
Test status
Simulation time 30028736 ps
CPU time 1.04 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 196324 kb
Host smart-9d90aa75-6e18-463e-aae6-a5baa5f69e77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882178570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1882178570
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1811142921
Short name T705
Test name
Test status
Simulation time 61438533 ps
CPU time 1.21 seconds
Started Jul 06 04:49:41 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 198604 kb
Host smart-daafddf8-2330-4f2f-aa9d-e6404a5a1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811142921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1811142921
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.90802242
Short name T566
Test name
Test status
Simulation time 77770476 ps
CPU time 0.8 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:37 PM PDT 24
Peak memory 196240 kb
Host smart-3cd8155a-5dcd-4c40-a470-585a1859e8e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90802242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup_
pulldown.90802242
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.757960815
Short name T627
Test name
Test status
Simulation time 694681463 ps
CPU time 3.14 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 198576 kb
Host smart-a47752a5-1ee5-4fa0-a1fa-63b2953edf54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757960815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.757960815
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1556242394
Short name T257
Test name
Test status
Simulation time 141005810 ps
CPU time 1.21 seconds
Started Jul 06 04:49:34 PM PDT 24
Finished Jul 06 04:49:37 PM PDT 24
Peak memory 197188 kb
Host smart-1bbcc166-8e57-46df-802d-c366674f38f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556242394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1556242394
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2206022650
Short name T259
Test name
Test status
Simulation time 47670449 ps
CPU time 1.25 seconds
Started Jul 06 04:49:43 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 197172 kb
Host smart-bb638d11-bcbb-4e73-bd28-7c6da77e565b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206022650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2206022650
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.112054351
Short name T480
Test name
Test status
Simulation time 31032701980 ps
CPU time 125.88 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:51:44 PM PDT 24
Peak memory 199092 kb
Host smart-4381635c-473e-4262-b67e-2d3e2cd97b9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112054351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.112054351
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3074088923
Short name T657
Test name
Test status
Simulation time 96697981391 ps
CPU time 1354.01 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 05:12:27 PM PDT 24
Peak memory 198820 kb
Host smart-4f0f6205-1a04-4736-9bd2-0f754fe79c4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3074088923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3074088923
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3773447022
Short name T592
Test name
Test status
Simulation time 15789598 ps
CPU time 0.59 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 194716 kb
Host smart-77208351-b329-4d66-9c0a-fb4409df5bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773447022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3773447022
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.479011329
Short name T297
Test name
Test status
Simulation time 13181070 ps
CPU time 0.66 seconds
Started Jul 06 04:49:32 PM PDT 24
Finished Jul 06 04:49:33 PM PDT 24
Peak memory 194724 kb
Host smart-65228d55-54e1-472a-94e2-0374ed59f3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479011329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.479011329
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2240853532
Short name T137
Test name
Test status
Simulation time 490720934 ps
CPU time 8.23 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 197492 kb
Host smart-0b0a752c-8622-40cb-8a58-ea9867726842
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240853532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2240853532
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.602542223
Short name T292
Test name
Test status
Simulation time 49812428 ps
CPU time 0.76 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 195452 kb
Host smart-53560c2a-c9ab-43fd-a702-fbf178632abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602542223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.602542223
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.430207328
Short name T447
Test name
Test status
Simulation time 291791035 ps
CPU time 1.18 seconds
Started Jul 06 04:49:29 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 197356 kb
Host smart-99892be4-c563-432d-acaa-2fd067f38614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430207328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.430207328
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1350684283
Short name T715
Test name
Test status
Simulation time 101766666 ps
CPU time 2.21 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:43 PM PDT 24
Peak memory 198708 kb
Host smart-2c145f64-c73b-49d3-b767-439a376eaa3c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350684283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1350684283
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2767883832
Short name T63
Test name
Test status
Simulation time 384900601 ps
CPU time 2.85 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:47 PM PDT 24
Peak memory 198544 kb
Host smart-27a7c35b-c8c3-4ef4-a4a2-76431f7b2ed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767883832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2767883832
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3424295457
Short name T392
Test name
Test status
Simulation time 103718109 ps
CPU time 1.21 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 197140 kb
Host smart-faba41cc-6540-4c6d-b785-98f1cd7b7268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424295457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3424295457
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4001641046
Short name T343
Test name
Test status
Simulation time 39122306 ps
CPU time 1.18 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 196544 kb
Host smart-f8e28bff-67ed-442e-9154-43b0e174bd48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001641046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4001641046
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4141298348
Short name T504
Test name
Test status
Simulation time 124592075 ps
CPU time 5.56 seconds
Started Jul 06 04:49:46 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 198464 kb
Host smart-1fbbc927-8df5-4648-af4c-8f2139f4c270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141298348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4141298348
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2885401287
Short name T534
Test name
Test status
Simulation time 443655148 ps
CPU time 1.45 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 197504 kb
Host smart-57c07204-64c8-4758-8a32-cb010e2da77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885401287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2885401287
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3140510731
Short name T691
Test name
Test status
Simulation time 148656928 ps
CPU time 1.18 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 197444 kb
Host smart-bfe7c828-dcfa-41da-851e-4ccd98c2015d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140510731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3140510731
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1846822284
Short name T602
Test name
Test status
Simulation time 19684501795 ps
CPU time 136.3 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:51:54 PM PDT 24
Peak memory 198660 kb
Host smart-b65bd55c-9382-4501-b620-0cd036e21fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846822284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1846822284
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1394972164
Short name T58
Test name
Test status
Simulation time 91617167826 ps
CPU time 1666.62 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 05:17:50 PM PDT 24
Peak memory 198828 kb
Host smart-213d7025-92bf-4567-b3ff-cc3be190c462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1394972164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1394972164
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1795946885
Short name T252
Test name
Test status
Simulation time 14856734 ps
CPU time 0.56 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 194572 kb
Host smart-26f29d7b-9f56-481d-a528-51356e000517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795946885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1795946885
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1869092528
Short name T499
Test name
Test status
Simulation time 56238669 ps
CPU time 0.76 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 196484 kb
Host smart-02dbf6e6-4d9a-488e-af79-dc5c0e07428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869092528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1869092528
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.931145037
Short name T596
Test name
Test status
Simulation time 1117691636 ps
CPU time 12.03 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:50:00 PM PDT 24
Peak memory 196236 kb
Host smart-9b169cc4-4076-467c-bd1e-6dbf330c0722
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931145037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.931145037
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2706626344
Short name T461
Test name
Test status
Simulation time 300157492 ps
CPU time 0.85 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 196596 kb
Host smart-73fcd985-2207-47a3-9870-59cc1a4e5d9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706626344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2706626344
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.175685179
Short name T303
Test name
Test status
Simulation time 53119228 ps
CPU time 0.97 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 197396 kb
Host smart-313320dd-abad-4399-b288-6601844ec9fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175685179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.175685179
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.280281911
Short name T675
Test name
Test status
Simulation time 269678798 ps
CPU time 2.79 seconds
Started Jul 06 04:49:35 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 198600 kb
Host smart-eb5b4cfa-8b1a-4295-a76e-73021e8090cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280281911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.280281911
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3450618536
Short name T460
Test name
Test status
Simulation time 363280316 ps
CPU time 2.92 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:48 PM PDT 24
Peak memory 197532 kb
Host smart-15ebeee4-8410-433f-a3a3-bf2bcdec2df0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450618536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3450618536
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.493517726
Short name T557
Test name
Test status
Simulation time 697239012 ps
CPU time 1.27 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:49:47 PM PDT 24
Peak memory 197632 kb
Host smart-78113447-248f-4100-bf87-738bc7e52289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493517726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.493517726
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2493684055
Short name T517
Test name
Test status
Simulation time 21849786 ps
CPU time 0.9 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 196724 kb
Host smart-1a059d27-f264-4598-b451-7601098bb183
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493684055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2493684055
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3623487655
Short name T421
Test name
Test status
Simulation time 43559187 ps
CPU time 1.59 seconds
Started Jul 06 04:50:06 PM PDT 24
Finished Jul 06 04:50:08 PM PDT 24
Peak memory 198540 kb
Host smart-edd0dcf6-4fc6-43b9-a621-e333c827208f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623487655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3623487655
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.199974150
Short name T258
Test name
Test status
Simulation time 55462161 ps
CPU time 1.13 seconds
Started Jul 06 04:50:05 PM PDT 24
Finished Jul 06 04:50:07 PM PDT 24
Peak memory 196176 kb
Host smart-fd512a18-d458-496a-bdd9-961e8f358bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199974150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.199974150
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2460593586
Short name T539
Test name
Test status
Simulation time 62975033 ps
CPU time 0.99 seconds
Started Jul 06 04:49:36 PM PDT 24
Finished Jul 06 04:49:38 PM PDT 24
Peak memory 196420 kb
Host smart-bf59ae47-d838-464a-9650-137c11b9332b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460593586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2460593586
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.627028179
Short name T569
Test name
Test status
Simulation time 11766810589 ps
CPU time 122.01 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:51:47 PM PDT 24
Peak memory 198776 kb
Host smart-b9cc2f47-d245-485f-ba84-fd300aadedb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627028179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.627028179
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3565096770
Short name T49
Test name
Test status
Simulation time 58737859159 ps
CPU time 616.01 seconds
Started Jul 06 04:49:39 PM PDT 24
Finished Jul 06 04:59:55 PM PDT 24
Peak memory 198764 kb
Host smart-359dca97-c14a-4503-9c3e-8804a2583666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3565096770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3565096770
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1015532691
Short name T80
Test name
Test status
Simulation time 16883566 ps
CPU time 0.62 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 195268 kb
Host smart-4aad3402-dcda-479d-82cf-e9f6e0fe591d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015532691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1015532691
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1476529257
Short name T490
Test name
Test status
Simulation time 81217689 ps
CPU time 0.71 seconds
Started Jul 06 04:49:54 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 195852 kb
Host smart-3c696791-9c41-4b1b-8080-002cacbdcf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476529257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1476529257
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.177316881
Short name T590
Test name
Test status
Simulation time 2659495004 ps
CPU time 26.13 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 198152 kb
Host smart-daecde64-f674-4bba-831e-e1928b0934aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177316881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.177316881
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4156841364
Short name T463
Test name
Test status
Simulation time 83186467 ps
CPU time 0.89 seconds
Started Jul 06 04:49:54 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 197712 kb
Host smart-24141fba-cf88-45dc-85c5-b944e7c7cb78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156841364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4156841364
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.4212223546
Short name T700
Test name
Test status
Simulation time 24507351 ps
CPU time 0.69 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:43 PM PDT 24
Peak memory 194812 kb
Host smart-1ca98956-e021-4071-aad3-eb28eb58f7b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212223546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.4212223546
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3826965317
Short name T157
Test name
Test status
Simulation time 43886550 ps
CPU time 1.08 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 198352 kb
Host smart-23f076df-e599-478f-b4f7-87b7bbdb8a38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826965317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3826965317
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1549547931
Short name T19
Test name
Test status
Simulation time 262679902 ps
CPU time 2.01 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:06 PM PDT 24
Peak memory 198048 kb
Host smart-025c7beb-8948-49b8-bd4d-07572a47a7d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549547931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1549547931
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.707928088
Short name T605
Test name
Test status
Simulation time 65239173 ps
CPU time 1.23 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 196432 kb
Host smart-845810b0-461a-4842-9da8-090d05446840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707928088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.707928088
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.921438955
Short name T219
Test name
Test status
Simulation time 37396900 ps
CPU time 0.89 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 196376 kb
Host smart-a35f8d41-37a1-4081-9f9b-043df2a3d9c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921438955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.921438955
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3957991207
Short name T693
Test name
Test status
Simulation time 799611034 ps
CPU time 4.39 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 198572 kb
Host smart-5d609e28-3818-46cb-8b91-ad26ea9d37f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957991207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3957991207
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2438724692
Short name T169
Test name
Test status
Simulation time 92820209 ps
CPU time 1.12 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 196536 kb
Host smart-8717e07f-0266-46b7-9d80-0509e2283735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438724692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2438724692
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1479775108
Short name T643
Test name
Test status
Simulation time 135859746 ps
CPU time 1.44 seconds
Started Jul 06 04:49:37 PM PDT 24
Finished Jul 06 04:49:40 PM PDT 24
Peak memory 197532 kb
Host smart-24d9d1d2-c01b-43fc-bb98-24d1dccb3694
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479775108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1479775108
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2859260893
Short name T610
Test name
Test status
Simulation time 7136569097 ps
CPU time 191.13 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:52:56 PM PDT 24
Peak memory 198676 kb
Host smart-a738bcfc-f8d0-42ae-a34e-0a9aae1fd5b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859260893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2859260893
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1797227975
Short name T475
Test name
Test status
Simulation time 78415566539 ps
CPU time 508.89 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:58:22 PM PDT 24
Peak memory 198892 kb
Host smart-6c2bc3d9-d5a6-4f7f-b7ff-ff6439660185
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1797227975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1797227975
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2362099387
Short name T505
Test name
Test status
Simulation time 31027676 ps
CPU time 0.59 seconds
Started Jul 06 04:49:38 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 195268 kb
Host smart-a0a8deb9-39fb-4a94-8afe-2c538f5c3233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362099387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2362099387
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1676347511
Short name T124
Test name
Test status
Simulation time 188952162 ps
CPU time 0.68 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 194672 kb
Host smart-488a825a-08a2-4504-8120-a00d01503264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676347511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1676347511
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2925305698
Short name T308
Test name
Test status
Simulation time 1350668527 ps
CPU time 15.01 seconds
Started Jul 06 04:49:46 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 197620 kb
Host smart-ec7fcdc7-1964-4814-bb09-94d1d78313ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925305698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2925305698
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2822885761
Short name T477
Test name
Test status
Simulation time 31437930 ps
CPU time 0.7 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 196052 kb
Host smart-3bb79a82-52c2-49d8-9b1f-d789325ac1a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822885761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2822885761
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2069796100
Short name T676
Test name
Test status
Simulation time 73690090 ps
CPU time 1.29 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:49:47 PM PDT 24
Peak memory 197196 kb
Host smart-07047421-b3d4-463f-8566-44797a4f1808
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069796100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2069796100
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3389126351
Short name T481
Test name
Test status
Simulation time 97824251 ps
CPU time 3.47 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:53 PM PDT 24
Peak memory 198608 kb
Host smart-76a9ad7b-8ca8-48cb-92d2-d8bf474ebf69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389126351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3389126351
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2378860715
Short name T61
Test name
Test status
Simulation time 202694603 ps
CPU time 2.15 seconds
Started Jul 06 04:49:51 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 197572 kb
Host smart-19a787d7-bc9a-48a8-83e1-602cc44c4c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378860715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2378860715
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3019078054
Short name T307
Test name
Test status
Simulation time 40939105 ps
CPU time 0.85 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 197100 kb
Host smart-9e2a7fc1-0ee2-434b-8dfb-8c73be9d4d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019078054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3019078054
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.924084403
Short name T202
Test name
Test status
Simulation time 32045908 ps
CPU time 1.1 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 197604 kb
Host smart-c63e6415-5cd4-4651-8bd8-6bfac50be28d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924084403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.924084403
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3483058542
Short name T4
Test name
Test status
Simulation time 8600541368 ps
CPU time 6.21 seconds
Started Jul 06 04:49:43 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 198712 kb
Host smart-9228ae0a-cacf-42a7-ac27-8880d3830d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483058542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3483058542
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1386754949
Short name T52
Test name
Test status
Simulation time 120258313 ps
CPU time 1.2 seconds
Started Jul 06 04:49:40 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 197496 kb
Host smart-67239ab0-e867-421a-b9dd-4fc82524be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386754949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1386754949
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4082286757
Short name T119
Test name
Test status
Simulation time 50941496 ps
CPU time 1.01 seconds
Started Jul 06 04:49:51 PM PDT 24
Finished Jul 06 04:49:53 PM PDT 24
Peak memory 196272 kb
Host smart-8ece7857-3f85-444f-92ba-e9fec89df2f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082286757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4082286757
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3552475313
Short name T687
Test name
Test status
Simulation time 29193031771 ps
CPU time 208.69 seconds
Started Jul 06 04:49:41 PM PDT 24
Finished Jul 06 04:53:10 PM PDT 24
Peak memory 198776 kb
Host smart-63158e86-6c27-4f04-86e6-a96b1d125302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552475313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3552475313
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.485371290
Short name T568
Test name
Test status
Simulation time 12935167 ps
CPU time 0.61 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 194536 kb
Host smart-4299f9b6-fd64-42c8-b93c-608c9e4fba3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485371290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.485371290
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3717787487
Short name T415
Test name
Test status
Simulation time 20931303 ps
CPU time 0.65 seconds
Started Jul 06 04:49:39 PM PDT 24
Finished Jul 06 04:49:41 PM PDT 24
Peak memory 195332 kb
Host smart-79e94894-0b5d-4a8e-9b41-ef377fa0edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717787487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3717787487
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.809447848
Short name T224
Test name
Test status
Simulation time 621573354 ps
CPU time 17.42 seconds
Started Jul 06 04:49:46 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 196060 kb
Host smart-24f6b6a8-2a55-4d37-88aa-8cffa61b323c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809447848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.809447848
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2594535071
Short name T698
Test name
Test status
Simulation time 41584701 ps
CPU time 0.77 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:04 PM PDT 24
Peak memory 195964 kb
Host smart-270a4f37-92ff-439f-b27b-bcd3e9435c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594535071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2594535071
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.317673857
Short name T267
Test name
Test status
Simulation time 26508475 ps
CPU time 0.8 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 197120 kb
Host smart-db8fdaa4-cb72-4556-b06e-e3f5246a29cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317673857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.317673857
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3155445516
Short name T166
Test name
Test status
Simulation time 88202879 ps
CPU time 3.58 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 198612 kb
Host smart-eb41648a-cdfd-4f06-af43-3c9d9b10c0ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155445516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3155445516
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1071463982
Short name T649
Test name
Test status
Simulation time 38652728 ps
CPU time 1.28 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:59 PM PDT 24
Peak memory 197412 kb
Host smart-e6e2415c-3dc0-495a-8e59-93ec95f517c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071463982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1071463982
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.951355626
Short name T22
Test name
Test status
Simulation time 137260783 ps
CPU time 1.19 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 197652 kb
Host smart-5d8a0be4-8379-451e-891e-c158fcab9843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951355626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.951355626
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1028840856
Short name T127
Test name
Test status
Simulation time 147066513 ps
CPU time 1.35 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 197828 kb
Host smart-f3254694-a41e-4401-9c01-2bb9b948dabf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028840856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1028840856
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4247701642
Short name T5
Test name
Test status
Simulation time 1850412147 ps
CPU time 6.04 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:53 PM PDT 24
Peak memory 198564 kb
Host smart-54be9d6e-3173-4897-98be-a0c5e71cd77a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247701642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4247701642
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.994858688
Short name T369
Test name
Test status
Simulation time 61884915 ps
CPU time 1.11 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 196360 kb
Host smart-a0388651-eb44-4b62-ab28-f6491fd29f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994858688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.994858688
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2648962429
Short name T458
Test name
Test status
Simulation time 75400498 ps
CPU time 1.24 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 196380 kb
Host smart-a3c283ae-7745-4b48-a33b-356855958e06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648962429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2648962429
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.8942921
Short name T249
Test name
Test status
Simulation time 18891199684 ps
CPU time 130.96 seconds
Started Jul 06 04:49:45 PM PDT 24
Finished Jul 06 04:51:57 PM PDT 24
Peak memory 198668 kb
Host smart-fd2525ad-6119-4634-92a3-6ef7dcc8dcd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8942921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpi
o_stress_all.8942921
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1242295042
Short name T35
Test name
Test status
Simulation time 57697139 ps
CPU time 0.6 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:59 PM PDT 24
Peak memory 195536 kb
Host smart-f0f068f9-5217-45e1-aa89-81228a76e59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242295042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1242295042
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.839821079
Short name T512
Test name
Test status
Simulation time 59011599 ps
CPU time 0.69 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:48 PM PDT 24
Peak memory 195444 kb
Host smart-cb913144-cb40-40c7-bc26-b372d5407d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839821079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.839821079
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1530269094
Short name T665
Test name
Test status
Simulation time 1384466380 ps
CPU time 23.32 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:50:06 PM PDT 24
Peak memory 197464 kb
Host smart-5f3e651d-8835-47c9-97c5-0de7cdefbdc1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530269094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1530269094
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2821676540
Short name T380
Test name
Test status
Simulation time 86666094 ps
CPU time 1.02 seconds
Started Jul 06 04:49:51 PM PDT 24
Finished Jul 06 04:49:53 PM PDT 24
Peak memory 197012 kb
Host smart-2fa704b8-1197-41a0-9416-5a1d4a44ba9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821676540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2821676540
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.846524177
Short name T456
Test name
Test status
Simulation time 23592568 ps
CPU time 0.75 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 195960 kb
Host smart-dd3938af-0c99-4e09-bbf9-506a48f55b2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846524177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.846524177
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1731722378
Short name T656
Test name
Test status
Simulation time 72514011 ps
CPU time 3 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 198632 kb
Host smart-807df12c-83fd-4195-aa07-ea51498f1df4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731722378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1731722378
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.667350444
Short name T372
Test name
Test status
Simulation time 249627107 ps
CPU time 3.44 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 197764 kb
Host smart-7330f43e-a7a3-450b-8971-953409dd2b68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667350444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
667350444
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1628239749
Short name T492
Test name
Test status
Simulation time 67976766 ps
CPU time 1.21 seconds
Started Jul 06 04:49:46 PM PDT 24
Finished Jul 06 04:49:48 PM PDT 24
Peak memory 197764 kb
Host smart-62bc03f0-1cb0-400c-9827-65daf653a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628239749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1628239749
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.30890466
Short name T300
Test name
Test status
Simulation time 102701704 ps
CPU time 1.06 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 196564 kb
Host smart-e7162e13-547d-44fe-a63e-2e79012ba50c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30890466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup_
pulldown.30890466
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3757769129
Short name T550
Test name
Test status
Simulation time 94404115 ps
CPU time 4.22 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 198556 kb
Host smart-c6f3543f-d6df-4291-88d2-b991a86234fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757769129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3757769129
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4191914177
Short name T623
Test name
Test status
Simulation time 147170055 ps
CPU time 1.23 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 196416 kb
Host smart-8cf388a6-e784-45f4-aba8-ecd21a1029e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191914177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4191914177
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.4166775179
Short name T223
Test name
Test status
Simulation time 39981215 ps
CPU time 0.72 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:49:46 PM PDT 24
Peak memory 196520 kb
Host smart-0488080b-f162-44bc-b382-0b8400f60c19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166775179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.4166775179
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3759639764
Short name T364
Test name
Test status
Simulation time 5760769660 ps
CPU time 78.18 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:51:17 PM PDT 24
Peak memory 198732 kb
Host smart-c2bdbe47-bb45-46ba-81e1-3bae76feff3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759639764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3759639764
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1706608898
Short name T699
Test name
Test status
Simulation time 12047718 ps
CPU time 0.63 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 194592 kb
Host smart-f4ce8052-a1e7-47d2-b5ca-3305a5e3cf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706608898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1706608898
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4232771685
Short name T348
Test name
Test status
Simulation time 54837036 ps
CPU time 0.68 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 194708 kb
Host smart-9fc33343-ce61-415a-9aee-a5ba0f2dca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232771685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4232771685
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1768240665
Short name T712
Test name
Test status
Simulation time 10632396179 ps
CPU time 16.78 seconds
Started Jul 06 04:49:44 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 197608 kb
Host smart-f98e4eb0-19f7-44a8-ad4c-5def000ed6d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768240665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1768240665
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4197312874
Short name T635
Test name
Test status
Simulation time 40463264 ps
CPU time 0.84 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 197116 kb
Host smart-f55d0915-cde9-4f37-8976-aac07f633d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197312874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4197312874
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.977205678
Short name T659
Test name
Test status
Simulation time 108130053 ps
CPU time 1.12 seconds
Started Jul 06 04:49:43 PM PDT 24
Finished Jul 06 04:49:45 PM PDT 24
Peak memory 196404 kb
Host smart-dacbfdfa-f11b-432f-9c34-7f9bbbb0faaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977205678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.977205678
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3687319961
Short name T716
Test name
Test status
Simulation time 544414565 ps
CPU time 3.4 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:11 PM PDT 24
Peak memory 198664 kb
Host smart-fa93623b-630f-4ece-ac85-04592e36874f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687319961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3687319961
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.345353693
Short name T139
Test name
Test status
Simulation time 126492229 ps
CPU time 0.99 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 196144 kb
Host smart-46b68d1b-7e5c-4d10-a8b8-f4c3c050398e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345353693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
345353693
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3810100446
Short name T494
Test name
Test status
Simulation time 33828133 ps
CPU time 0.66 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 194856 kb
Host smart-8e3074f7-0717-44ca-9346-ca4af2f6eb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810100446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3810100446
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3445778789
Short name T132
Test name
Test status
Simulation time 68601199 ps
CPU time 0.72 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 196588 kb
Host smart-e735258e-0daf-493c-9598-fc60ce0fbabb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445778789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3445778789
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1512802768
Short name T582
Test name
Test status
Simulation time 627475310 ps
CPU time 2.34 seconds
Started Jul 06 04:50:06 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 198564 kb
Host smart-26b8f745-5fab-4d0a-86c8-2fd9777abf4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512802768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1512802768
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.943610847
Short name T570
Test name
Test status
Simulation time 321762470 ps
CPU time 1.03 seconds
Started Jul 06 04:49:42 PM PDT 24
Finished Jul 06 04:49:44 PM PDT 24
Peak memory 196300 kb
Host smart-9a859a3b-a2f6-4dfb-b108-934bf24da12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943610847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.943610847
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.977947690
Short name T264
Test name
Test status
Simulation time 80900807 ps
CPU time 1.29 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:05 PM PDT 24
Peak memory 198616 kb
Host smart-5496ab34-15e7-4374-a6f9-325e29a06bcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977947690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.977947690
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.86163850
Short name T442
Test name
Test status
Simulation time 13073510693 ps
CPU time 35.64 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:36 PM PDT 24
Peak memory 198788 kb
Host smart-d083a4e4-1c69-4650-9aec-fb05990b1919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86163850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gp
io_stress_all.86163850
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.531739330
Short name T531
Test name
Test status
Simulation time 16727753 ps
CPU time 0.58 seconds
Started Jul 06 04:49:01 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 194768 kb
Host smart-d58cec89-a549-45f9-8b11-e57e2417bede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531739330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.531739330
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3925964748
Short name T134
Test name
Test status
Simulation time 33761798 ps
CPU time 0.85 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:54 PM PDT 24
Peak memory 196468 kb
Host smart-433df5d4-9417-4cb1-a9bc-dd12c470272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925964748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3925964748
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.648718942
Short name T704
Test name
Test status
Simulation time 3287938837 ps
CPU time 24.46 seconds
Started Jul 06 04:49:05 PM PDT 24
Finished Jul 06 04:49:30 PM PDT 24
Peak memory 197184 kb
Host smart-178393ee-91d0-4e0d-98de-b85aa1d3bb4e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648718942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.648718942
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2378891749
Short name T679
Test name
Test status
Simulation time 234960652 ps
CPU time 1.1 seconds
Started Jul 06 04:48:57 PM PDT 24
Finished Jul 06 04:48:58 PM PDT 24
Peak memory 196924 kb
Host smart-6eda5cd4-f99f-4b04-ab75-0faec83116a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378891749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2378891749
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1625970357
Short name T426
Test name
Test status
Simulation time 92419130 ps
CPU time 1.38 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 196432 kb
Host smart-5e63d29b-8083-4cbc-ac0b-64d230bcbb4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625970357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1625970357
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.775491632
Short name T322
Test name
Test status
Simulation time 110979998 ps
CPU time 2.58 seconds
Started Jul 06 04:48:52 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 198656 kb
Host smart-1e398d6e-872d-45ec-8cc4-31ba336b6b1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775491632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.775491632
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2478200894
Short name T603
Test name
Test status
Simulation time 398708807 ps
CPU time 2.21 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:49:14 PM PDT 24
Peak memory 197852 kb
Host smart-eac4434d-02bd-46d8-a60d-554b0b0a16df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478200894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2478200894
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3050547255
Short name T284
Test name
Test status
Simulation time 15647528 ps
CPU time 0.72 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:56 PM PDT 24
Peak memory 195908 kb
Host smart-fe5f8aaf-69cc-411d-97a6-dc65f0e0c9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050547255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3050547255
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2586341295
Short name T489
Test name
Test status
Simulation time 22532336 ps
CPU time 0.92 seconds
Started Jul 06 04:48:58 PM PDT 24
Finished Jul 06 04:48:59 PM PDT 24
Peak memory 197784 kb
Host smart-f3e44712-dcc7-42a7-8b6c-af1e8ac35673
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586341295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2586341295
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2389093467
Short name T422
Test name
Test status
Simulation time 867116873 ps
CPU time 2.69 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 04:49:09 PM PDT 24
Peak memory 198544 kb
Host smart-5244428b-0ce6-4aaf-9637-ef20819fd92b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389093467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2389093467
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.3521016385
Short name T230
Test name
Test status
Simulation time 85310233 ps
CPU time 1.33 seconds
Started Jul 06 04:49:14 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 198604 kb
Host smart-2b909757-e4cd-4b19-be9b-9315bd9cf44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521016385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3521016385
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3981439295
Short name T131
Test name
Test status
Simulation time 69601343 ps
CPU time 1.11 seconds
Started Jul 06 04:48:53 PM PDT 24
Finished Jul 06 04:48:55 PM PDT 24
Peak memory 196160 kb
Host smart-b85f83af-cb85-4d39-bf92-a1d7f2c25513
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981439295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3981439295
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2968417970
Short name T402
Test name
Test status
Simulation time 29181222893 ps
CPU time 149.51 seconds
Started Jul 06 04:49:05 PM PDT 24
Finished Jul 06 04:51:35 PM PDT 24
Peak memory 198772 kb
Host smart-310819ca-3191-4381-a614-fdcbe99ac674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968417970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2968417970
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.171724550
Short name T354
Test name
Test status
Simulation time 36491276 ps
CPU time 0.59 seconds
Started Jul 06 04:49:54 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 194852 kb
Host smart-a3fce31b-46eb-44cd-a999-a1c34be77f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171724550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.171724550
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.742710514
Short name T243
Test name
Test status
Simulation time 50533397 ps
CPU time 0.87 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 196860 kb
Host smart-5bb22b25-00ef-45c1-9e25-b09822f6e241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742710514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.742710514
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.693175486
Short name T245
Test name
Test status
Simulation time 3520724914 ps
CPU time 25.74 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:50:16 PM PDT 24
Peak memory 197552 kb
Host smart-397cbbff-1e15-407d-ae9a-3dbb24f1dbb3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693175486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.693175486
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3564530076
Short name T689
Test name
Test status
Simulation time 84439845 ps
CPU time 1.03 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 198536 kb
Host smart-c35b034e-619f-4dbf-bfe6-f6ccc0b87afb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564530076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3564530076
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2164610739
Short name T641
Test name
Test status
Simulation time 47990555 ps
CPU time 0.81 seconds
Started Jul 06 04:50:11 PM PDT 24
Finished Jul 06 04:50:12 PM PDT 24
Peak memory 196008 kb
Host smart-9633204e-3b16-4e43-9ae0-7aea793bebad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164610739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2164610739
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3104678938
Short name T671
Test name
Test status
Simulation time 1601798196 ps
CPU time 3.19 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:11 PM PDT 24
Peak memory 198664 kb
Host smart-430d6e65-aa49-473b-8cf5-7c346aae2ce0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104678938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3104678938
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3827993715
Short name T443
Test name
Test status
Simulation time 299752828 ps
CPU time 0.91 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 195016 kb
Host smart-19f964dd-1b55-4c43-a2f1-9bcc94c97b84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827993715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3827993715
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3730238515
Short name T135
Test name
Test status
Simulation time 147112163 ps
CPU time 1.3 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 197584 kb
Host smart-4492f9d7-5bd4-4e90-b191-1b0900b5fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730238515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3730238515
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2944926850
Short name T143
Test name
Test status
Simulation time 54293547 ps
CPU time 0.79 seconds
Started Jul 06 04:50:04 PM PDT 24
Finished Jul 06 04:50:05 PM PDT 24
Peak memory 196048 kb
Host smart-5c79b61c-375d-4808-abd1-e6602901621a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944926850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2944926850
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1053810966
Short name T384
Test name
Test status
Simulation time 1035474411 ps
CPU time 3.25 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 198520 kb
Host smart-e71d926b-f47b-44ad-9213-ba8a2d62b810
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053810966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1053810966
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3173097508
Short name T488
Test name
Test status
Simulation time 156628823 ps
CPU time 1.37 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 197204 kb
Host smart-341bdb8a-6d58-46bb-a5c9-4df703750070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173097508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3173097508
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4008651463
Short name T618
Test name
Test status
Simulation time 48696546 ps
CPU time 1.23 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:59 PM PDT 24
Peak memory 196152 kb
Host smart-ec68c10c-da7a-440c-98b4-f3323816a079
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008651463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4008651463
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.684087450
Short name T118
Test name
Test status
Simulation time 4548290497 ps
CPU time 123.3 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:52:04 PM PDT 24
Peak memory 198764 kb
Host smart-62c3ef34-8f3b-4d99-8d74-1f083e377fdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684087450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.684087450
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3420961053
Short name T26
Test name
Test status
Simulation time 201875649450 ps
CPU time 2033.22 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 05:23:41 PM PDT 24
Peak memory 198824 kb
Host smart-be62fa6b-de2e-44d5-a98e-25a383a045f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3420961053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3420961053
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2744675
Short name T327
Test name
Test status
Simulation time 19221202 ps
CPU time 0.66 seconds
Started Jul 06 04:50:01 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 194760 kb
Host smart-2d1a1949-5dc8-4cf3-8a20-12a1ff111497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2744675
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3316017284
Short name T696
Test name
Test status
Simulation time 46317176 ps
CPU time 0.63 seconds
Started Jul 06 04:49:55 PM PDT 24
Finished Jul 06 04:49:56 PM PDT 24
Peak memory 194556 kb
Host smart-0cd62cd4-9458-4730-b975-3588e58637ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316017284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3316017284
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1494989063
Short name T255
Test name
Test status
Simulation time 2594467695 ps
CPU time 16.29 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:51:23 PM PDT 24
Peak memory 197416 kb
Host smart-19bef141-60fa-4f4c-85cb-a89481d6dfec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494989063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1494989063
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1573677700
Short name T406
Test name
Test status
Simulation time 330287001 ps
CPU time 1.06 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:57 PM PDT 24
Peak memory 198332 kb
Host smart-2a17e58d-14b1-4413-b903-925d92a3782e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573677700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1573677700
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1941479761
Short name T194
Test name
Test status
Simulation time 49606778 ps
CPU time 0.67 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 194840 kb
Host smart-8dd584a7-5de9-4952-a634-98f0bd0a4eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941479761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1941479761
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1473125184
Short name T650
Test name
Test status
Simulation time 74131634 ps
CPU time 2.66 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 197164 kb
Host smart-b169a0a1-3e9d-4fa4-9812-e0aec0245d79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473125184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1473125184
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.457876177
Short name T309
Test name
Test status
Simulation time 63192540 ps
CPU time 1.6 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 196752 kb
Host smart-7f0369bf-9efb-427b-9d14-d03ca6ade9c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457876177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
457876177
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.838743961
Short name T397
Test name
Test status
Simulation time 107855264 ps
CPU time 0.84 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 196700 kb
Host smart-d85d20b7-f0e5-4f9e-86c0-c3ba98e873a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838743961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.838743961
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.351782273
Short name T588
Test name
Test status
Simulation time 61724435 ps
CPU time 1.25 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:00 PM PDT 24
Peak memory 197660 kb
Host smart-50b1b08b-7dee-47f8-a8bd-06ace658cd65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351782273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.351782273
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1562764755
Short name T538
Test name
Test status
Simulation time 1306306045 ps
CPU time 4.43 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:12 PM PDT 24
Peak memory 198588 kb
Host smart-311680b6-0775-4eca-a040-b59276e02dee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562764755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1562764755
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1401394543
Short name T237
Test name
Test status
Simulation time 140227186 ps
CPU time 1.17 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 197120 kb
Host smart-2071cd51-9e13-42e3-95fe-5c2988fa0009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401394543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1401394543
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2607620271
Short name T313
Test name
Test status
Simulation time 115166685 ps
CPU time 1.14 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 196348 kb
Host smart-cb16ced7-0f49-4b81-aa82-1d94e72807ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607620271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2607620271
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.4173613318
Short name T388
Test name
Test status
Simulation time 5473383337 ps
CPU time 147.54 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:52:33 PM PDT 24
Peak memory 198704 kb
Host smart-3f8fe3f1-6632-43a1-8050-e566828b403f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173613318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.4173613318
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.465826546
Short name T686
Test name
Test status
Simulation time 39277196 ps
CPU time 0.59 seconds
Started Jul 06 04:50:52 PM PDT 24
Finished Jul 06 04:50:53 PM PDT 24
Peak memory 193660 kb
Host smart-6153342d-76c3-45a7-85c7-33826acea9f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465826546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.465826546
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2662642912
Short name T430
Test name
Test status
Simulation time 66136807 ps
CPU time 0.8 seconds
Started Jul 06 04:49:50 PM PDT 24
Finished Jul 06 04:49:52 PM PDT 24
Peak memory 195864 kb
Host smart-a1ce942f-2a8a-46c5-842d-40a5533e84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662642912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2662642912
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2242971339
Short name T614
Test name
Test status
Simulation time 2772853365 ps
CPU time 24.35 seconds
Started Jul 06 04:50:08 PM PDT 24
Finished Jul 06 04:50:33 PM PDT 24
Peak memory 197220 kb
Host smart-e9639e51-d09a-44c8-94e9-4fb9ed75362b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242971339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2242971339
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2250168352
Short name T525
Test name
Test status
Simulation time 424513864 ps
CPU time 0.7 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 195320 kb
Host smart-42622448-4d46-4e6b-a7c9-099a44dc876e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250168352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2250168352
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3144356909
Short name T587
Test name
Test status
Simulation time 89396217 ps
CPU time 1.22 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 196764 kb
Host smart-a9ee0dd5-930c-4c4b-9065-ff460f0893c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144356909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3144356909
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1462324814
Short name T713
Test name
Test status
Simulation time 287904698 ps
CPU time 2.69 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:49:56 PM PDT 24
Peak memory 197172 kb
Host smart-6dc8f7e9-15f2-4f71-af73-f3c2c69b4323
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462324814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1462324814
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2067017549
Short name T180
Test name
Test status
Simulation time 254179062 ps
CPU time 2.04 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 198780 kb
Host smart-b92ce04a-f09f-4d00-9a30-b09368383882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067017549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2067017549
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2642242423
Short name T391
Test name
Test status
Simulation time 113269468 ps
CPU time 0.77 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 196736 kb
Host smart-6a450b34-8178-4fca-8100-e97245697514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642242423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2642242423
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1488986718
Short name T467
Test name
Test status
Simulation time 39248499 ps
CPU time 0.9 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:04 PM PDT 24
Peak memory 197344 kb
Host smart-f9753592-3b7b-4063-bbdc-2c6044a41319
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488986718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1488986718
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3727741834
Short name T283
Test name
Test status
Simulation time 209257603 ps
CPU time 4.97 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 198552 kb
Host smart-3dc5ba01-a801-4cda-b209-0e5178a442da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727741834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3727741834
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1655072196
Short name T510
Test name
Test status
Simulation time 209939541 ps
CPU time 1.07 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:04 PM PDT 24
Peak memory 196332 kb
Host smart-f883671d-6f65-4447-a141-3d6304217285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655072196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1655072196
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1175702532
Short name T559
Test name
Test status
Simulation time 77960390 ps
CPU time 1.27 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 197764 kb
Host smart-00a2948e-2941-4a99-80c0-9c183e385fe5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175702532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1175702532
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3478469918
Short name T598
Test name
Test status
Simulation time 14873859216 ps
CPU time 168.8 seconds
Started Jul 06 04:49:54 PM PDT 24
Finished Jul 06 04:52:43 PM PDT 24
Peak memory 198696 kb
Host smart-ae047d11-9259-4dfe-9161-68597f558b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478469918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3478469918
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2945804211
Short name T244
Test name
Test status
Simulation time 15059227 ps
CPU time 0.65 seconds
Started Jul 06 04:50:08 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 195588 kb
Host smart-ba2f77fb-cb9d-47e1-83d6-8ef5c059f8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945804211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2945804211
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3632334310
Short name T211
Test name
Test status
Simulation time 55298410 ps
CPU time 0.68 seconds
Started Jul 06 04:49:47 PM PDT 24
Finished Jul 06 04:49:49 PM PDT 24
Peak memory 195184 kb
Host smart-6a569867-f526-4e2e-a225-7eacd541d67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632334310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3632334310
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3928041497
Short name T111
Test name
Test status
Simulation time 1206117279 ps
CPU time 16.88 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:50:07 PM PDT 24
Peak memory 197436 kb
Host smart-ac0393c6-0f7f-4a62-a4fd-0b2d9b1a87d9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928041497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3928041497
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3494765391
Short name T8
Test name
Test status
Simulation time 235121017 ps
CPU time 0.77 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 196828 kb
Host smart-998574da-4a8c-484f-9de3-d02b31b060b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494765391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3494765391
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2101830496
Short name T233
Test name
Test status
Simulation time 190489376 ps
CPU time 1.06 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 196512 kb
Host smart-bc131d67-2cd6-4a24-937f-4797720aff55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101830496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2101830496
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3496903295
Short name T109
Test name
Test status
Simulation time 180634524 ps
CPU time 0.92 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:51:08 PM PDT 24
Peak memory 196716 kb
Host smart-e4047f39-c270-4446-b73b-da3914fc3f94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496903295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3496903295
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3558730956
Short name T280
Test name
Test status
Simulation time 446268164 ps
CPU time 2.56 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 198792 kb
Host smart-07323c2f-4886-4df0-b491-0d57c5ccc053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558730956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3558730956
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2564352454
Short name T468
Test name
Test status
Simulation time 34461020 ps
CPU time 0.91 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 196692 kb
Host smart-3576b0e5-d23c-4a29-9e77-40ed4ca78a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564352454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2564352454
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1889587098
Short name T398
Test name
Test status
Simulation time 214798032 ps
CPU time 1.26 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:54 PM PDT 24
Peak memory 197596 kb
Host smart-686a80b8-bfa0-492b-a10b-1cf7389e8d4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889587098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1889587098
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3017145856
Short name T254
Test name
Test status
Simulation time 106665460 ps
CPU time 5.1 seconds
Started Jul 06 04:49:49 PM PDT 24
Finished Jul 06 04:49:56 PM PDT 24
Peak memory 198536 kb
Host smart-8e748010-74c1-4507-a80f-5c83759c8486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017145856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3017145856
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3301538473
Short name T434
Test name
Test status
Simulation time 165875606 ps
CPU time 1.08 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:50 PM PDT 24
Peak memory 196408 kb
Host smart-441e08cb-3d22-4645-acc2-ea39bc925d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301538473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3301538473
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1812699201
Short name T172
Test name
Test status
Simulation time 132387704 ps
CPU time 0.97 seconds
Started Jul 06 04:49:52 PM PDT 24
Finished Jul 06 04:49:53 PM PDT 24
Peak memory 196156 kb
Host smart-66bc3390-0922-4f2f-9466-7d2ab536afbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812699201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1812699201
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2044861992
Short name T342
Test name
Test status
Simulation time 22777800419 ps
CPU time 124.82 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:52:07 PM PDT 24
Peak memory 198744 kb
Host smart-d4ebac1a-5205-4581-8667-6ef8ace5a06b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044861992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2044861992
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.4126452393
Short name T411
Test name
Test status
Simulation time 42714435 ps
CPU time 0.62 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 194588 kb
Host smart-ef43f82e-9faf-4fc0-8eaf-0e70705e9ef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126452393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.4126452393
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2909532321
Short name T472
Test name
Test status
Simulation time 38389368 ps
CPU time 0.67 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:57 PM PDT 24
Peak memory 194732 kb
Host smart-0b17d1fe-73e3-4ee5-99f9-045e547df1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909532321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2909532321
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.290888000
Short name T76
Test name
Test status
Simulation time 1496715312 ps
CPU time 23.21 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:50:17 PM PDT 24
Peak memory 196228 kb
Host smart-8c77addb-65c0-4d79-9427-1727e16fcbee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290888000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.290888000
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2207462164
Short name T630
Test name
Test status
Simulation time 162919004 ps
CPU time 0.84 seconds
Started Jul 06 04:50:09 PM PDT 24
Finished Jul 06 04:50:11 PM PDT 24
Peak memory 196576 kb
Host smart-562e3305-a800-4c51-8bc9-ff578fa56319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207462164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2207462164
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.518702690
Short name T453
Test name
Test status
Simulation time 49527424 ps
CPU time 1.42 seconds
Started Jul 06 04:50:05 PM PDT 24
Finished Jul 06 04:50:07 PM PDT 24
Peak memory 198660 kb
Host smart-9392f593-4907-42d6-a1c2-10bf127d73c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518702690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.518702690
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2989876443
Short name T316
Test name
Test status
Simulation time 349340800 ps
CPU time 3.53 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 198592 kb
Host smart-a566d3da-e5e0-4e19-a51b-24e23d5102cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989876443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2989876443
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.935310114
Short name T227
Test name
Test status
Simulation time 36395359 ps
CPU time 0.92 seconds
Started Jul 06 04:49:54 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 196152 kb
Host smart-048b8155-df88-4ac8-aa5b-b6f60c7aa1bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935310114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
935310114
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1129959136
Short name T162
Test name
Test status
Simulation time 46844128 ps
CPU time 0.68 seconds
Started Jul 06 04:51:06 PM PDT 24
Finished Jul 06 04:51:07 PM PDT 24
Peak memory 196156 kb
Host smart-bcc3e26a-83f4-421c-878f-b231e8a0a66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129959136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1129959136
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.870782034
Short name T60
Test name
Test status
Simulation time 64958708 ps
CPU time 0.73 seconds
Started Jul 06 04:50:01 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 196692 kb
Host smart-48249778-d0e6-427c-9fd3-1288972cb19d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870782034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.870782034
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2811261621
Short name T545
Test name
Test status
Simulation time 154417723 ps
CPU time 3.71 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:22 PM PDT 24
Peak memory 198556 kb
Host smart-e64c4b0d-dbe4-4405-b77e-900ba7be221d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811261621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2811261621
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3418203754
Short name T395
Test name
Test status
Simulation time 144671245 ps
CPU time 1.34 seconds
Started Jul 06 04:49:48 PM PDT 24
Finished Jul 06 04:49:51 PM PDT 24
Peak memory 197528 kb
Host smart-5eb210b9-8dd1-497b-9304-50f7194fbe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418203754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3418203754
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2082091192
Short name T62
Test name
Test status
Simulation time 47119183 ps
CPU time 1.34 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:00 PM PDT 24
Peak memory 198604 kb
Host smart-58d2c12f-570d-4098-9e65-27314e945117
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082091192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2082091192
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1185468199
Short name T147
Test name
Test status
Simulation time 51411395617 ps
CPU time 143.96 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:52:24 PM PDT 24
Peak memory 198684 kb
Host smart-5015386c-67fc-4843-a5a4-8bbef13cc1fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185468199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1185468199
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.4235084212
Short name T27
Test name
Test status
Simulation time 135259522033 ps
CPU time 1422.07 seconds
Started Jul 06 04:50:01 PM PDT 24
Finished Jul 06 05:13:48 PM PDT 24
Peak memory 198980 kb
Host smart-183c8412-a16d-4849-9c63-3eae181fb2dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4235084212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.4235084212
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2991476882
Short name T144
Test name
Test status
Simulation time 14002791 ps
CPU time 0.59 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:50:20 PM PDT 24
Peak memory 194800 kb
Host smart-a6171d33-5ac8-447c-a651-d3fe7e37038a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991476882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2991476882
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2194660786
Short name T521
Test name
Test status
Simulation time 190460695 ps
CPU time 0.83 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 197120 kb
Host smart-3e5b93f1-ac39-4111-b467-2df6be249969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194660786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2194660786
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3918315768
Short name T628
Test name
Test status
Simulation time 5301414767 ps
CPU time 24.47 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:50:23 PM PDT 24
Peak memory 197532 kb
Host smart-b0398294-f5fd-4a10-8af4-3bb145411f3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918315768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3918315768
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.652944561
Short name T479
Test name
Test status
Simulation time 236577823 ps
CPU time 0.84 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 196748 kb
Host smart-15852420-2fac-4184-95cb-fc517c22bc58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652944561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.652944561
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1327661905
Short name T363
Test name
Test status
Simulation time 34466193 ps
CPU time 0.75 seconds
Started Jul 06 04:49:54 PM PDT 24
Finished Jul 06 04:49:55 PM PDT 24
Peak memory 195908 kb
Host smart-780db71f-ead2-4907-a2ce-b411f8b0051c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327661905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1327661905
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2799305764
Short name T181
Test name
Test status
Simulation time 110429304 ps
CPU time 0.93 seconds
Started Jul 06 04:49:56 PM PDT 24
Finished Jul 06 04:49:58 PM PDT 24
Peak memory 196744 kb
Host smart-8e0f8ffc-5193-46ba-b4fe-a873fe37ef1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799305764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2799305764
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2894976402
Short name T269
Test name
Test status
Simulation time 30794444 ps
CPU time 1.06 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:59 PM PDT 24
Peak memory 196148 kb
Host smart-62441a32-386e-457d-a769-574e38304634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894976402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2894976402
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.614774398
Short name T13
Test name
Test status
Simulation time 20982327 ps
CPU time 0.79 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 197104 kb
Host smart-40a27db6-0698-4f42-ad5c-60f8c074c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614774398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.614774398
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.775321743
Short name T662
Test name
Test status
Simulation time 186618561 ps
CPU time 1.06 seconds
Started Jul 06 04:50:10 PM PDT 24
Finished Jul 06 04:50:11 PM PDT 24
Peak memory 197104 kb
Host smart-6e5321ac-dcd0-4861-aff3-40a455ddb4c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775321743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.775321743
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.546476878
Short name T583
Test name
Test status
Simulation time 380126342 ps
CPU time 2.87 seconds
Started Jul 06 04:49:53 PM PDT 24
Finished Jul 06 04:49:57 PM PDT 24
Peak memory 198568 kb
Host smart-38a3002b-5854-4d1f-b6f5-8b45fd9e53e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546476878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.546476878
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.4019841056
Short name T378
Test name
Test status
Simulation time 56684785 ps
CPU time 1.01 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 196348 kb
Host smart-69837bf9-79f2-433d-8d89-31ff85be086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019841056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.4019841056
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2477191867
Short name T113
Test name
Test status
Simulation time 158249978 ps
CPU time 1.15 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 196412 kb
Host smart-e77cebd0-b231-4857-8125-3ec6ee22ed3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477191867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2477191867
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2285652644
Short name T438
Test name
Test status
Simulation time 49344351294 ps
CPU time 80.94 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:51:23 PM PDT 24
Peak memory 198604 kb
Host smart-0a1a53ef-397e-4706-98e7-d6cad4563677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285652644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2285652644
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.909965475
Short name T493
Test name
Test status
Simulation time 23496589 ps
CPU time 0.56 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:50:13 PM PDT 24
Peak memory 194580 kb
Host smart-2a5a7883-17b9-4928-a6e5-0b628b302057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909965475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.909965475
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2580943516
Short name T418
Test name
Test status
Simulation time 28772887 ps
CPU time 0.83 seconds
Started Jul 06 04:49:57 PM PDT 24
Finished Jul 06 04:49:59 PM PDT 24
Peak memory 195560 kb
Host smart-401cac9a-a0b7-4c69-8e4d-6c86fe95ce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580943516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2580943516
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2668306722
Short name T241
Test name
Test status
Simulation time 4401229405 ps
CPU time 13.83 seconds
Started Jul 06 04:49:55 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 197520 kb
Host smart-59860d80-cc5e-4e2b-a6fc-c6a13987abfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668306722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2668306722
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.254410678
Short name T487
Test name
Test status
Simulation time 257162683 ps
CPU time 0.89 seconds
Started Jul 06 04:50:05 PM PDT 24
Finished Jul 06 04:50:07 PM PDT 24
Peak memory 196496 kb
Host smart-be903bd0-b379-481e-a0d7-614ac5a3a425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254410678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.254410678
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.71029097
Short name T432
Test name
Test status
Simulation time 297692144 ps
CPU time 1.38 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:00 PM PDT 24
Peak memory 197284 kb
Host smart-552fc6a9-3a4d-48f4-a623-95b76dc4e40b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71029097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.71029097
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4113065597
Short name T678
Test name
Test status
Simulation time 33192706 ps
CPU time 1.43 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:50:14 PM PDT 24
Peak memory 198696 kb
Host smart-aa19e359-1a51-4511-ab64-0609a498bf38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113065597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4113065597
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2811083310
Short name T455
Test name
Test status
Simulation time 149570125 ps
CPU time 2.75 seconds
Started Jul 06 04:50:16 PM PDT 24
Finished Jul 06 04:50:19 PM PDT 24
Peak memory 196388 kb
Host smart-afd96fca-de4c-4c2a-90d6-54b84647ea20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811083310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2811083310
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1661838510
Short name T302
Test name
Test status
Simulation time 360079784 ps
CPU time 1.28 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 198596 kb
Host smart-302486d5-2b6a-4e2a-a928-326365e987a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661838510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1661838510
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2998509777
Short name T152
Test name
Test status
Simulation time 271217015 ps
CPU time 1.24 seconds
Started Jul 06 04:49:55 PM PDT 24
Finished Jul 06 04:49:56 PM PDT 24
Peak memory 196496 kb
Host smart-4359bd63-a6a2-41c7-854f-22257c1d7ffb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998509777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2998509777
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2812118081
Short name T238
Test name
Test status
Simulation time 115726563 ps
CPU time 2.74 seconds
Started Jul 06 04:50:11 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 198544 kb
Host smart-bed96267-54dd-4632-8e21-3096efbfaa8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812118081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2812118081
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1294912220
Short name T339
Test name
Test status
Simulation time 35372055 ps
CPU time 1.08 seconds
Started Jul 06 04:50:09 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 196120 kb
Host smart-bd920438-8725-4a45-a290-4c886c17a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294912220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1294912220
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3847617896
Short name T205
Test name
Test status
Simulation time 97221841 ps
CPU time 0.95 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 196300 kb
Host smart-414add53-37e8-465e-8d75-aa9e96da8c88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847617896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3847617896
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3027419650
Short name T21
Test name
Test status
Simulation time 31769681858 ps
CPU time 166.8 seconds
Started Jul 06 04:50:10 PM PDT 24
Finished Jul 06 04:52:57 PM PDT 24
Peak memory 198712 kb
Host smart-e4ad726d-6bc3-4973-93d9-aff7d8ba3973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027419650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3027419650
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.482565263
Short name T476
Test name
Test status
Simulation time 514734666808 ps
CPU time 1610.32 seconds
Started Jul 06 04:50:10 PM PDT 24
Finished Jul 06 05:17:01 PM PDT 24
Peak memory 198900 kb
Host smart-e2e6db2f-6f5e-4796-9da9-1d3613ba7f56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=482565263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.482565263
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1483620368
Short name T185
Test name
Test status
Simulation time 13491994 ps
CPU time 0.58 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 194784 kb
Host smart-6c845b23-5897-4594-b22d-eda3b1d6e2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483620368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1483620368
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3665844254
Short name T658
Test name
Test status
Simulation time 66940394 ps
CPU time 0.77 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:00 PM PDT 24
Peak memory 195928 kb
Host smart-c9ff5e3b-7f1e-4979-a906-f7135c381c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665844254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3665844254
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3380365374
Short name T116
Test name
Test status
Simulation time 433382386 ps
CPU time 21.69 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:21 PM PDT 24
Peak memory 197316 kb
Host smart-9dca03e8-188b-4068-99cb-806e5c03a841
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380365374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3380365374
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.54826077
Short name T290
Test name
Test status
Simulation time 98671152 ps
CPU time 0.95 seconds
Started Jul 06 04:50:16 PM PDT 24
Finished Jul 06 04:50:17 PM PDT 24
Peak memory 196716 kb
Host smart-194db7f2-765a-459c-9e89-7d25355988f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54826077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.54826077
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.4161942918
Short name T48
Test name
Test status
Simulation time 20093405 ps
CPU time 0.67 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:04 PM PDT 24
Peak memory 195040 kb
Host smart-d46d8578-156d-47e2-aa9a-9f2be328d313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161942918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.4161942918
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3822477047
Short name T337
Test name
Test status
Simulation time 275582236 ps
CPU time 3.37 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 198632 kb
Host smart-55f8fa1b-a5d1-4607-9ede-8c41d9adc650
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822477047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3822477047
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4089204341
Short name T470
Test name
Test status
Simulation time 158905983 ps
CPU time 1.73 seconds
Started Jul 06 04:50:11 PM PDT 24
Finished Jul 06 04:50:13 PM PDT 24
Peak memory 197372 kb
Host smart-b01bc0bb-da5d-4170-a338-0de305dbf02b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089204341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4089204341
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.320976080
Short name T262
Test name
Test status
Simulation time 232150599 ps
CPU time 0.93 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 197308 kb
Host smart-8cf85e39-b15b-4a07-a6aa-9783930baccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320976080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.320976080
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.276165701
Short name T145
Test name
Test status
Simulation time 128177972 ps
CPU time 1.15 seconds
Started Jul 06 04:50:17 PM PDT 24
Finished Jul 06 04:50:18 PM PDT 24
Peak memory 197156 kb
Host smart-a5706ba0-ac30-4c70-9cb9-ccff2407481b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276165701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.276165701
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2632885505
Short name T260
Test name
Test status
Simulation time 165663075 ps
CPU time 3.87 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 04:50:07 PM PDT 24
Peak memory 198528 kb
Host smart-4bf98425-8696-4d98-996a-87ee76cdeffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632885505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2632885505
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2905248405
Short name T256
Test name
Test status
Simulation time 252099422 ps
CPU time 1.19 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 196372 kb
Host smart-e6691bd0-78c4-49eb-9f59-e4c97be39fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905248405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2905248405
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2207503876
Short name T350
Test name
Test status
Simulation time 44895306 ps
CPU time 1.34 seconds
Started Jul 06 04:50:00 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 197444 kb
Host smart-6bfe8873-92ab-4925-b292-867a43278152
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207503876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2207503876
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3484134170
Short name T708
Test name
Test status
Simulation time 20874891979 ps
CPU time 133.82 seconds
Started Jul 06 04:49:58 PM PDT 24
Finished Jul 06 04:52:14 PM PDT 24
Peak memory 198800 kb
Host smart-37a37469-7486-4a26-b593-d27e4638cee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484134170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3484134170
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3829499445
Short name T57
Test name
Test status
Simulation time 206798867691 ps
CPU time 657.47 seconds
Started Jul 06 04:50:03 PM PDT 24
Finished Jul 06 05:01:01 PM PDT 24
Peak memory 198908 kb
Host smart-f06cb297-e5b9-4e10-9e55-8a0e85f7c22f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3829499445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3829499445
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.673687769
Short name T146
Test name
Test status
Simulation time 16200700 ps
CPU time 0.59 seconds
Started Jul 06 04:50:05 PM PDT 24
Finished Jul 06 04:50:06 PM PDT 24
Peak memory 195472 kb
Host smart-214202fa-345f-4682-8181-eae9e5a5020f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673687769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.673687769
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1791744320
Short name T619
Test name
Test status
Simulation time 115292347 ps
CPU time 0.81 seconds
Started Jul 06 04:50:02 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 195708 kb
Host smart-3cfee85f-8e8a-4126-a29d-79c361b6b672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791744320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1791744320
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3380134126
Short name T474
Test name
Test status
Simulation time 206786599 ps
CPU time 6.47 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:07 PM PDT 24
Peak memory 198576 kb
Host smart-40426dce-5310-4bcd-8e48-ddfb1ee308aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380134126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3380134126
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2324118470
Short name T632
Test name
Test status
Simulation time 767134268 ps
CPU time 0.87 seconds
Started Jul 06 04:50:09 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 197488 kb
Host smart-4734756d-f6f1-439d-925d-54696ee5d9e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324118470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2324118470
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.328633340
Short name T114
Test name
Test status
Simulation time 229101004 ps
CPU time 1.41 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:01 PM PDT 24
Peak memory 196540 kb
Host smart-00c3d630-deac-4b05-84bc-d41002a2ef76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328633340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.328633340
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3250469644
Short name T190
Test name
Test status
Simulation time 90755476 ps
CPU time 3.3 seconds
Started Jul 06 04:50:11 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 198564 kb
Host smart-5c53ad75-20a8-450c-a1df-de457e6d0f9e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250469644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3250469644
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2033051235
Short name T278
Test name
Test status
Simulation time 1269435938 ps
CPU time 2.54 seconds
Started Jul 06 04:50:02 PM PDT 24
Finished Jul 06 04:50:05 PM PDT 24
Peak memory 198568 kb
Host smart-06c577dd-5222-4dc8-a2dc-874408c82bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033051235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2033051235
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2856104075
Short name T498
Test name
Test status
Simulation time 105292697 ps
CPU time 0.95 seconds
Started Jul 06 04:50:01 PM PDT 24
Finished Jul 06 04:50:03 PM PDT 24
Peak memory 197304 kb
Host smart-c1c06e11-aef2-4462-ac43-e70241ff6199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856104075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2856104075
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3915818042
Short name T626
Test name
Test status
Simulation time 25020979 ps
CPU time 0.84 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:28 PM PDT 24
Peak memory 196052 kb
Host smart-10c4f51c-0b58-40f1-86a8-d893f236c741
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915818042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3915818042
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2676701924
Short name T452
Test name
Test status
Simulation time 3648195842 ps
CPU time 6.02 seconds
Started Jul 06 04:50:08 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 198628 kb
Host smart-084a51c9-059d-4a6d-9cef-9dd3bc79ff37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676701924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2676701924
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.883161736
Short name T464
Test name
Test status
Simulation time 48387655 ps
CPU time 1 seconds
Started Jul 06 04:49:59 PM PDT 24
Finished Jul 06 04:50:02 PM PDT 24
Peak memory 196860 kb
Host smart-44d9475e-4349-4308-9b4a-def30f05395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883161736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.883161736
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1728227905
Short name T253
Test name
Test status
Simulation time 90860102 ps
CPU time 1.17 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 196428 kb
Host smart-53f13a15-e549-4302-a1f9-eaa533b126c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728227905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1728227905
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.974957011
Short name T581
Test name
Test status
Simulation time 3874697983 ps
CPU time 52.06 seconds
Started Jul 06 04:50:33 PM PDT 24
Finished Jul 06 04:51:25 PM PDT 24
Peak memory 198704 kb
Host smart-8fcad7e4-bf84-4ddc-8887-4cfe21b86c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974957011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.974957011
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.268451832
Short name T320
Test name
Test status
Simulation time 40146154 ps
CPU time 0.6 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:09 PM PDT 24
Peak memory 194844 kb
Host smart-fe8e673c-a7b9-40d7-a2e0-5722a2875b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268451832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.268451832
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1332386541
Short name T374
Test name
Test status
Simulation time 29330663 ps
CPU time 0.95 seconds
Started Jul 06 04:50:06 PM PDT 24
Finished Jul 06 04:50:08 PM PDT 24
Peak memory 196432 kb
Host smart-e3b1459b-8f4b-469d-84ce-57f89f8a2ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332386541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1332386541
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3387241947
Short name T466
Test name
Test status
Simulation time 404308843 ps
CPU time 14.55 seconds
Started Jul 06 04:50:11 PM PDT 24
Finished Jul 06 04:50:27 PM PDT 24
Peak memory 197420 kb
Host smart-37fc53a0-41de-4962-ab3f-e68248527058
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387241947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3387241947
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2581036722
Short name T405
Test name
Test status
Simulation time 181559307 ps
CPU time 0.68 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:19 PM PDT 24
Peak memory 195076 kb
Host smart-c591217d-65e0-4be4-8c00-d3eebfdebb67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581036722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2581036722
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2837249094
Short name T653
Test name
Test status
Simulation time 146979531 ps
CPU time 0.95 seconds
Started Jul 06 04:50:25 PM PDT 24
Finished Jul 06 04:50:26 PM PDT 24
Peak memory 198060 kb
Host smart-929d1487-9271-4590-9877-65f5ccf413bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837249094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2837249094
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2403267482
Short name T326
Test name
Test status
Simulation time 22794744 ps
CPU time 1.09 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:32 PM PDT 24
Peak memory 196540 kb
Host smart-adca785d-5497-435e-a3c2-1e5dd23ff1d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403267482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2403267482
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3910478313
Short name T325
Test name
Test status
Simulation time 26993828 ps
CPU time 0.94 seconds
Started Jul 06 04:50:26 PM PDT 24
Finished Jul 06 04:50:27 PM PDT 24
Peak memory 196160 kb
Host smart-6f8d50cf-7ff3-42d9-8ca1-60dcc7506bed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910478313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3910478313
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3134308715
Short name T282
Test name
Test status
Simulation time 40643100 ps
CPU time 0.88 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:19 PM PDT 24
Peak memory 196628 kb
Host smart-62d77023-85a6-40a4-bef9-5de7725ee410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134308715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3134308715
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.189645221
Short name T261
Test name
Test status
Simulation time 654703548 ps
CPU time 1.16 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:32 PM PDT 24
Peak memory 197408 kb
Host smart-0a0cef96-b31b-4b4a-9b46-b2d4819796f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189645221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.189645221
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.467642713
Short name T396
Test name
Test status
Simulation time 278347326 ps
CPU time 4.76 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:50:17 PM PDT 24
Peak memory 197944 kb
Host smart-cb09a222-a6c8-48f4-a1ad-f0e85bfdfc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467642713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ran
dom_long_reg_writes_reg_reads.467642713
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.785934528
Short name T276
Test name
Test status
Simulation time 131679780 ps
CPU time 1.13 seconds
Started Jul 06 04:50:06 PM PDT 24
Finished Jul 06 04:50:08 PM PDT 24
Peak memory 196408 kb
Host smart-f3fabc6f-a047-431c-ab40-2056046fafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785934528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.785934528
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3013173824
Short name T128
Test name
Test status
Simulation time 54690708 ps
CPU time 1.12 seconds
Started Jul 06 04:50:08 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 196488 kb
Host smart-aa03067d-1ee0-40ea-b95a-325f9e42c308
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013173824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3013173824
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2287132185
Short name T574
Test name
Test status
Simulation time 28314953864 ps
CPU time 196.69 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:53:30 PM PDT 24
Peak memory 198680 kb
Host smart-2ef16553-9577-41c2-9fa0-23702e54304d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287132185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2287132185
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3097468104
Short name T394
Test name
Test status
Simulation time 279697817587 ps
CPU time 1298.8 seconds
Started Jul 06 04:50:23 PM PDT 24
Finished Jul 06 05:12:02 PM PDT 24
Peak memory 198844 kb
Host smart-f5b0df55-f442-4d47-9b2e-0d883c6f1aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3097468104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3097468104
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1447856800
Short name T586
Test name
Test status
Simulation time 13172842 ps
CPU time 0.58 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:14 PM PDT 24
Peak memory 194532 kb
Host smart-49d94849-28c0-4f42-abf7-70bd578668f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447856800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1447856800
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3531392152
Short name T155
Test name
Test status
Simulation time 61414459 ps
CPU time 0.67 seconds
Started Jul 06 04:49:01 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 194616 kb
Host smart-51bf65cb-5b27-4ae7-be34-9ac8ef1885e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531392152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3531392152
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1439678377
Short name T130
Test name
Test status
Simulation time 598842205 ps
CPU time 10.5 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:25 PM PDT 24
Peak memory 196860 kb
Host smart-1841b26c-fb9d-4cd8-8ca7-f478411eeffe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439678377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1439678377
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3391178899
Short name T148
Test name
Test status
Simulation time 175402195 ps
CPU time 0.82 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 197348 kb
Host smart-44c5b0ea-8ab8-4348-b38b-92e690aa6b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391178899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3391178899
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.472401645
Short name T225
Test name
Test status
Simulation time 47474128 ps
CPU time 0.92 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 196212 kb
Host smart-5f5ce0f2-d7e3-4dd0-adfc-e2be6456cb3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472401645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.472401645
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.266735783
Short name T473
Test name
Test status
Simulation time 196795634 ps
CPU time 1.55 seconds
Started Jul 06 04:49:04 PM PDT 24
Finished Jul 06 04:49:06 PM PDT 24
Peak memory 197424 kb
Host smart-b0c7a13b-35d4-4be9-8e7a-2763358f8502
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266735783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.266735783
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.674075649
Short name T575
Test name
Test status
Simulation time 453635205 ps
CPU time 3.61 seconds
Started Jul 06 04:48:57 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 197868 kb
Host smart-845ea95c-9324-4f37-b38c-37fa003641c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674075649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.674075649
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1104464289
Short name T612
Test name
Test status
Simulation time 270040321 ps
CPU time 1.18 seconds
Started Jul 06 04:48:57 PM PDT 24
Finished Jul 06 04:48:59 PM PDT 24
Peak memory 197176 kb
Host smart-933b2fce-7a2e-45cb-88e9-d6914fee41f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104464289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1104464289
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1591705075
Short name T228
Test name
Test status
Simulation time 57613939 ps
CPU time 1.12 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 197132 kb
Host smart-bf00828e-1dee-4e9e-8f54-223cc78d7843
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591705075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1591705075
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1933805343
Short name T371
Test name
Test status
Simulation time 54379569 ps
CPU time 1.21 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 198664 kb
Host smart-26a5059e-be9e-454e-8c45-8c05162902d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933805343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1933805343
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2994463330
Short name T33
Test name
Test status
Simulation time 156437428 ps
CPU time 0.9 seconds
Started Jul 06 04:48:58 PM PDT 24
Finished Jul 06 04:49:00 PM PDT 24
Peak memory 214204 kb
Host smart-d39b242e-8863-489d-8d0d-3b3aa7c78d91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994463330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2994463330
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1513350408
Short name T451
Test name
Test status
Simulation time 44087998 ps
CPU time 0.95 seconds
Started Jul 06 04:48:56 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 195820 kb
Host smart-23463a1f-ac7c-42be-aaff-8b9a697bbe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513350408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1513350408
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1017072509
Short name T218
Test name
Test status
Simulation time 33358988 ps
CPU time 1.07 seconds
Started Jul 06 04:48:55 PM PDT 24
Finished Jul 06 04:48:57 PM PDT 24
Peak memory 196300 kb
Host smart-7e749601-88c9-4f6c-ad25-028f92ac1a80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017072509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1017072509
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3803408347
Short name T478
Test name
Test status
Simulation time 5480546833 ps
CPU time 144.67 seconds
Started Jul 06 04:49:01 PM PDT 24
Finished Jul 06 04:51:26 PM PDT 24
Peak memory 198676 kb
Host smart-e50a66f9-53ba-41c3-9664-6e227d43ad09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803408347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3803408347
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3859742110
Short name T648
Test name
Test status
Simulation time 23046658 ps
CPU time 0.58 seconds
Started Jul 06 04:50:11 PM PDT 24
Finished Jul 06 04:50:12 PM PDT 24
Peak memory 195560 kb
Host smart-06888a88-4a9e-41cf-8f4b-68e045c2f870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859742110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3859742110
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.256597311
Short name T528
Test name
Test status
Simulation time 416003352 ps
CPU time 0.84 seconds
Started Jul 06 04:50:08 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 197820 kb
Host smart-2e2ba2da-4a3e-4217-8a3d-1146cdb47b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256597311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.256597311
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.17539665
Short name T486
Test name
Test status
Simulation time 3672981604 ps
CPU time 29.95 seconds
Started Jul 06 04:50:15 PM PDT 24
Finished Jul 06 04:50:45 PM PDT 24
Peak memory 198684 kb
Host smart-a82cdd42-2307-4067-8589-390781c69833
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17539665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stress
.17539665
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4024965077
Short name T321
Test name
Test status
Simulation time 45654585 ps
CPU time 0.89 seconds
Started Jul 06 04:50:15 PM PDT 24
Finished Jul 06 04:50:16 PM PDT 24
Peak memory 197704 kb
Host smart-03fea748-039a-4d23-89a5-e22f440e0d59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024965077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4024965077
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1594170281
Short name T368
Test name
Test status
Simulation time 638601014 ps
CPU time 0.95 seconds
Started Jul 06 04:50:25 PM PDT 24
Finished Jul 06 04:50:26 PM PDT 24
Peak memory 197244 kb
Host smart-abd4f355-0ab8-4250-901b-17478f8f1cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594170281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1594170281
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.942306608
Short name T108
Test name
Test status
Simulation time 169881561 ps
CPU time 2.36 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:38 PM PDT 24
Peak memory 197860 kb
Host smart-d3a08a16-26ed-46e5-a165-81784b7850dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942306608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.942306608
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1262044775
Short name T433
Test name
Test status
Simulation time 481631629 ps
CPU time 2.97 seconds
Started Jul 06 04:50:09 PM PDT 24
Finished Jul 06 04:50:12 PM PDT 24
Peak memory 198704 kb
Host smart-2f7bf941-518a-4494-9a9c-c8cbf53bb3ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262044775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1262044775
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.197565817
Short name T711
Test name
Test status
Simulation time 73844271 ps
CPU time 1.26 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:50:13 PM PDT 24
Peak memory 195760 kb
Host smart-2bc20dfa-672d-403a-946b-bb93500029ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197565817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.197565817
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2381779011
Short name T275
Test name
Test status
Simulation time 803806590 ps
CPU time 1.08 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:50:14 PM PDT 24
Peak memory 197348 kb
Host smart-c4f35d49-4839-49fe-b186-205325a74027
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381779011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2381779011
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3115326008
Short name T344
Test name
Test status
Simulation time 116126137 ps
CPU time 1.93 seconds
Started Jul 06 04:50:08 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 198632 kb
Host smart-3289f76c-3075-4a97-9688-66e4a9a46e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115326008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3115326008
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2375263860
Short name T163
Test name
Test status
Simulation time 28118814 ps
CPU time 1.06 seconds
Started Jul 06 04:50:07 PM PDT 24
Finished Jul 06 04:50:08 PM PDT 24
Peak memory 196344 kb
Host smart-37adacf2-05ed-4737-90bc-a49871513e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375263860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2375263860
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2367760227
Short name T645
Test name
Test status
Simulation time 128193145 ps
CPU time 1.23 seconds
Started Jul 06 04:50:09 PM PDT 24
Finished Jul 06 04:50:10 PM PDT 24
Peak memory 197208 kb
Host smart-215c24b9-25b9-403e-90fc-f39cd7033d24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367760227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2367760227
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2450921597
Short name T236
Test name
Test status
Simulation time 30540184035 ps
CPU time 199.76 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:53:33 PM PDT 24
Peak memory 198688 kb
Host smart-2fc203a6-fa34-4de8-a715-66b54e617d2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450921597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2450921597
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.283230088
Short name T655
Test name
Test status
Simulation time 154407110054 ps
CPU time 1437.72 seconds
Started Jul 06 04:50:31 PM PDT 24
Finished Jul 06 05:14:29 PM PDT 24
Peak memory 198892 kb
Host smart-346c5db3-46d3-436a-a34a-32f7dfa445c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=283230088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.283230088
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.358374344
Short name T203
Test name
Test status
Simulation time 12593370 ps
CPU time 0.59 seconds
Started Jul 06 04:50:20 PM PDT 24
Finished Jul 06 04:50:21 PM PDT 24
Peak memory 194592 kb
Host smart-20930a9d-4974-42a6-b888-96e1d7497740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358374344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.358374344
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1667120047
Short name T681
Test name
Test status
Simulation time 207683296 ps
CPU time 0.9 seconds
Started Jul 06 04:50:14 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 197944 kb
Host smart-0cd51944-aabd-489f-909c-b061cd795696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667120047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1667120047
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1200381942
Short name T340
Test name
Test status
Simulation time 487637754 ps
CPU time 12.44 seconds
Started Jul 06 04:50:21 PM PDT 24
Finished Jul 06 04:50:34 PM PDT 24
Peak memory 197540 kb
Host smart-86308c60-98ec-493f-99f0-5f23543d776f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200381942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1200381942
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1684004564
Short name T197
Test name
Test status
Simulation time 173235415 ps
CPU time 0.82 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:50:20 PM PDT 24
Peak memory 197132 kb
Host smart-756d197b-8b4c-4143-807f-e625d2cb2960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684004564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1684004564
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.71951853
Short name T677
Test name
Test status
Simulation time 34578358 ps
CPU time 0.9 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:20 PM PDT 24
Peak memory 196372 kb
Host smart-6c250639-1567-4fdf-853b-bf3ea135b2e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71951853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.71951853
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3352516139
Short name T518
Test name
Test status
Simulation time 249674255 ps
CPU time 2.94 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:42 PM PDT 24
Peak memory 198648 kb
Host smart-3e357420-131f-441b-8ba0-906c8ef7921d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352516139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3352516139
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3627265005
Short name T74
Test name
Test status
Simulation time 74912535 ps
CPU time 2.39 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 198748 kb
Host smart-aab8fc91-ca86-4003-a888-bf51c7f6f888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627265005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3627265005
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.581465593
Short name T270
Test name
Test status
Simulation time 26208999 ps
CPU time 0.94 seconds
Started Jul 06 04:50:15 PM PDT 24
Finished Jul 06 04:50:16 PM PDT 24
Peak memory 196640 kb
Host smart-dd51549d-9fb1-4672-89c1-de0b3acd26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581465593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.581465593
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.483884260
Short name T663
Test name
Test status
Simulation time 70461784 ps
CPU time 0.81 seconds
Started Jul 06 04:50:22 PM PDT 24
Finished Jul 06 04:50:23 PM PDT 24
Peak memory 196116 kb
Host smart-eaa74236-538c-4af9-9f61-e17c47b5822b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483884260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.483884260
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.374760030
Short name T526
Test name
Test status
Simulation time 35872212 ps
CPU time 1.54 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 198552 kb
Host smart-0f0c95ce-9c86-43cc-ad14-c31c152447cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374760030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.374760030
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1693540052
Short name T431
Test name
Test status
Simulation time 62392348 ps
CPU time 1.18 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 196836 kb
Host smart-1be9894c-3466-4308-98f2-4ddd180b2366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693540052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1693540052
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2685619822
Short name T206
Test name
Test status
Simulation time 67290091 ps
CPU time 0.95 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:50:21 PM PDT 24
Peak memory 196192 kb
Host smart-e0fdf7a7-bd54-4859-b9c8-c49e8adc9b61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685619822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2685619822
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.671458462
Short name T399
Test name
Test status
Simulation time 4912330150 ps
CPU time 53.28 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:51:11 PM PDT 24
Peak memory 198728 kb
Host smart-2044fa4b-6204-49a3-b658-c9c3bae8cb51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671458462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.671458462
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.93628872
Short name T54
Test name
Test status
Simulation time 85388738275 ps
CPU time 581.94 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 05:00:01 PM PDT 24
Peak memory 198860 kb
Host smart-622ea5ec-9ecc-4b29-b491-3b915f05cf56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=93628872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.93628872
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2648329527
Short name T42
Test name
Test status
Simulation time 43971131 ps
CPU time 0.55 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 195272 kb
Host smart-4e359bb2-b131-4147-946c-f55390d31f79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648329527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2648329527
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.385003288
Short name T279
Test name
Test status
Simulation time 106113713 ps
CPU time 0.86 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 196908 kb
Host smart-be970eed-1a31-4966-8db6-6a28f78bbb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385003288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.385003288
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4171734799
Short name T319
Test name
Test status
Simulation time 1500539652 ps
CPU time 18.46 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 198728 kb
Host smart-d75d62d4-4eb9-4122-97b9-ebf5221f02e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171734799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4171734799
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2485104130
Short name T571
Test name
Test status
Simulation time 102318353 ps
CPU time 0.77 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:40 PM PDT 24
Peak memory 197196 kb
Host smart-a5186923-48c0-41c7-b4ef-57450d2dcf06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485104130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2485104130
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.754651619
Short name T271
Test name
Test status
Simulation time 19530357 ps
CPU time 0.82 seconds
Started Jul 06 04:50:12 PM PDT 24
Finished Jul 06 04:50:14 PM PDT 24
Peak memory 196156 kb
Host smart-ef00c463-a4a2-4dc9-8689-04b53d7e65a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754651619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.754651619
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2391323707
Short name T314
Test name
Test status
Simulation time 36629257 ps
CPU time 1.56 seconds
Started Jul 06 04:50:26 PM PDT 24
Finished Jul 06 04:50:27 PM PDT 24
Peak memory 196988 kb
Host smart-7dc4b2fb-f026-4683-b2e3-a5fb26ef3aed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391323707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2391323707
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.791093691
Short name T585
Test name
Test status
Simulation time 78456583 ps
CPU time 2.3 seconds
Started Jul 06 04:50:15 PM PDT 24
Finished Jul 06 04:50:17 PM PDT 24
Peak memory 197712 kb
Host smart-b75bda19-2797-41f6-b8fb-c1457eaaa87b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791093691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
791093691
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.4245047637
Short name T714
Test name
Test status
Simulation time 63838619 ps
CPU time 1.24 seconds
Started Jul 06 04:50:20 PM PDT 24
Finished Jul 06 04:50:22 PM PDT 24
Peak memory 197632 kb
Host smart-d1b2a62e-e0a2-4bda-bd19-697e58c55d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245047637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.4245047637
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.195971563
Short name T178
Test name
Test status
Simulation time 207155827 ps
CPU time 1.22 seconds
Started Jul 06 04:50:24 PM PDT 24
Finished Jul 06 04:50:25 PM PDT 24
Peak memory 197120 kb
Host smart-8239d4d7-46b7-4b53-87aa-920bb388da1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195971563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.195971563
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3831452571
Short name T234
Test name
Test status
Simulation time 29195005 ps
CPU time 1.18 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:20 PM PDT 24
Peak memory 198468 kb
Host smart-8adddfb0-13b3-4e49-97da-395c0019f548
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831452571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3831452571
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3224477342
Short name T328
Test name
Test status
Simulation time 92699817 ps
CPU time 1.44 seconds
Started Jul 06 04:50:13 PM PDT 24
Finished Jul 06 04:50:15 PM PDT 24
Peak memory 196172 kb
Host smart-598c90ee-b3e4-4fc4-b10d-f40202a399ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224477342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3224477342
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3399985743
Short name T175
Test name
Test status
Simulation time 24577044 ps
CPU time 0.69 seconds
Started Jul 06 04:50:23 PM PDT 24
Finished Jul 06 04:50:24 PM PDT 24
Peak memory 194820 kb
Host smart-d800ab35-81b0-4e31-bf66-425c80b33837
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399985743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3399985743
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2676351250
Short name T552
Test name
Test status
Simulation time 3246531503 ps
CPU time 45.62 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:51:05 PM PDT 24
Peak memory 198728 kb
Host smart-57d33f69-4f40-484f-9a06-5ba69359d0ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676351250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2676351250
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.972709045
Short name T351
Test name
Test status
Simulation time 44197544 ps
CPU time 0.66 seconds
Started Jul 06 04:50:24 PM PDT 24
Finished Jul 06 04:50:25 PM PDT 24
Peak memory 195424 kb
Host smart-46800449-4b65-4b8e-ba7c-19c5ed9f0827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972709045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.972709045
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.4087063863
Short name T188
Test name
Test status
Simulation time 24602143 ps
CPU time 0.76 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:40 PM PDT 24
Peak memory 195924 kb
Host smart-4f40c791-555f-438c-84e0-b655ee21adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087063863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.4087063863
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3463981139
Short name T120
Test name
Test status
Simulation time 2202799692 ps
CPU time 22.16 seconds
Started Jul 06 04:50:31 PM PDT 24
Finished Jul 06 04:50:53 PM PDT 24
Peak memory 197672 kb
Host smart-85969583-ac07-4c1d-86b3-b213abb4d74e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463981139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3463981139
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1893363195
Short name T597
Test name
Test status
Simulation time 40135935 ps
CPU time 0.72 seconds
Started Jul 06 04:50:28 PM PDT 24
Finished Jul 06 04:50:29 PM PDT 24
Peak memory 195292 kb
Host smart-11932a07-c974-4173-9e39-479da1163bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893363195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1893363195
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2547260845
Short name T638
Test name
Test status
Simulation time 82173465 ps
CPU time 0.71 seconds
Started Jul 06 04:50:22 PM PDT 24
Finished Jul 06 04:50:23 PM PDT 24
Peak memory 194872 kb
Host smart-f5c3bcab-4741-4d3b-838b-08052a46ac6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547260845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2547260845
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1105510886
Short name T332
Test name
Test status
Simulation time 229308066 ps
CPU time 2.27 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:21 PM PDT 24
Peak memory 198592 kb
Host smart-cd421c9d-e228-45f1-86ab-80745a5cbcc4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105510886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1105510886
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1994665129
Short name T265
Test name
Test status
Simulation time 40440889 ps
CPU time 1.19 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 196032 kb
Host smart-940a6c3f-2f12-4049-b6e6-950636311313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994665129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1994665129
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2487248030
Short name T277
Test name
Test status
Simulation time 460560488 ps
CPU time 0.82 seconds
Started Jul 06 04:50:23 PM PDT 24
Finished Jul 06 04:50:24 PM PDT 24
Peak memory 196164 kb
Host smart-b281b000-5ab3-4fcb-bb12-96b10f0c9a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487248030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2487248030
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1435908892
Short name T239
Test name
Test status
Simulation time 318095364 ps
CPU time 1.36 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:31 PM PDT 24
Peak memory 197684 kb
Host smart-619755bd-b228-4352-8417-ef52b821960c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435908892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1435908892
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3572687219
Short name T702
Test name
Test status
Simulation time 97163135 ps
CPU time 1.83 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:50:21 PM PDT 24
Peak memory 198576 kb
Host smart-7beeef59-7732-48ab-9664-ccc13d1f7088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572687219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3572687219
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4129153243
Short name T482
Test name
Test status
Simulation time 216643426 ps
CPU time 1.15 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:20 PM PDT 24
Peak memory 196512 kb
Host smart-45361a1c-578f-4814-87a6-5072e6867d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129153243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4129153243
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1180731777
Short name T503
Test name
Test status
Simulation time 67476674 ps
CPU time 1.28 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:20 PM PDT 24
Peak memory 196860 kb
Host smart-0ff9c1cd-249b-41ce-9464-7f1971b14e55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180731777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1180731777
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.195104483
Short name T707
Test name
Test status
Simulation time 2382641170 ps
CPU time 30.03 seconds
Started Jul 06 04:50:31 PM PDT 24
Finished Jul 06 04:51:01 PM PDT 24
Peak memory 198648 kb
Host smart-cb3334ce-db71-4912-9754-16a2cc24ae83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195104483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.195104483
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2985083714
Short name T513
Test name
Test status
Simulation time 511944169758 ps
CPU time 3016.23 seconds
Started Jul 06 04:50:24 PM PDT 24
Finished Jul 06 05:40:41 PM PDT 24
Peak memory 198920 kb
Host smart-484b9a74-e571-4696-ae4d-f3d9fa966586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2985083714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2985083714
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.564157778
Short name T533
Test name
Test status
Simulation time 13018688 ps
CPU time 0.55 seconds
Started Jul 06 04:50:24 PM PDT 24
Finished Jul 06 04:50:25 PM PDT 24
Peak memory 194568 kb
Host smart-8f17ab0b-4409-4714-8dd7-2ecbf6603580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564157778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.564157778
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3018141652
Short name T577
Test name
Test status
Simulation time 38735306 ps
CPU time 0.6 seconds
Started Jul 06 04:50:20 PM PDT 24
Finished Jul 06 04:50:21 PM PDT 24
Peak memory 195224 kb
Host smart-519a5f16-7c9f-4c93-8648-2b431f1af872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018141652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3018141652
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4087001773
Short name T416
Test name
Test status
Simulation time 789253597 ps
CPU time 12.24 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:48 PM PDT 24
Peak memory 197832 kb
Host smart-c37deb9b-33a1-4bf2-b4fa-529eda415847
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087001773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4087001773
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2235076081
Short name T620
Test name
Test status
Simulation time 273277900 ps
CPU time 0.92 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:41 PM PDT 24
Peak memory 197744 kb
Host smart-b9990803-97f9-4257-8906-a5c86dedbed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235076081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2235076081
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.499338362
Short name T409
Test name
Test status
Simulation time 249952249 ps
CPU time 0.81 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:37 PM PDT 24
Peak memory 196876 kb
Host smart-17c23aa9-e227-4038-a587-7acc316aad76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499338362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.499338362
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3169960714
Short name T668
Test name
Test status
Simulation time 207098268 ps
CPU time 2.44 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:32 PM PDT 24
Peak memory 198616 kb
Host smart-333049b8-5869-4804-91f4-c1bb56f45872
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169960714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3169960714
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2360940984
Short name T156
Test name
Test status
Simulation time 869454499 ps
CPU time 3.23 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:50:23 PM PDT 24
Peak memory 198636 kb
Host smart-c052ab91-bfe0-4a91-a2e5-8f4d44c9ab07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360940984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2360940984
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2141144315
Short name T390
Test name
Test status
Simulation time 71288531 ps
CPU time 0.93 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 196632 kb
Host smart-80c3d7f7-d0c6-49e4-9304-1f02b3c7859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141144315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2141144315
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1150295417
Short name T584
Test name
Test status
Simulation time 65495822 ps
CPU time 0.76 seconds
Started Jul 06 04:50:18 PM PDT 24
Finished Jul 06 04:50:19 PM PDT 24
Peak memory 195952 kb
Host smart-330d45bd-b4a4-4362-89fc-7a8937893824
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150295417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1150295417
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.689637374
Short name T634
Test name
Test status
Simulation time 524765784 ps
CPU time 3.27 seconds
Started Jul 06 04:50:19 PM PDT 24
Finished Jul 06 04:50:23 PM PDT 24
Peak memory 198556 kb
Host smart-a0002d4e-5427-48c1-9d8a-cc7acc36f094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689637374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.689637374
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.38094380
Short name T299
Test name
Test status
Simulation time 40148242 ps
CPU time 0.88 seconds
Started Jul 06 04:50:47 PM PDT 24
Finished Jul 06 04:50:48 PM PDT 24
Peak memory 196928 kb
Host smart-b69baefb-6b2d-4a9f-9e85-7df1573f74a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38094380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.38094380
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1065451812
Short name T158
Test name
Test status
Simulation time 173836220 ps
CPU time 0.96 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:50:42 PM PDT 24
Peak memory 196888 kb
Host smart-00f29982-f8ab-4e26-b6c9-e91f98677633
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065451812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1065451812
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3440370351
Short name T14
Test name
Test status
Simulation time 3590969151 ps
CPU time 96.37 seconds
Started Jul 06 04:50:22 PM PDT 24
Finished Jul 06 04:51:59 PM PDT 24
Peak memory 198720 kb
Host smart-01221b15-c3f8-4182-a02e-b2036f637072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440370351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3440370351
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3031818220
Short name T401
Test name
Test status
Simulation time 20171234 ps
CPU time 0.59 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:40 PM PDT 24
Peak memory 194600 kb
Host smart-809b1502-0d70-4b4e-9cf4-7de3f2f64cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031818220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3031818220
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2118960934
Short name T514
Test name
Test status
Simulation time 41331590 ps
CPU time 0.88 seconds
Started Jul 06 04:50:21 PM PDT 24
Finished Jul 06 04:50:22 PM PDT 24
Peak memory 197756 kb
Host smart-251505d1-5f95-42e2-aa87-69ddf7308ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118960934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2118960934
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.908683145
Short name T25
Test name
Test status
Simulation time 1571194732 ps
CPU time 21.18 seconds
Started Jul 06 04:50:33 PM PDT 24
Finished Jul 06 04:50:54 PM PDT 24
Peak memory 198552 kb
Host smart-10dd6667-3f35-4d46-bc5a-0c4e83785a4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908683145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.908683145
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.176647573
Short name T201
Test name
Test status
Simulation time 54081894 ps
CPU time 0.95 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:50:42 PM PDT 24
Peak memory 198256 kb
Host smart-95729eec-976c-465e-9e9e-db69251083db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176647573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.176647573
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2636572805
Short name T425
Test name
Test status
Simulation time 67396631 ps
CPU time 1.16 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:41 PM PDT 24
Peak memory 197380 kb
Host smart-ec2c923e-f2dd-44cf-adfb-9ad385c7ba45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636572805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2636572805
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1820847369
Short name T250
Test name
Test status
Simulation time 50822659 ps
CPU time 1.27 seconds
Started Jul 06 04:50:24 PM PDT 24
Finished Jul 06 04:50:25 PM PDT 24
Peak memory 197524 kb
Host smart-ce36a708-680c-4ae4-9976-243757e0517c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820847369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1820847369
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3368757401
Short name T548
Test name
Test status
Simulation time 127283756 ps
CPU time 0.93 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:50:41 PM PDT 24
Peak memory 197264 kb
Host smart-f48d46c1-dc15-487a-aa71-1ca1f7533104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368757401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3368757401
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.506329425
Short name T599
Test name
Test status
Simulation time 43992008 ps
CPU time 0.83 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:50:41 PM PDT 24
Peak memory 197924 kb
Host smart-c2e51c91-efdb-4fa1-a4c9-0a666325e5df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506329425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.506329425
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2238464636
Short name T541
Test name
Test status
Simulation time 190050839 ps
CPU time 2.28 seconds
Started Jul 06 04:50:38 PM PDT 24
Finished Jul 06 04:50:41 PM PDT 24
Peak memory 198580 kb
Host smart-38ec5cc0-d72e-48c4-8ce9-fbb989c6ea1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238464636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2238464636
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4279651234
Short name T484
Test name
Test status
Simulation time 45014764 ps
CPU time 1.11 seconds
Started Jul 06 04:50:31 PM PDT 24
Finished Jul 06 04:50:32 PM PDT 24
Peak memory 196852 kb
Host smart-465b4461-731f-4196-af34-9d61dfde9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279651234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4279651234
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3791673151
Short name T200
Test name
Test status
Simulation time 684451575 ps
CPU time 1.42 seconds
Started Jul 06 04:50:20 PM PDT 24
Finished Jul 06 04:50:22 PM PDT 24
Peak memory 198544 kb
Host smart-13079d85-d979-4efa-81c2-630583f31610
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791673151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3791673151
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.827187079
Short name T6
Test name
Test status
Simulation time 1754821686 ps
CPU time 22.98 seconds
Started Jul 06 04:50:22 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 198632 kb
Host smart-ebdd9d6d-d7e0-4bf5-a9f3-abef3cbd0492
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827187079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.827187079
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3887518428
Short name T357
Test name
Test status
Simulation time 14664040 ps
CPU time 0.6 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 195628 kb
Host smart-5a42439e-2edd-4b16-8dc6-aa509618e82c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887518428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3887518428
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.175987602
Short name T579
Test name
Test status
Simulation time 153924494 ps
CPU time 0.87 seconds
Started Jul 06 04:50:32 PM PDT 24
Finished Jul 06 04:50:34 PM PDT 24
Peak memory 195828 kb
Host smart-8df608b0-78e9-43b2-8628-4ff0688d9a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175987602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.175987602
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.642917859
Short name T457
Test name
Test status
Simulation time 744707791 ps
CPU time 11.13 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:47 PM PDT 24
Peak memory 196740 kb
Host smart-c8a3bfdd-315c-4009-b1c2-cbc081270df1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642917859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.642917859
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2984274194
Short name T543
Test name
Test status
Simulation time 73782234 ps
CPU time 0.94 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 197004 kb
Host smart-ba965d66-e321-4f95-9fec-7d00ffabd571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984274194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2984274194
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2479308285
Short name T184
Test name
Test status
Simulation time 579529527 ps
CPU time 0.73 seconds
Started Jul 06 04:50:26 PM PDT 24
Finished Jul 06 04:50:27 PM PDT 24
Peak memory 196748 kb
Host smart-0c0073e1-b2e3-4a12-a47b-75046deb0399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479308285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2479308285
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.990993270
Short name T701
Test name
Test status
Simulation time 371808039 ps
CPU time 2.47 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:50:49 PM PDT 24
Peak memory 198408 kb
Host smart-b682052f-66f9-453f-a569-4459c8d6a416
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990993270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.990993270
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1804495371
Short name T613
Test name
Test status
Simulation time 33669428 ps
CPU time 0.98 seconds
Started Jul 06 04:50:34 PM PDT 24
Finished Jul 06 04:50:36 PM PDT 24
Peak memory 196276 kb
Host smart-1086ed2b-af26-4f95-b721-99c6127ab55f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804495371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1804495371
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3408768703
Short name T519
Test name
Test status
Simulation time 77174393 ps
CPU time 0.67 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:36 PM PDT 24
Peak memory 196048 kb
Host smart-81336721-c483-44ee-b7e9-07794e67c932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408768703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3408768703
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3690371505
Short name T376
Test name
Test status
Simulation time 31818854 ps
CPU time 0.84 seconds
Started Jul 06 04:50:26 PM PDT 24
Finished Jul 06 04:50:27 PM PDT 24
Peak memory 196668 kb
Host smart-3b47f486-28a4-47e1-be44-71fe70ac0264
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690371505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3690371505
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1591459201
Short name T555
Test name
Test status
Simulation time 33879983 ps
CPU time 1.65 seconds
Started Jul 06 04:50:25 PM PDT 24
Finished Jul 06 04:50:27 PM PDT 24
Peak memory 198668 kb
Host smart-eda2bb87-a743-4a16-9971-238720213727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591459201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1591459201
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.205270721
Short name T666
Test name
Test status
Simulation time 36611014 ps
CPU time 1 seconds
Started Jul 06 04:50:21 PM PDT 24
Finished Jul 06 04:50:22 PM PDT 24
Peak memory 196560 kb
Host smart-d4eaa53a-c55a-4fbc-ae2c-65e19486cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205270721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.205270721
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3984315185
Short name T622
Test name
Test status
Simulation time 153298172 ps
CPU time 0.94 seconds
Started Jul 06 04:50:34 PM PDT 24
Finished Jul 06 04:50:35 PM PDT 24
Peak memory 197556 kb
Host smart-34104977-3827-4897-afb3-7dcc42e2dc88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984315185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3984315185
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1921582944
Short name T621
Test name
Test status
Simulation time 3996913805 ps
CPU time 55.26 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:51:36 PM PDT 24
Peak memory 198780 kb
Host smart-9755713e-d310-4f86-ab6d-da24cde7d9ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921582944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1921582944
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.255321463
Short name T631
Test name
Test status
Simulation time 15125177 ps
CPU time 0.59 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:28 PM PDT 24
Peak memory 195612 kb
Host smart-d6f94abe-39b6-4870-9c97-2a6d71c7f2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255321463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.255321463
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2396045164
Short name T81
Test name
Test status
Simulation time 35979007 ps
CPU time 0.79 seconds
Started Jul 06 04:50:29 PM PDT 24
Finished Jul 06 04:50:30 PM PDT 24
Peak memory 196088 kb
Host smart-24168345-83fb-4d73-9f0f-7bcfca12b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396045164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2396045164
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2576862473
Short name T524
Test name
Test status
Simulation time 2509733398 ps
CPU time 6.93 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:38 PM PDT 24
Peak memory 197380 kb
Host smart-cf0d7be5-68dc-4a4f-bf8c-956d6fda65d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576862473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2576862473
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3853461974
Short name T129
Test name
Test status
Simulation time 134272895 ps
CPU time 0.75 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:36 PM PDT 24
Peak memory 196236 kb
Host smart-624935b7-0d86-43b7-9fe7-066a243ce03b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853461974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3853461974
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1320002715
Short name T154
Test name
Test status
Simulation time 286541084 ps
CPU time 1.02 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 197132 kb
Host smart-f01c7c72-e363-49ac-a01b-afc2c9e19c44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320002715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1320002715
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.984780740
Short name T549
Test name
Test status
Simulation time 26395915 ps
CPU time 1.13 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:29 PM PDT 24
Peak memory 197436 kb
Host smart-8a8201c9-bb0a-45d5-a119-37c58dd0fcb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984780740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.984780740
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3798821985
Short name T407
Test name
Test status
Simulation time 594950658 ps
CPU time 1 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 196008 kb
Host smart-05d81fbe-abfc-4a22-bf96-9412f42d10bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798821985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3798821985
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3676625744
Short name T209
Test name
Test status
Simulation time 22109574 ps
CPU time 0.83 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:31 PM PDT 24
Peak memory 197124 kb
Host smart-6b693ea4-b061-4d5c-aac5-427a4d0376fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676625744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3676625744
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.128064943
Short name T375
Test name
Test status
Simulation time 163622244 ps
CPU time 0.94 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:38 PM PDT 24
Peak memory 196460 kb
Host smart-f65644e8-df17-4e5d-b704-32c706ffd98a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128064943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.128064943
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.476544065
Short name T507
Test name
Test status
Simulation time 45126487 ps
CPU time 2.05 seconds
Started Jul 06 04:50:37 PM PDT 24
Finished Jul 06 04:50:40 PM PDT 24
Peak memory 198648 kb
Host smart-b4c45049-9172-4bfc-8dfd-7a48400b92b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476544065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.476544065
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2232340971
Short name T242
Test name
Test status
Simulation time 159233422 ps
CPU time 1.13 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:37 PM PDT 24
Peak memory 196204 kb
Host smart-78623021-a839-4410-b927-60656c629f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232340971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2232340971
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3796486087
Short name T212
Test name
Test status
Simulation time 260165303 ps
CPU time 0.73 seconds
Started Jul 06 04:50:43 PM PDT 24
Finished Jul 06 04:50:44 PM PDT 24
Peak memory 195784 kb
Host smart-242afc9f-5f23-44ee-993c-2a96e2fed589
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796486087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3796486087
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2150336294
Short name T3
Test name
Test status
Simulation time 5535919242 ps
CPU time 16.1 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:52 PM PDT 24
Peak memory 198704 kb
Host smart-e96ed6eb-67b0-4e2b-89e3-7a3b049e8cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150336294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2150336294
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1293699623
Short name T646
Test name
Test status
Simulation time 28250195 ps
CPU time 0.6 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:31 PM PDT 24
Peak memory 195272 kb
Host smart-efb14de1-bb12-4179-9e6e-1e34f82de369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293699623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1293699623
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1138631972
Short name T413
Test name
Test status
Simulation time 19112324 ps
CPU time 0.63 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:36 PM PDT 24
Peak memory 194632 kb
Host smart-aecde0dd-37b0-4e05-9844-9c7bf72a9e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138631972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1138631972
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.796645298
Short name T117
Test name
Test status
Simulation time 195861166 ps
CPU time 9.62 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 196124 kb
Host smart-227bb9fc-10ac-46d4-8cfa-b264f9c4c47a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796645298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.796645298
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2210895607
Short name T208
Test name
Test status
Simulation time 1959469700 ps
CPU time 1.03 seconds
Started Jul 06 04:50:44 PM PDT 24
Finished Jul 06 04:50:46 PM PDT 24
Peak memory 197068 kb
Host smart-bc095f7f-9f0e-4e69-a5b0-7128fb222eed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210895607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2210895607
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.545470820
Short name T495
Test name
Test status
Simulation time 170413035 ps
CPU time 0.88 seconds
Started Jul 06 04:50:34 PM PDT 24
Finished Jul 06 04:50:35 PM PDT 24
Peak memory 196180 kb
Host smart-69766440-ad59-4422-a6a8-2badd3fc4778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545470820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.545470820
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1884457687
Short name T295
Test name
Test status
Simulation time 278284363 ps
CPU time 3.81 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:31 PM PDT 24
Peak memory 198660 kb
Host smart-a1353794-feea-4f72-8e32-13e658f142d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884457687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1884457687
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3818586819
Short name T79
Test name
Test status
Simulation time 236010046 ps
CPU time 2.5 seconds
Started Jul 06 04:50:41 PM PDT 24
Finished Jul 06 04:50:45 PM PDT 24
Peak memory 198596 kb
Host smart-13232cdc-9d92-42be-a9c9-0f9c3bd53990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818586819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3818586819
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1835068406
Short name T660
Test name
Test status
Simulation time 244838149 ps
CPU time 1.13 seconds
Started Jul 06 04:50:24 PM PDT 24
Finished Jul 06 04:50:26 PM PDT 24
Peak memory 196648 kb
Host smart-09255b96-69cd-477d-b30c-dce8193435cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835068406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1835068406
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3212705509
Short name T601
Test name
Test status
Simulation time 62686995 ps
CPU time 1.28 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 197472 kb
Host smart-a038377c-5b73-4925-a3f9-36ed81366510
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212705509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3212705509
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2433925659
Short name T247
Test name
Test status
Simulation time 97622877 ps
CPU time 1.73 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 198460 kb
Host smart-17d818dc-772c-4c50-8f81-67e656d23efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433925659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2433925659
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3988842899
Short name T530
Test name
Test status
Simulation time 53296922 ps
CPU time 0.93 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:28 PM PDT 24
Peak memory 197772 kb
Host smart-0812ae32-1f5e-4e93-a79e-f69b523a955b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988842899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3988842899
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.135523378
Short name T112
Test name
Test status
Simulation time 44212486 ps
CPU time 1.24 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:39 PM PDT 24
Peak memory 197236 kb
Host smart-f5a3264d-43c4-42a1-a53e-1c5fbc5236b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135523378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.135523378
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3412704981
Short name T454
Test name
Test status
Simulation time 5591573946 ps
CPU time 37.34 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:51:05 PM PDT 24
Peak memory 198676 kb
Host smart-c1df6719-f78e-47f8-a057-5b7a49ed06ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412704981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3412704981
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2647768460
Short name T672
Test name
Test status
Simulation time 120550731775 ps
CPU time 1138.32 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 05:09:34 PM PDT 24
Peak memory 198976 kb
Host smart-f0b49587-806b-4743-a248-bb142678cbe4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2647768460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2647768460
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1450364820
Short name T410
Test name
Test status
Simulation time 13684274 ps
CPU time 0.55 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 194600 kb
Host smart-7673681a-b8a5-40fa-97c6-4f315c572d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450364820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1450364820
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.37022642
Short name T450
Test name
Test status
Simulation time 72085768 ps
CPU time 0.72 seconds
Started Jul 06 04:50:42 PM PDT 24
Finished Jul 06 04:50:44 PM PDT 24
Peak memory 196560 kb
Host smart-b4c89fa5-e455-4793-aa29-3c076ea26a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37022642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.37022642
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2947358056
Short name T268
Test name
Test status
Simulation time 929952151 ps
CPU time 29.01 seconds
Started Jul 06 04:50:30 PM PDT 24
Finished Jul 06 04:50:59 PM PDT 24
Peak memory 196952 kb
Host smart-8d310463-a167-4c7d-9e5e-8929af79fa22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947358056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2947358056
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.3539266229
Short name T593
Test name
Test status
Simulation time 495333753 ps
CPU time 0.88 seconds
Started Jul 06 04:50:23 PM PDT 24
Finished Jul 06 04:50:24 PM PDT 24
Peak memory 198576 kb
Host smart-ddd59643-e731-42c0-9219-b85662f2bdd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539266229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.3539266229
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3763130457
Short name T703
Test name
Test status
Simulation time 197926014 ps
CPU time 1.4 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 04:50:42 PM PDT 24
Peak memory 197728 kb
Host smart-0e9bb482-cd52-4cfe-a8f6-1273133fb833
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763130457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3763130457
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3998075579
Short name T537
Test name
Test status
Simulation time 369104667 ps
CPU time 3.3 seconds
Started Jul 06 04:50:25 PM PDT 24
Finished Jul 06 04:50:29 PM PDT 24
Peak memory 198580 kb
Host smart-2ed53c5c-3f03-4b9a-9f95-1dd3b53e06b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998075579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3998075579
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1767109858
Short name T710
Test name
Test status
Simulation time 79454373 ps
CPU time 1.69 seconds
Started Jul 06 04:50:40 PM PDT 24
Finished Jul 06 04:50:43 PM PDT 24
Peak memory 197416 kb
Host smart-ec26d291-54c8-4e9b-9c0f-2cd99511b4e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767109858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1767109858
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3372199860
Short name T165
Test name
Test status
Simulation time 57672563 ps
CPU time 0.73 seconds
Started Jul 06 04:50:27 PM PDT 24
Finished Jul 06 04:50:28 PM PDT 24
Peak memory 196680 kb
Host smart-0bdd1cfc-9d1d-478c-88c6-94161221ee32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372199860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3372199860
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.741851790
Short name T213
Test name
Test status
Simulation time 115811306 ps
CPU time 1.17 seconds
Started Jul 06 04:50:36 PM PDT 24
Finished Jul 06 04:50:38 PM PDT 24
Peak memory 197484 kb
Host smart-d66b2176-9e6f-446f-8e85-daee369a1e97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741851790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.741851790
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3712477138
Short name T207
Test name
Test status
Simulation time 103256992 ps
CPU time 4.4 seconds
Started Jul 06 04:50:29 PM PDT 24
Finished Jul 06 04:50:33 PM PDT 24
Peak memory 198496 kb
Host smart-713cf202-c588-4376-a892-1326126ada0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712477138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3712477138
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1663443646
Short name T174
Test name
Test status
Simulation time 122065404 ps
CPU time 1.08 seconds
Started Jul 06 04:50:31 PM PDT 24
Finished Jul 06 04:50:33 PM PDT 24
Peak memory 196316 kb
Host smart-0ef5b964-29d5-4938-9a03-05f1d0315eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663443646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1663443646
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.364868598
Short name T281
Test name
Test status
Simulation time 68689669 ps
CPU time 1.2 seconds
Started Jul 06 04:50:35 PM PDT 24
Finished Jul 06 04:50:37 PM PDT 24
Peak memory 196120 kb
Host smart-d4b1cefb-c243-4138-9c12-6b961f86f55e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364868598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.364868598
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1034681897
Short name T523
Test name
Test status
Simulation time 4884228467 ps
CPU time 65.74 seconds
Started Jul 06 04:50:46 PM PDT 24
Finished Jul 06 04:51:52 PM PDT 24
Peak memory 198712 kb
Host smart-bf1b49d8-aa08-4743-a4db-1a637b725641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034681897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1034681897
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1288148402
Short name T551
Test name
Test status
Simulation time 1018772597667 ps
CPU time 2129.69 seconds
Started Jul 06 04:50:39 PM PDT 24
Finished Jul 06 05:26:11 PM PDT 24
Peak memory 207160 kb
Host smart-e0fd83dd-50e9-44be-bfa7-2104c86b1241
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1288148402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1288148402
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2923064651
Short name T417
Test name
Test status
Simulation time 24750906 ps
CPU time 0.66 seconds
Started Jul 06 04:49:02 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 195480 kb
Host smart-a33070a3-214a-4cef-b0b0-5edde11cebf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923064651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2923064651
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.476811580
Short name T177
Test name
Test status
Simulation time 31990245 ps
CPU time 0.8 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 196628 kb
Host smart-25ec76d9-3868-4b24-bb49-dac73f2460db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476811580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.476811580
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.777354120
Short name T23
Test name
Test status
Simulation time 603808759 ps
CPU time 16.09 seconds
Started Jul 06 04:49:03 PM PDT 24
Finished Jul 06 04:49:20 PM PDT 24
Peak memory 197624 kb
Host smart-aeaebc8a-534b-4016-b90d-0a817bee319d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777354120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.777354120
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3725365908
Short name T428
Test name
Test status
Simulation time 44800738 ps
CPU time 0.84 seconds
Started Jul 06 04:48:58 PM PDT 24
Finished Jul 06 04:48:59 PM PDT 24
Peak memory 197228 kb
Host smart-e7beb7d8-ff2a-43bf-9db0-f4abcd1157b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725365908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3725365908
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3612164241
Short name T483
Test name
Test status
Simulation time 47803598 ps
CPU time 0.93 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 197080 kb
Host smart-8217eb4d-efae-48f0-bc75-37cb2112cc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612164241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3612164241
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3441190736
Short name T186
Test name
Test status
Simulation time 62326240 ps
CPU time 2.57 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 198652 kb
Host smart-9277e88e-ae30-4387-8ca1-19277d906e74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441190736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3441190736
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1627100051
Short name T403
Test name
Test status
Simulation time 52444688 ps
CPU time 1.22 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:15 PM PDT 24
Peak memory 197132 kb
Host smart-324a1ed9-ec78-482a-b2ac-a97133ab33f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627100051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1627100051
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3750851217
Short name T639
Test name
Test status
Simulation time 112903432 ps
CPU time 0.77 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 195896 kb
Host smart-902e5db5-9c96-4bcd-925b-7c2d701b8703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750851217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3750851217
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.419280680
Short name T329
Test name
Test status
Simulation time 47468575 ps
CPU time 1.08 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 197372 kb
Host smart-73ec4adb-2676-40d4-ad2e-639528c38f1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419280680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.419280680
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.773601697
Short name T501
Test name
Test status
Simulation time 52327014 ps
CPU time 2.57 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 198580 kb
Host smart-4bb18526-1213-46b7-b5d8-b152a529a0f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773601697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.773601697
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3355766368
Short name T565
Test name
Test status
Simulation time 182318180 ps
CPU time 0.81 seconds
Started Jul 06 04:49:11 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 195980 kb
Host smart-d3bcb59f-693e-4189-b055-89c65e3a80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355766368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3355766368
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1479200493
Short name T216
Test name
Test status
Simulation time 355279840 ps
CPU time 1.37 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:49:13 PM PDT 24
Peak memory 197480 kb
Host smart-a7f4a26b-f952-4814-8cf8-737a24a51e6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479200493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1479200493
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3334540068
Short name T682
Test name
Test status
Simulation time 15530489276 ps
CPU time 159.12 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:51:39 PM PDT 24
Peak memory 198624 kb
Host smart-30e61372-d067-443b-a944-da49f115fd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334540068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3334540068
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.623536097
Short name T56
Test name
Test status
Simulation time 164890188471 ps
CPU time 601.07 seconds
Started Jul 06 04:49:21 PM PDT 24
Finished Jul 06 04:59:22 PM PDT 24
Peak memory 198900 kb
Host smart-45ed98d9-26be-4f67-a7b4-fa8beaaacd75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=623536097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.623536097
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.4292283811
Short name T78
Test name
Test status
Simulation time 20187005 ps
CPU time 0.58 seconds
Started Jul 06 04:49:09 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 194584 kb
Host smart-679015b2-d752-4f6d-a8a6-1ff17c2f2575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292283811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.4292283811
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3737622210
Short name T562
Test name
Test status
Simulation time 536549347 ps
CPU time 0.9 seconds
Started Jul 06 04:49:02 PM PDT 24
Finished Jul 06 04:49:04 PM PDT 24
Peak memory 196496 kb
Host smart-373802c3-32a3-4148-b1aa-f8578c9f26bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737622210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3737622210
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3043646411
Short name T16
Test name
Test status
Simulation time 1563207565 ps
CPU time 20.58 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:29 PM PDT 24
Peak memory 198596 kb
Host smart-fabbcee8-2a73-4029-9311-acf5d0490834
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043646411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3043646411
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2915862564
Short name T346
Test name
Test status
Simulation time 155311655 ps
CPU time 0.99 seconds
Started Jul 06 04:49:09 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 196952 kb
Host smart-e5e31756-5da7-44fe-b22a-459d615d3903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915862564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2915862564
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2610718104
Short name T502
Test name
Test status
Simulation time 26131581 ps
CPU time 0.78 seconds
Started Jul 06 04:49:02 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 195052 kb
Host smart-257063f4-52b8-412f-b330-fea3334dd5e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610718104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2610718104
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3725925201
Short name T183
Test name
Test status
Simulation time 463744955 ps
CPU time 2.46 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:13 PM PDT 24
Peak memory 198724 kb
Host smart-0244783b-655a-4907-a210-95ae608a1f17
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725925201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3725925201
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.590234451
Short name T50
Test name
Test status
Simulation time 137132519 ps
CPU time 1.26 seconds
Started Jul 06 04:49:03 PM PDT 24
Finished Jul 06 04:49:04 PM PDT 24
Peak memory 196384 kb
Host smart-113347c6-0a76-4d5c-99e2-cabcf186c43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590234451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.590234451
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1545491503
Short name T355
Test name
Test status
Simulation time 46733805 ps
CPU time 1.05 seconds
Started Jul 06 04:49:00 PM PDT 24
Finished Jul 06 04:49:02 PM PDT 24
Peak memory 196668 kb
Host smart-419f16f0-f1ec-4f80-9567-01b981c28e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545491503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1545491503
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1451394854
Short name T594
Test name
Test status
Simulation time 44684519 ps
CPU time 0.82 seconds
Started Jul 06 04:49:02 PM PDT 24
Finished Jul 06 04:49:03 PM PDT 24
Peak memory 196044 kb
Host smart-f1b43502-5a9d-46d8-aa6f-b3ff61f0550e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451394854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1451394854
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.795486590
Short name T624
Test name
Test status
Simulation time 276452725 ps
CPU time 4.3 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:18 PM PDT 24
Peak memory 198576 kb
Host smart-35d26a29-0bc1-4c6b-89e5-28f9d8f7b557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795486590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.795486590
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2277710312
Short name T436
Test name
Test status
Simulation time 53607723 ps
CPU time 1.16 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:17 PM PDT 24
Peak memory 196428 kb
Host smart-8d3fdb90-6532-4c3f-ae48-35979c2e2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277710312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2277710312
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3797001525
Short name T692
Test name
Test status
Simulation time 236588928 ps
CPU time 1.06 seconds
Started Jul 06 04:48:59 PM PDT 24
Finished Jul 06 04:49:01 PM PDT 24
Peak memory 196140 kb
Host smart-15ab052d-5421-4b5e-bcc0-106ad4c28dca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797001525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3797001525
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3756862680
Short name T381
Test name
Test status
Simulation time 13011678084 ps
CPU time 19.95 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:34 PM PDT 24
Peak memory 198684 kb
Host smart-ce3c3707-e3e1-43ed-a5cb-2aa9aa76d2e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756862680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3756862680
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3730427362
Short name T198
Test name
Test status
Simulation time 12007990 ps
CPU time 0.56 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:08 PM PDT 24
Peak memory 194516 kb
Host smart-b3783e27-752d-465b-a994-a7daabcbf518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730427362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3730427362
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3408740321
Short name T45
Test name
Test status
Simulation time 54121464 ps
CPU time 0.93 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:49:13 PM PDT 24
Peak memory 196420 kb
Host smart-c7036fe6-8256-44f7-b548-ed6b749b3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408740321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3408740321
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1867553500
Short name T289
Test name
Test status
Simulation time 670311457 ps
CPU time 23.97 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:39 PM PDT 24
Peak memory 196116 kb
Host smart-fb8767f6-b48c-486f-a94e-b9bda5695258
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867553500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1867553500
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3541303221
Short name T520
Test name
Test status
Simulation time 310452863 ps
CPU time 1.02 seconds
Started Jul 06 04:49:11 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 197264 kb
Host smart-496acb28-f201-495a-bd24-8d8d572b9779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541303221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3541303221
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4073936892
Short name T419
Test name
Test status
Simulation time 94655175 ps
CPU time 0.78 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 197176 kb
Host smart-e18f1eec-6458-4ca0-9c8b-3531bab2b296
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073936892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4073936892
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3077582647
Short name T688
Test name
Test status
Simulation time 83282192 ps
CPU time 1.78 seconds
Started Jul 06 04:49:04 PM PDT 24
Finished Jul 06 04:49:06 PM PDT 24
Peak memory 198556 kb
Host smart-b0079ab1-2e53-4b1c-a23d-134421fdf833
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077582647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3077582647
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2218335050
Short name T149
Test name
Test status
Simulation time 65372153 ps
CPU time 1.58 seconds
Started Jul 06 04:49:09 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 196560 kb
Host smart-a59b8740-12c6-4166-8e59-dea9962338fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218335050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2218335050
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2434980461
Short name T404
Test name
Test status
Simulation time 19253797 ps
CPU time 0.73 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 194936 kb
Host smart-8f58d024-ab76-4380-961d-bbcd9b35b8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434980461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2434980461
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3746400696
Short name T304
Test name
Test status
Simulation time 54314554 ps
CPU time 1.1 seconds
Started Jul 06 04:49:14 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 197364 kb
Host smart-63a0dcea-820d-4b3f-af6e-fd62c641ede0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746400696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3746400696
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3442793151
Short name T567
Test name
Test status
Simulation time 102385020 ps
CPU time 2.4 seconds
Started Jul 06 04:49:07 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 198592 kb
Host smart-d8a21bce-4f1d-42c5-814d-769f4f4b69d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442793151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3442793151
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.752428347
Short name T140
Test name
Test status
Simulation time 46508311 ps
CPU time 1.06 seconds
Started Jul 06 04:49:09 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 196956 kb
Host smart-67f02d25-f3c3-4243-93db-2bb3bcc469ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752428347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.752428347
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.4100761332
Short name T718
Test name
Test status
Simulation time 282783795 ps
CPU time 1.11 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 04:49:08 PM PDT 24
Peak memory 196228 kb
Host smart-f2f15d0b-418a-43ce-b57c-c2c1e46047c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100761332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.4100761332
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3214178768
Short name T500
Test name
Test status
Simulation time 49786067623 ps
CPU time 175.25 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:52:04 PM PDT 24
Peak memory 198724 kb
Host smart-2c533f92-f099-4823-a038-a906a852d3d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214178768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3214178768
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4261770561
Short name T695
Test name
Test status
Simulation time 13030103 ps
CPU time 0.61 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 194548 kb
Host smart-df0ae842-744b-4696-9fd2-75a7a63c5403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261770561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4261770561
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1787043733
Short name T446
Test name
Test status
Simulation time 59068368 ps
CPU time 0.95 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:09 PM PDT 24
Peak memory 197836 kb
Host smart-b98b446d-5016-4d06-aee1-de0d3f61eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787043733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1787043733
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.4122273062
Short name T572
Test name
Test status
Simulation time 1090790555 ps
CPU time 11.71 seconds
Started Jul 06 04:49:12 PM PDT 24
Finished Jul 06 04:49:24 PM PDT 24
Peak memory 198676 kb
Host smart-1104678c-ebc7-4bc8-95c9-2e026c569e37
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122273062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.4122273062
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1234652926
Short name T522
Test name
Test status
Simulation time 55034512 ps
CPU time 0.82 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 196652 kb
Host smart-7137e4a7-eb63-4ea0-82c2-cc283cebb2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234652926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1234652926
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2057024042
Short name T222
Test name
Test status
Simulation time 170608500 ps
CPU time 1.21 seconds
Started Jul 06 04:49:07 PM PDT 24
Finished Jul 06 04:49:09 PM PDT 24
Peak memory 197136 kb
Host smart-710814fc-ca10-4dc2-8050-52c9800e076d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057024042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2057024042
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2274356564
Short name T291
Test name
Test status
Simulation time 205289918 ps
CPU time 2.09 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 197004 kb
Host smart-e4000097-c82e-4d68-84a4-4731eea934b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274356564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2274356564
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3516564301
Short name T595
Test name
Test status
Simulation time 114350720 ps
CPU time 3.24 seconds
Started Jul 06 04:49:07 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 197196 kb
Host smart-44a6c8d6-3f30-466f-8bb7-9e397ea111a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516564301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3516564301
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1617023398
Short name T12
Test name
Test status
Simulation time 128383998 ps
CPU time 1.23 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 04:49:08 PM PDT 24
Peak memory 197424 kb
Host smart-ea4baf38-0436-4f9a-8fe5-8cce3329e80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617023398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1617023398
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3863751892
Short name T580
Test name
Test status
Simulation time 79251394 ps
CPU time 0.71 seconds
Started Jul 06 04:49:09 PM PDT 24
Finished Jul 06 04:49:11 PM PDT 24
Peak memory 194956 kb
Host smart-afd45dc2-877c-41a6-9960-397623f0cfb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863751892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3863751892
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1266684915
Short name T515
Test name
Test status
Simulation time 556068598 ps
CPU time 6.67 seconds
Started Jul 06 04:49:16 PM PDT 24
Finished Jul 06 04:49:23 PM PDT 24
Peak memory 198564 kb
Host smart-2ef24da4-3806-4aab-9ea3-8f1420103bd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266684915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1266684915
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.336090598
Short name T667
Test name
Test status
Simulation time 85189581 ps
CPU time 0.83 seconds
Started Jul 06 04:49:11 PM PDT 24
Finished Jul 06 04:49:12 PM PDT 24
Peak memory 196788 kb
Host smart-2a3ddc72-7368-42ba-9ccf-08154419ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336090598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.336090598
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.796536091
Short name T335
Test name
Test status
Simulation time 125478080 ps
CPU time 1.07 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 196172 kb
Host smart-c90b91e0-773e-422d-aa13-23de0def8136
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796536091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.796536091
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2701394873
Short name T9
Test name
Test status
Simulation time 10370907334 ps
CPU time 27.73 seconds
Started Jul 06 04:49:13 PM PDT 24
Finished Jul 06 04:49:42 PM PDT 24
Peak memory 198624 kb
Host smart-7d4a4690-fba5-4594-84e9-c5e44ae80ace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701394873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2701394873
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.335727146
Short name T697
Test name
Test status
Simulation time 51842307 ps
CPU time 0.56 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 195380 kb
Host smart-28e5baca-ceb6-4d60-921b-87bcbc660f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335727146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.335727146
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3072989774
Short name T359
Test name
Test status
Simulation time 21736193 ps
CPU time 0.81 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 195824 kb
Host smart-09c365e3-f96d-4cad-94a3-25beba0b63f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072989774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3072989774
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2757343975
Short name T444
Test name
Test status
Simulation time 2949117733 ps
CPU time 11.03 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:21 PM PDT 24
Peak memory 198672 kb
Host smart-a849ac7a-5448-4574-b30c-f2fb06c388ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757343975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2757343975
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1963683216
Short name T196
Test name
Test status
Simulation time 48679575 ps
CPU time 0.76 seconds
Started Jul 06 04:49:30 PM PDT 24
Finished Jul 06 04:49:31 PM PDT 24
Peak memory 196332 kb
Host smart-fc722479-5765-4f40-ab8c-8699fac39fb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963683216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1963683216
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2058577108
Short name T195
Test name
Test status
Simulation time 762102047 ps
CPU time 1.48 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 196420 kb
Host smart-c4a2b477-5ffc-487b-ae54-46f74a6b2725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058577108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2058577108
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.559826357
Short name T159
Test name
Test status
Simulation time 765471804 ps
CPU time 2.8 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 198660 kb
Host smart-bde7c529-2dc5-4d40-aa45-a79fe0fc5ab1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559826357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.559826357
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.562122359
Short name T75
Test name
Test status
Simulation time 116592368 ps
CPU time 1.38 seconds
Started Jul 06 04:49:18 PM PDT 24
Finished Jul 06 04:49:20 PM PDT 24
Peak memory 198032 kb
Host smart-0bc2d3c3-2e47-49d3-b675-0d6a14b731b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562122359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.562122359
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3756455055
Short name T187
Test name
Test status
Simulation time 53110779 ps
CPU time 0.65 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 04:49:07 PM PDT 24
Peak memory 194828 kb
Host smart-3dac519d-c79e-485d-9fe8-47392a93ec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756455055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3756455055
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3994095921
Short name T509
Test name
Test status
Simulation time 114957491 ps
CPU time 1.18 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 198740 kb
Host smart-f121aca1-fe18-4a10-aad6-d7658a689942
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994095921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3994095921
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3230500058
Short name T633
Test name
Test status
Simulation time 646509494 ps
CPU time 5.84 seconds
Started Jul 06 04:49:10 PM PDT 24
Finished Jul 06 04:49:16 PM PDT 24
Peak memory 198496 kb
Host smart-c32a3788-8f62-4e19-9f70-cf412f7d9156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230500058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3230500058
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1943628042
Short name T46
Test name
Test status
Simulation time 88144738 ps
CPU time 1.29 seconds
Started Jul 06 04:49:08 PM PDT 24
Finished Jul 06 04:49:10 PM PDT 24
Peak memory 197156 kb
Host smart-5ca507a7-dbf2-440c-9a69-0becbf25d101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943628042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1943628042
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.566574631
Short name T121
Test name
Test status
Simulation time 34468137 ps
CPU time 1 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 04:49:08 PM PDT 24
Peak memory 196960 kb
Host smart-1ab96056-e2cd-466c-a32f-a6e42bcc2f38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566574631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.566574631
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2687632406
Short name T690
Test name
Test status
Simulation time 8154610618 ps
CPU time 211.45 seconds
Started Jul 06 04:49:15 PM PDT 24
Finished Jul 06 04:52:47 PM PDT 24
Peak memory 198784 kb
Host smart-c3cedc1c-1437-4abc-951f-d928c99acb44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687632406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2687632406
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.767705978
Short name T576
Test name
Test status
Simulation time 53180123492 ps
CPU time 1060.99 seconds
Started Jul 06 04:49:06 PM PDT 24
Finished Jul 06 05:06:48 PM PDT 24
Peak memory 198884 kb
Host smart-568c5249-263f-40c1-8b9d-0e0d8fa2356f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=767705978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.767705978
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2880383232
Short name T851
Test name
Test status
Simulation time 61953601 ps
CPU time 0.88 seconds
Started Jul 06 04:46:21 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 198180 kb
Host smart-3696346d-5eb4-402e-845c-8e237a5a0bba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2880383232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2880383232
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1226740063
Short name T850
Test name
Test status
Simulation time 158118634 ps
CPU time 1.24 seconds
Started Jul 06 04:46:21 PM PDT 24
Finished Jul 06 04:46:23 PM PDT 24
Peak memory 195928 kb
Host smart-bee7fb59-5a2c-4b77-a1fc-543c22555eaf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226740063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1226740063
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3588285201
Short name T942
Test name
Test status
Simulation time 25981678 ps
CPU time 0.77 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 195728 kb
Host smart-8a8c6761-efe4-4c3e-b08f-46cf043385e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3588285201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3588285201
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164948552
Short name T882
Test name
Test status
Simulation time 102688658 ps
CPU time 0.8 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 195352 kb
Host smart-6ee075d4-7e15-4de7-8332-67606bde6aea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164948552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1164948552
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1317345661
Short name T878
Test name
Test status
Simulation time 773639880 ps
CPU time 1.03 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:20 PM PDT 24
Peak memory 196808 kb
Host smart-76657a1e-171f-4e41-8726-9214fe95f413
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1317345661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1317345661
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3922628123
Short name T866
Test name
Test status
Simulation time 331493874 ps
CPU time 1.22 seconds
Started Jul 06 04:46:27 PM PDT 24
Finished Jul 06 04:46:29 PM PDT 24
Peak memory 196004 kb
Host smart-c519ffd1-63a7-415d-bd48-de55f763e0da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922628123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3922628123
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1059207781
Short name T904
Test name
Test status
Simulation time 42008519 ps
CPU time 1.05 seconds
Started Jul 06 04:46:21 PM PDT 24
Finished Jul 06 04:46:23 PM PDT 24
Peak memory 198180 kb
Host smart-b73bee16-675b-43a7-956b-a2893087075c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1059207781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1059207781
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2937240191
Short name T864
Test name
Test status
Simulation time 50355839 ps
CPU time 1.42 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 197128 kb
Host smart-c5222c89-160a-40d0-8280-b44d82679724
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937240191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2937240191
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1926472955
Short name T873
Test name
Test status
Simulation time 60618287 ps
CPU time 1.13 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:19 PM PDT 24
Peak memory 198356 kb
Host smart-f1bfbe67-1a69-46a0-8115-6ae7aa76674a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1926472955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1926472955
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4166554633
Short name T862
Test name
Test status
Simulation time 30037218 ps
CPU time 0.94 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 196456 kb
Host smart-8ba6658e-413a-4738-8065-b9b75b6116e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166554633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4166554633
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1564436021
Short name T869
Test name
Test status
Simulation time 315240333 ps
CPU time 1.58 seconds
Started Jul 06 04:46:26 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 197152 kb
Host smart-271c3b04-faa5-438b-94e2-509c9a8b9f38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1564436021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1564436021
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3290666708
Short name T870
Test name
Test status
Simulation time 108645366 ps
CPU time 0.87 seconds
Started Jul 06 04:46:22 PM PDT 24
Finished Jul 06 04:46:23 PM PDT 24
Peak memory 196988 kb
Host smart-3f4c454c-b9ca-4e07-ae91-bd6f09fd23a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290666708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3290666708
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1163182216
Short name T861
Test name
Test status
Simulation time 208869925 ps
CPU time 0.98 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 195888 kb
Host smart-f95ced3b-ff0f-4155-b8c8-4db582d0793d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1163182216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1163182216
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.890973554
Short name T898
Test name
Test status
Simulation time 249331155 ps
CPU time 1.54 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 198368 kb
Host smart-9daee90c-fd99-42a1-8fff-ce2b1317ceae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890973554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.890973554
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1764513862
Short name T883
Test name
Test status
Simulation time 77242993 ps
CPU time 1.11 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 197100 kb
Host smart-ec4d769f-a741-43c6-b214-4f22908d42db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1764513862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1764513862
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3875080777
Short name T924
Test name
Test status
Simulation time 99436599 ps
CPU time 1.14 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:19 PM PDT 24
Peak memory 196880 kb
Host smart-c8b3622d-a80d-4dc4-aec1-a9dd77ab06d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875080777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3875080777
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.989931044
Short name T921
Test name
Test status
Simulation time 114568582 ps
CPU time 1.04 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 196884 kb
Host smart-f06bf161-ccbb-449c-94c3-e2c172824276
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=989931044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.989931044
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.20155151
Short name T910
Test name
Test status
Simulation time 117846536 ps
CPU time 1.06 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 196952 kb
Host smart-ff4bd922-a113-4305-abc2-b05822295c15
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20155151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.20155151
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1187608158
Short name T929
Test name
Test status
Simulation time 378610446 ps
CPU time 1 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 196880 kb
Host smart-a36751cb-6af2-4149-99af-8a2d915d4c78
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1187608158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1187608158
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1178093699
Short name T931
Test name
Test status
Simulation time 520855793 ps
CPU time 1.21 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 198300 kb
Host smart-49b23c3e-ef82-4ac6-9f83-38e8d6a121ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178093699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1178093699
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2546085675
Short name T858
Test name
Test status
Simulation time 148547022 ps
CPU time 1.32 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 198340 kb
Host smart-2b3d2b50-5ee1-4e5e-a241-84266a847716
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2546085675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2546085675
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.563752504
Short name T933
Test name
Test status
Simulation time 303022826 ps
CPU time 0.88 seconds
Started Jul 06 04:46:28 PM PDT 24
Finished Jul 06 04:46:29 PM PDT 24
Peak memory 196636 kb
Host smart-9566d365-cd82-4402-bed3-1925fc870011
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563752504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.563752504
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3810886053
Short name T930
Test name
Test status
Simulation time 279198079 ps
CPU time 1.19 seconds
Started Jul 06 04:46:22 PM PDT 24
Finished Jul 06 04:46:24 PM PDT 24
Peak memory 198312 kb
Host smart-0b2c1f4a-ff45-4f68-8703-ebcfa95e4074
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3810886053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3810886053
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1690404204
Short name T853
Test name
Test status
Simulation time 43087284 ps
CPU time 0.78 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 195660 kb
Host smart-d847ec04-aa5d-4dbb-ba8c-885fba9d3da4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690404204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1690404204
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.255572337
Short name T872
Test name
Test status
Simulation time 232769274 ps
CPU time 1.11 seconds
Started Jul 06 04:46:17 PM PDT 24
Finished Jul 06 04:46:18 PM PDT 24
Peak memory 196944 kb
Host smart-19e4c23d-9f50-4884-b0a6-aa963f9e81c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=255572337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.255572337
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1366774555
Short name T884
Test name
Test status
Simulation time 57011606 ps
CPU time 1.27 seconds
Started Jul 06 04:46:26 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 196848 kb
Host smart-6ddaea53-4930-4876-9573-385c0fbfd39f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366774555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1366774555
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1715363770
Short name T919
Test name
Test status
Simulation time 319349289 ps
CPU time 1.35 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 198356 kb
Host smart-fb1e5291-16e0-4ced-a9e5-910cccc961be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1715363770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1715363770
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3593369368
Short name T847
Test name
Test status
Simulation time 50491420 ps
CPU time 0.97 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 196752 kb
Host smart-f2370854-2822-4385-a1f4-5035f05dc9f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593369368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3593369368
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.663505854
Short name T891
Test name
Test status
Simulation time 66246523 ps
CPU time 1.27 seconds
Started Jul 06 04:47:38 PM PDT 24
Finished Jul 06 04:47:40 PM PDT 24
Peak memory 196964 kb
Host smart-89815a76-e8fc-4c15-9a5c-5c41051c0501
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=663505854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.663505854
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3020226459
Short name T938
Test name
Test status
Simulation time 229967610 ps
CPU time 1.17 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 196900 kb
Host smart-cb70773c-1454-4c9e-ad7f-8d305ee12744
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020226459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3020226459
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1279466744
Short name T935
Test name
Test status
Simulation time 133912397 ps
CPU time 0.89 seconds
Started Jul 06 04:46:27 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 196448 kb
Host smart-2ce4acde-11b2-4338-a9e7-5ab9a251ddf0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1279466744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1279466744
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3468354553
Short name T888
Test name
Test status
Simulation time 47482767 ps
CPU time 0.94 seconds
Started Jul 06 04:46:28 PM PDT 24
Finished Jul 06 04:46:29 PM PDT 24
Peak memory 195824 kb
Host smart-0c4635f0-07ce-4c59-928a-015dc1dd08d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468354553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3468354553
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.614827262
Short name T925
Test name
Test status
Simulation time 1821228865 ps
CPU time 1.45 seconds
Started Jul 06 04:46:28 PM PDT 24
Finished Jul 06 04:46:30 PM PDT 24
Peak memory 196888 kb
Host smart-f4857c84-a849-460a-93f0-6d2f3195d269
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=614827262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.614827262
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1072305374
Short name T881
Test name
Test status
Simulation time 141750976 ps
CPU time 1.17 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 196916 kb
Host smart-07cc1512-7ec6-49c0-acd3-9e8ca3d9ad42
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072305374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1072305374
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.353206711
Short name T934
Test name
Test status
Simulation time 89621939 ps
CPU time 1.46 seconds
Started Jul 06 04:46:26 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 196948 kb
Host smart-c6c0d628-f061-4c9d-b422-2204a65800ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=353206711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.353206711
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1051502154
Short name T909
Test name
Test status
Simulation time 52116092 ps
CPU time 1.48 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 196896 kb
Host smart-93238fb7-7f8d-4532-b26c-357efdda4a11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051502154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1051502154
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.440650490
Short name T875
Test name
Test status
Simulation time 29075975 ps
CPU time 1.09 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 196892 kb
Host smart-71dd2d26-0b06-445a-8035-f7dc52736ea7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=440650490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.440650490
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3463521854
Short name T907
Test name
Test status
Simulation time 244745306 ps
CPU time 1.16 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 196212 kb
Host smart-e9bc2257-ae3a-4b40-9772-880b04b975dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463521854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3463521854
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2936011711
Short name T854
Test name
Test status
Simulation time 135877441 ps
CPU time 1.37 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 195968 kb
Host smart-e226b7f8-acbe-40e1-9f56-2d71cde3783d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2936011711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2936011711
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1548846291
Short name T937
Test name
Test status
Simulation time 44492544 ps
CPU time 0.96 seconds
Started Jul 06 04:46:22 PM PDT 24
Finished Jul 06 04:46:24 PM PDT 24
Peak memory 196536 kb
Host smart-1f6b9367-68b0-41cb-9f21-e87424870f97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548846291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1548846291
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3258299826
Short name T895
Test name
Test status
Simulation time 41337329 ps
CPU time 0.89 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 198300 kb
Host smart-c5b9370b-8c06-41f3-99df-02359099b4d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3258299826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3258299826
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398958820
Short name T914
Test name
Test status
Simulation time 46627192 ps
CPU time 1.02 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 196796 kb
Host smart-c1af4ea6-236e-41d0-869f-95ecb595346a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398958820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3398958820
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.214483148
Short name T897
Test name
Test status
Simulation time 97451312 ps
CPU time 0.89 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 195652 kb
Host smart-7a1b158d-446f-4d4f-9164-4cd52642c5c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=214483148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.214483148
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3162937732
Short name T913
Test name
Test status
Simulation time 88362255 ps
CPU time 0.95 seconds
Started Jul 06 04:46:29 PM PDT 24
Finished Jul 06 04:46:30 PM PDT 24
Peak memory 198136 kb
Host smart-27cee8bb-ee7c-4339-b501-453ec5861384
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162937732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3162937732
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2552286013
Short name T894
Test name
Test status
Simulation time 120917043 ps
CPU time 1.1 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 196956 kb
Host smart-d5cfc340-891b-4d6c-989d-a658d806ab38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2552286013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2552286013
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1762080564
Short name T860
Test name
Test status
Simulation time 28102171 ps
CPU time 0.88 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 195652 kb
Host smart-b8b2fe41-1422-4d27-ac60-1c07ff510612
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762080564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1762080564
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1313230780
Short name T939
Test name
Test status
Simulation time 121212119 ps
CPU time 0.9 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 195804 kb
Host smart-7250b771-196a-4772-93cc-49ec52345033
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1313230780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1313230780
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1761238035
Short name T905
Test name
Test status
Simulation time 41851454 ps
CPU time 1.39 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 197316 kb
Host smart-7a822778-23a9-4319-a5bc-b1a485450a33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761238035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1761238035
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1331994696
Short name T911
Test name
Test status
Simulation time 131809748 ps
CPU time 1.25 seconds
Started Jul 06 04:46:24 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 197288 kb
Host smart-1a4e78b2-e8e1-4173-b005-1ed5c0462d28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1331994696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1331994696
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154864561
Short name T922
Test name
Test status
Simulation time 207273141 ps
CPU time 1.58 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 198356 kb
Host smart-c7de9e56-17d5-4bec-89c3-7dc4fa9a5f95
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154864561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.154864561
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2681197972
Short name T852
Test name
Test status
Simulation time 36071785 ps
CPU time 0.95 seconds
Started Jul 06 04:46:26 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 196988 kb
Host smart-81fab7b9-e3bf-446d-8d46-c34d03f5db80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2681197972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2681197972
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1790981474
Short name T892
Test name
Test status
Simulation time 103729325 ps
CPU time 0.77 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 195704 kb
Host smart-ce630781-bfc2-46d6-aea0-756c010a26ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790981474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1790981474
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1687810017
Short name T886
Test name
Test status
Simulation time 73021647 ps
CPU time 0.95 seconds
Started Jul 06 04:46:23 PM PDT 24
Finished Jul 06 04:46:25 PM PDT 24
Peak memory 196936 kb
Host smart-6c97af18-2c4e-444b-9f63-d545d231da97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1687810017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1687810017
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4081449599
Short name T899
Test name
Test status
Simulation time 55327294 ps
CPU time 0.96 seconds
Started Jul 06 04:46:33 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 197048 kb
Host smart-1eaa2863-2c01-421b-b8c3-c15e894683ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081449599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4081449599
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2014909123
Short name T920
Test name
Test status
Simulation time 223641827 ps
CPU time 1.08 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 197020 kb
Host smart-0749a244-3aed-4586-a635-23581ee5278e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2014909123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2014909123
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2090593748
Short name T916
Test name
Test status
Simulation time 250149578 ps
CPU time 1.02 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 196808 kb
Host smart-cf7a0f88-8925-450f-b043-9f7f667cee4d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090593748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2090593748
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3046236240
Short name T908
Test name
Test status
Simulation time 77859853 ps
CPU time 0.81 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196436 kb
Host smart-2a058196-820f-4c67-8946-ea73e8bd864b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3046236240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3046236240
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4139186230
Short name T923
Test name
Test status
Simulation time 50099946 ps
CPU time 1.04 seconds
Started Jul 06 04:46:37 PM PDT 24
Finished Jul 06 04:46:38 PM PDT 24
Peak memory 196216 kb
Host smart-c00cfd59-6912-4483-9e9c-f3cceb63bb40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139186230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4139186230
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.4021390136
Short name T877
Test name
Test status
Simulation time 96264846 ps
CPU time 1.32 seconds
Started Jul 06 04:46:34 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 197056 kb
Host smart-9434dc53-14a3-4ea3-b0fd-a5a48fdb8749
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4021390136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.4021390136
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2612341229
Short name T926
Test name
Test status
Simulation time 37225433 ps
CPU time 1.12 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196956 kb
Host smart-60b6740d-26e1-462f-a14a-fd9f0b2a0edf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612341229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2612341229
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1057420267
Short name T893
Test name
Test status
Simulation time 162197458 ps
CPU time 1.08 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 196824 kb
Host smart-8757b3f4-2e3b-4cb3-903d-9c7f91aa2e5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1057420267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1057420267
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4224747729
Short name T879
Test name
Test status
Simulation time 70590261 ps
CPU time 1.12 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 196036 kb
Host smart-77b5b1c2-4a67-4b01-abc1-ca784b439a85
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224747729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4224747729
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.775747449
Short name T940
Test name
Test status
Simulation time 66759835 ps
CPU time 1.28 seconds
Started Jul 06 04:46:33 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 197280 kb
Host smart-75f29370-a0b1-4ce3-9a54-e9253b1d7644
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=775747449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.775747449
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1638531760
Short name T918
Test name
Test status
Simulation time 77180157 ps
CPU time 0.93 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 196704 kb
Host smart-d9ccd68e-b3e6-4cc2-ad5e-f0300ac52af7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638531760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1638531760
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4260628122
Short name T903
Test name
Test status
Simulation time 191384781 ps
CPU time 0.99 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196904 kb
Host smart-e805bc21-a555-44c4-b90a-8004bca33ffc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4260628122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4260628122
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3134968256
Short name T844
Test name
Test status
Simulation time 522330050 ps
CPU time 1.52 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:37 PM PDT 24
Peak memory 198308 kb
Host smart-e1ddcfc2-859c-455f-9b80-8d65c65cfa24
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134968256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3134968256
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3454279350
Short name T845
Test name
Test status
Simulation time 44891521 ps
CPU time 1.3 seconds
Started Jul 06 04:46:34 PM PDT 24
Finished Jul 06 04:46:35 PM PDT 24
Peak memory 196328 kb
Host smart-0407879b-5100-42b7-95d6-d415ceec2216
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3454279350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3454279350
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.393438318
Short name T932
Test name
Test status
Simulation time 176490568 ps
CPU time 0.97 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196828 kb
Host smart-e0b8e3b6-cadf-42de-8e05-412baf031585
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393438318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.393438318
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3347015617
Short name T915
Test name
Test status
Simulation time 122948935 ps
CPU time 1.25 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 198292 kb
Host smart-19894200-7df6-4337-9ddd-91d3edf821a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3347015617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3347015617
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3920546212
Short name T896
Test name
Test status
Simulation time 34562533 ps
CPU time 1.13 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 196868 kb
Host smart-5447b48e-e965-4291-b859-7f1561144b83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920546212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3920546212
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2616044657
Short name T867
Test name
Test status
Simulation time 231887003 ps
CPU time 1.14 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 198328 kb
Host smart-630f82af-2c27-4928-ad95-1f2c69acdc57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2616044657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2616044657
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1304667542
Short name T927
Test name
Test status
Simulation time 184950173 ps
CPU time 1.34 seconds
Started Jul 06 04:46:34 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 195968 kb
Host smart-82c29db6-43ad-48c5-ad9b-c84af9bbd5f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304667542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1304667542
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1848145555
Short name T902
Test name
Test status
Simulation time 39883721 ps
CPU time 1.05 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196100 kb
Host smart-373525b1-512f-4a04-9565-c1d5cf9959a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1848145555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1848145555
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2235787326
Short name T865
Test name
Test status
Simulation time 53260898 ps
CPU time 0.78 seconds
Started Jul 06 04:46:30 PM PDT 24
Finished Jul 06 04:46:31 PM PDT 24
Peak memory 196372 kb
Host smart-55b3dc9c-244b-4d5a-90b3-0a4b6c77b39a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235787326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2235787326
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.752515411
Short name T848
Test name
Test status
Simulation time 112602930 ps
CPU time 0.98 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 196692 kb
Host smart-7500f9a9-297d-4403-ab78-0a1d9bb9a42e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=752515411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.752515411
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3721637501
Short name T885
Test name
Test status
Simulation time 122097648 ps
CPU time 0.85 seconds
Started Jul 06 04:46:33 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 196752 kb
Host smart-4745817b-6277-443c-abf5-819ce895477d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721637501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3721637501
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1039420127
Short name T868
Test name
Test status
Simulation time 84389333 ps
CPU time 1.03 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 198284 kb
Host smart-e0af4c6d-dd96-4562-bbaf-02c6350535af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1039420127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1039420127
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.246631905
Short name T871
Test name
Test status
Simulation time 117984245 ps
CPU time 1 seconds
Started Jul 06 04:46:34 PM PDT 24
Finished Jul 06 04:46:35 PM PDT 24
Peak memory 196184 kb
Host smart-2161c554-d435-4160-a9af-3dce91f00732
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246631905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.246631905
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3625494832
Short name T863
Test name
Test status
Simulation time 130414478 ps
CPU time 1.34 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196080 kb
Host smart-6acbf6a7-4d49-4dbc-97c4-be05591e5159
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3625494832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3625494832
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2880622215
Short name T856
Test name
Test status
Simulation time 140037004 ps
CPU time 1.11 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 195972 kb
Host smart-67059cb3-918c-424e-bc4b-1406d7399a04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880622215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2880622215
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1751306692
Short name T846
Test name
Test status
Simulation time 64239668 ps
CPU time 1.11 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:37 PM PDT 24
Peak memory 196856 kb
Host smart-35a964eb-afc6-432d-8aa1-2ba7cb6deb81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1751306692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1751306692
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3342247898
Short name T859
Test name
Test status
Simulation time 194985662 ps
CPU time 1.39 seconds
Started Jul 06 04:46:31 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 195980 kb
Host smart-63d419b5-4ca0-4aa7-b806-f620b1692730
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342247898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3342247898
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4272551958
Short name T936
Test name
Test status
Simulation time 629860637 ps
CPU time 1.25 seconds
Started Jul 06 04:46:33 PM PDT 24
Finished Jul 06 04:46:35 PM PDT 24
Peak memory 196812 kb
Host smart-45d10883-cc22-4a58-88ce-00645c221038
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4272551958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4272551958
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2057180751
Short name T855
Test name
Test status
Simulation time 53827064 ps
CPU time 1.54 seconds
Started Jul 06 04:46:34 PM PDT 24
Finished Jul 06 04:46:36 PM PDT 24
Peak memory 198288 kb
Host smart-603f5b5e-731f-4e7f-bfb5-197e28230d2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057180751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2057180751
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1258489828
Short name T890
Test name
Test status
Simulation time 52089065 ps
CPU time 1.45 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 197076 kb
Host smart-93ece328-71fb-4ad4-be19-90248b46df73
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1258489828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1258489828
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.383889971
Short name T912
Test name
Test status
Simulation time 67155479 ps
CPU time 1.37 seconds
Started Jul 06 04:46:33 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 198288 kb
Host smart-a1e7b64c-6cf0-4ca6-89de-6af145d1f367
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383889971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.383889971
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3181786857
Short name T943
Test name
Test status
Simulation time 50105609 ps
CPU time 1.11 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:34 PM PDT 24
Peak memory 196824 kb
Host smart-4f5ebb86-03b4-4244-b0db-9f189381631f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3181786857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3181786857
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3781105195
Short name T880
Test name
Test status
Simulation time 36575939 ps
CPU time 1.24 seconds
Started Jul 06 04:46:36 PM PDT 24
Finished Jul 06 04:46:38 PM PDT 24
Peak memory 197328 kb
Host smart-12cfc535-ca3f-41c1-8465-0d9935a3dd49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781105195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3781105195
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3979139559
Short name T849
Test name
Test status
Simulation time 71728559 ps
CPU time 0.92 seconds
Started Jul 06 04:46:32 PM PDT 24
Finished Jul 06 04:46:33 PM PDT 24
Peak memory 196536 kb
Host smart-8d0f69cf-5a79-46b1-8827-31d2beb377b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3979139559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3979139559
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3586130244
Short name T928
Test name
Test status
Simulation time 42264963 ps
CPU time 1.19 seconds
Started Jul 06 04:46:35 PM PDT 24
Finished Jul 06 04:46:37 PM PDT 24
Peak memory 196700 kb
Host smart-8c6c4a06-37cb-4d1e-8405-e4aecba81905
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586130244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3586130244
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2897061833
Short name T887
Test name
Test status
Simulation time 91992215 ps
CPU time 1.06 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 196984 kb
Host smart-c9fefa1e-708f-4573-af83-6e6d53657d6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2897061833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2897061833
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1015039372
Short name T900
Test name
Test status
Simulation time 35296775 ps
CPU time 0.87 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:26 PM PDT 24
Peak memory 195696 kb
Host smart-d3f30065-03cf-4e52-a0a5-e3a8c47ef522
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015039372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1015039372
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3760864409
Short name T857
Test name
Test status
Simulation time 37836076 ps
CPU time 1.11 seconds
Started Jul 06 04:46:19 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 195684 kb
Host smart-dc24237d-eccf-44f4-b7ac-cc43b46fb567
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3760864409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3760864409
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707633167
Short name T889
Test name
Test status
Simulation time 480862498 ps
CPU time 1.24 seconds
Started Jul 06 04:46:27 PM PDT 24
Finished Jul 06 04:46:28 PM PDT 24
Peak memory 196204 kb
Host smart-163903de-6fb1-4749-a12e-84fa96524d5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707633167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1707633167
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3278102239
Short name T901
Test name
Test status
Simulation time 120565083 ps
CPU time 1.45 seconds
Started Jul 06 04:46:18 PM PDT 24
Finished Jul 06 04:46:21 PM PDT 24
Peak memory 198372 kb
Host smart-64d5b8a0-3b3d-4ad5-83e2-e15e1c4d7c76
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3278102239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3278102239
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.572026522
Short name T874
Test name
Test status
Simulation time 55622894 ps
CPU time 1.25 seconds
Started Jul 06 04:46:22 PM PDT 24
Finished Jul 06 04:46:24 PM PDT 24
Peak memory 196924 kb
Host smart-0bd97486-41d0-4eed-92b1-a7b5426a161c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572026522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.572026522
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.398615116
Short name T917
Test name
Test status
Simulation time 107142487 ps
CPU time 1 seconds
Started Jul 06 04:46:20 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 196508 kb
Host smart-eab1bdf4-cd95-4592-b785-8e7cdf383c57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=398615116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.398615116
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.519270525
Short name T941
Test name
Test status
Simulation time 84164479 ps
CPU time 0.88 seconds
Started Jul 06 04:46:21 PM PDT 24
Finished Jul 06 04:46:22 PM PDT 24
Peak memory 195768 kb
Host smart-132b9059-d3dd-48e7-9b74-1d06d7b5abb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519270525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.519270525
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2611023418
Short name T906
Test name
Test status
Simulation time 52349333 ps
CPU time 0.96 seconds
Started Jul 06 04:46:25 PM PDT 24
Finished Jul 06 04:46:27 PM PDT 24
Peak memory 196764 kb
Host smart-30dc3c71-c754-4383-8a54-771e5f4ea1e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2611023418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2611023418
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.887547526
Short name T876
Test name
Test status
Simulation time 275689264 ps
CPU time 1.23 seconds
Started Jul 06 04:46:21 PM PDT 24
Finished Jul 06 04:46:23 PM PDT 24
Peak memory 196836 kb
Host smart-093c7269-a949-4dce-a8b6-3c8d69c2cb36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887547526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.887547526
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%