Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4503306	1			T23	82		T24	1		T25	1
all_pins[1]	4503306	1			T23	82		T24	1		T25	1
all_pins[2]	4503306	1			T23	82		T24	1		T25	1
all_pins[3]	4503306	1			T23	82		T24	1		T25	1
all_pins[4]	4503306	1			T23	82		T24	1		T25	1
all_pins[5]	4503306	1			T23	82		T24	1		T25	1
all_pins[6]	4503306	1			T23	82		T24	1		T25	1
all_pins[7]	4503306	1			T23	82		T24	1		T25	1
all_pins[8]	4503306	1			T23	82		T24	1		T25	1
all_pins[9]	4503306	1			T23	82		T24	1		T25	1
all_pins[10]	4503306	1			T23	82		T24	1		T25	1
all_pins[11]	4503306	1			T23	82		T24	1		T25	1
all_pins[12]	4503306	1			T23	82		T24	1		T25	1
all_pins[13]	4503306	1			T23	82		T24	1		T25	1
all_pins[14]	4503306	1			T23	82		T24	1		T25	1
all_pins[15]	4503306	1			T23	82		T24	1		T25	1
all_pins[16]	4503306	1			T23	82		T24	1		T25	1
all_pins[17]	4503306	1			T23	82		T24	1		T25	1
all_pins[18]	4503306	1			T23	82		T24	1		T25	1
all_pins[19]	4503306	1			T23	82		T24	1		T25	1
all_pins[20]	4503306	1			T23	82		T24	1		T25	1
all_pins[21]	4503306	1			T23	82		T24	1		T25	1
all_pins[22]	4503306	1			T23	82		T24	1		T25	1
all_pins[23]	4503306	1			T23	82		T24	1		T25	1
all_pins[24]	4503306	1			T23	82		T24	1		T25	1
all_pins[25]	4503306	1			T23	82		T24	1		T25	1
all_pins[26]	4503306	1			T23	82		T24	1		T25	1
all_pins[27]	4503306	1			T23	82		T24	1		T25	1
all_pins[28]	4503306	1			T23	82		T24	1		T25	1
all_pins[29]	4503306	1			T23	82		T24	1		T25	1
all_pins[30]	4503306	1			T23	82		T24	1		T25	1
all_pins[31]	4503306	1			T23	82		T24	1		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	89507330	1			T23	1401		T24	32		T25	32
values[0x1]	54598462	1			T23	1223		T26	63		T29	112899
transitions[0x0=>0x1]	32706870	1			T23	623		T26	50		T29	67172
transitions[0x1=>0x0]	32706716	1			T23	622		T26	50		T29	67172

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2797739	1			T23	48		T24	1		T25	1
all_pins[0]	values[0x1]	1705567	1			T23	34		T29	3358		T1	14338
all_pins[0]	transitions[0x0=>0x1]	1054234	1			T23	19		T29	2080		T1	8672
all_pins[0]	transitions[0x1=>0x0]	1057202	1			T23	12		T26	7		T29	2089
all_pins[1]	values[0x0]	2791701	1			T23	44		T24	1		T25	1
all_pins[1]	values[0x1]	1711605	1			T23	38		T26	2		T29	3588
all_pins[1]	transitions[0x0=>0x1]	1023104	1			T23	21		T26	2		T29	2249
all_pins[1]	transitions[0x1=>0x0]	1017066	1			T23	17		T29	2019		T1	8261
all_pins[2]	values[0x0]	2797598	1			T23	42		T24	1		T25	1
all_pins[2]	values[0x1]	1705708	1			T23	40		T26	5		T29	3346
all_pins[2]	transitions[0x0=>0x1]	1016893	1			T23	22		T26	5		T29	2060
all_pins[2]	transitions[0x1=>0x0]	1022790	1			T23	20		T26	2		T29	2302
all_pins[3]	values[0x0]	2800036	1			T23	45		T24	1		T25	1
all_pins[3]	values[0x1]	1703270	1			T23	37		T26	1		T29	3498
all_pins[3]	transitions[0x0=>0x1]	1017670	1			T23	20		T29	2193		T1	8540
all_pins[3]	transitions[0x1=>0x0]	1020108	1			T23	23		T26	4		T29	2041
all_pins[4]	values[0x0]	2798535	1			T23	49		T24	1		T25	1
all_pins[4]	values[0x1]	1704771	1			T23	33		T29	3721		T1	14353
all_pins[4]	transitions[0x0=>0x1]	1022174	1			T23	19		T29	2229		T1	8383
all_pins[4]	transitions[0x1=>0x0]	1020673	1			T23	23		T26	1		T29	2006
all_pins[5]	values[0x0]	2795147	1			T23	48		T24	1		T25	1
all_pins[5]	values[0x1]	1708159	1			T23	34		T29	3438		T1	14426
all_pins[5]	transitions[0x0=>0x1]	1026594	1			T23	18		T29	2113		T1	8408
all_pins[5]	transitions[0x1=>0x0]	1023206	1			T23	17		T29	2396		T1	8335
all_pins[6]	values[0x0]	2793017	1			T23	42		T24	1		T25	1
all_pins[6]	values[0x1]	1710289	1			T23	40		T26	1		T29	3562
all_pins[6]	transitions[0x0=>0x1]	1023642	1			T23	20		T26	1		T29	2179
all_pins[6]	transitions[0x1=>0x0]	1021512	1			T23	14		T29	2055		T1	8437
all_pins[7]	values[0x0]	2792372	1			T23	32		T24	1		T25	1
all_pins[7]	values[0x1]	1710934	1			T23	50		T29	3485		T1	14068
all_pins[7]	transitions[0x0=>0x1]	1022771	1			T23	28		T29	2106		T1	8311
all_pins[7]	transitions[0x1=>0x0]	1022126	1			T23	18		T26	1		T29	2183
all_pins[8]	values[0x0]	2798471	1			T23	56		T24	1		T25	1
all_pins[8]	values[0x1]	1704835	1			T23	26		T29	3562		T1	13683
all_pins[8]	transitions[0x0=>0x1]	1019062	1			T23	7		T29	2093		T1	8241
all_pins[8]	transitions[0x1=>0x0]	1025161	1			T23	31		T29	2016		T1	8626
all_pins[9]	values[0x0]	2797232	1			T23	44		T24	1		T25	1
all_pins[9]	values[0x1]	1706074	1			T23	38		T26	2		T29	3418
all_pins[9]	transitions[0x0=>0x1]	1021919	1			T23	25		T26	2		T29	2005
all_pins[9]	transitions[0x1=>0x0]	1020680	1			T23	13		T29	2149		T1	8288
all_pins[10]	values[0x0]	2795751	1			T23	47		T24	1		T25	1
all_pins[10]	values[0x1]	1707555	1			T23	35		T29	3524		T1	13581
all_pins[10]	transitions[0x0=>0x1]	1022955	1			T23	13		T29	2155		T1	8313
all_pins[10]	transitions[0x1=>0x0]	1021474	1			T23	16		T26	2		T29	2049
all_pins[11]	values[0x0]	2801954	1			T23	44		T24	1		T25	1
all_pins[11]	values[0x1]	1701352	1			T23	38		T29	3324		T1	13952
all_pins[11]	transitions[0x0=>0x1]	1017831	1			T23	22		T29	2052		T1	8570
all_pins[11]	transitions[0x1=>0x0]	1024034	1			T23	19		T29	2252		T1	8199
all_pins[12]	values[0x0]	2796761	1			T23	39		T24	1		T25	1
all_pins[12]	values[0x1]	1706545	1			T23	43		T26	2		T29	3449
all_pins[12]	transitions[0x0=>0x1]	1020691	1			T23	18		T26	2		T29	2137
all_pins[12]	transitions[0x1=>0x0]	1015498	1			T23	13		T29	2012		T1	8255
all_pins[13]	values[0x0]	2800674	1			T23	38		T24	1		T25	1
all_pins[13]	values[0x1]	1702632	1			T23	44		T29	3834		T1	14192
all_pins[13]	transitions[0x0=>0x1]	1017468	1			T23	18		T29	2300		T1	8761
all_pins[13]	transitions[0x1=>0x0]	1021381	1			T23	17		T26	2		T29	1915
all_pins[14]	values[0x0]	2800956	1			T23	43		T24	1		T25	1
all_pins[14]	values[0x1]	1702350	1			T23	39		T26	7		T29	3675
all_pins[14]	transitions[0x0=>0x1]	1020850	1			T23	19		T26	7		T29	1960
all_pins[14]	transitions[0x1=>0x0]	1021132	1			T23	24		T29	2119		T1	8485
all_pins[15]	values[0x0]	2798651	1			T23	45		T24	1		T25	1
all_pins[15]	values[0x1]	1704655	1			T23	37		T29	3835		T1	13924
all_pins[15]	transitions[0x0=>0x1]	1022160	1			T23	21		T29	2227		T1	8342
all_pins[15]	transitions[0x1=>0x0]	1019855	1			T23	23		T26	7		T29	2067
all_pins[16]	values[0x0]	2794718	1			T23	49		T24	1		T25	1
all_pins[16]	values[0x1]	1708588	1			T23	33		T29	3702		T1	13773
all_pins[16]	transitions[0x0=>0x1]	1022249	1			T23	17		T29	2059		T1	8331
all_pins[16]	transitions[0x1=>0x0]	1018316	1			T23	21		T29	2192		T1	8482
all_pins[17]	values[0x0]	2798539	1			T23	39		T24	1		T25	1
all_pins[17]	values[0x1]	1704767	1			T23	43		T26	2		T29	3572
all_pins[17]	transitions[0x0=>0x1]	1017900	1			T23	25		T26	2		T29	2052
all_pins[17]	transitions[0x1=>0x0]	1021721	1			T23	15		T29	2182		T1	8092
all_pins[18]	values[0x0]	2797166	1			T23	47		T24	1		T25	1
all_pins[18]	values[0x1]	1706140	1			T23	35		T26	2		T29	3538
all_pins[18]	transitions[0x0=>0x1]	1023512	1			T23	16		T26	2		T29	2056
all_pins[18]	transitions[0x1=>0x0]	1022139	1			T23	24		T26	2		T29	2090
all_pins[19]	values[0x0]	2795938	1			T23	40		T24	1		T25	1
all_pins[19]	values[0x1]	1707368	1			T23	42		T26	1		T29	3476
all_pins[19]	transitions[0x0=>0x1]	1019493	1			T23	26		T29	2021		T1	8609
all_pins[19]	transitions[0x1=>0x0]	1018265	1			T23	19		T26	1		T29	2083
all_pins[20]	values[0x0]	2793849	1			T23	41		T24	1		T25	1
all_pins[20]	values[0x1]	1709457	1			T23	41		T29	3618		T1	13689
all_pins[20]	transitions[0x0=>0x1]	1024831	1			T23	19		T29	2197		T1	8157
all_pins[20]	transitions[0x1=>0x0]	1022742	1			T23	20		T26	1		T29	2055
all_pins[21]	values[0x0]	2796846	1			T23	43		T24	1		T25	1
all_pins[21]	values[0x1]	1706460	1			T23	39		T26	1		T29	3583
all_pins[21]	transitions[0x0=>0x1]	1019715	1			T23	19		T26	1		T29	2030
all_pins[21]	transitions[0x1=>0x0]	1022712	1			T23	21		T29	2065		T1	8101
all_pins[22]	values[0x0]	2796988	1			T23	38		T24	1		T25	1
all_pins[22]	values[0x1]	1706318	1			T23	44		T29	3381		T1	14677
all_pins[22]	transitions[0x0=>0x1]	1020365	1			T23	24		T29	1883		T1	8602
all_pins[22]	transitions[0x1=>0x0]	1020507	1			T23	19		T26	1		T29	2085
all_pins[23]	values[0x0]	2796942	1			T23	43		T24	1		T25	1
all_pins[23]	values[0x1]	1706364	1			T23	39		T26	10		T29	3348
all_pins[23]	transitions[0x0=>0x1]	1022401	1			T23	16		T26	10		T29	1963
all_pins[23]	transitions[0x1=>0x0]	1022355	1			T23	21		T29	1996		T1	8696
all_pins[24]	values[0x0]	2795560	1			T23	33		T24	1		T25	1
all_pins[24]	values[0x1]	1707746	1			T23	49		T29	3504		T1	14263
all_pins[24]	transitions[0x0=>0x1]	1020342	1			T23	27		T29	2134		T1	8543
all_pins[24]	transitions[0x1=>0x0]	1018960	1			T23	17		T26	10		T29	1978
all_pins[25]	values[0x0]	2802703	1			T23	42		T24	1		T25	1
all_pins[25]	values[0x1]	1700603	1			T23	40		T29	3493		T1	14230
all_pins[25]	transitions[0x0=>0x1]	1015580	1			T23	17		T29	2116		T1	8416
all_pins[25]	transitions[0x1=>0x0]	1022723	1			T23	26		T29	2127		T1	8449
all_pins[26]	values[0x0]	2794904	1			T23	43		T24	1		T25	1
all_pins[26]	values[0x1]	1708402	1			T23	39		T29	3710		T1	13812
all_pins[26]	transitions[0x0=>0x1]	1023813	1			T23	18		T29	2179		T1	8221
all_pins[26]	transitions[0x1=>0x0]	1016014	1			T23	19		T29	1962		T1	8639
all_pins[27]	values[0x0]	2794731	1			T23	47		T24	1		T25	1
all_pins[27]	values[0x1]	1708575	1			T23	35		T29	3633		T1	14341
all_pins[27]	transitions[0x0=>0x1]	1021694	1			T23	16		T29	2084		T1	8870
all_pins[27]	transitions[0x1=>0x0]	1021521	1			T23	20		T29	2161		T1	8341
all_pins[28]	values[0x0]	2798643	1			T23	49		T24	1		T25	1
all_pins[28]	values[0x1]	1704663	1			T23	33		T26	10		T29	3392
all_pins[28]	transitions[0x0=>0x1]	1018350	1			T23	20		T26	10		T29	2101
all_pins[28]	transitions[0x1=>0x0]	1022262	1			T23	22		T29	2342		T1	8420
all_pins[29]	values[0x0]	2799758	1			T23	43		T24	1		T25	1
all_pins[29]	values[0x1]	1703548	1			T23	39		T26	5		T29	3365
all_pins[29]	transitions[0x0=>0x1]	1021572	1			T23	23		T29	1944		T1	8401
all_pins[29]	transitions[0x1=>0x0]	1022687	1			T23	17		T26	5		T29	1971
all_pins[30]	values[0x0]	2798833	1			T23	44		T24	1		T25	1
all_pins[30]	values[0x1]	1704473	1			T23	38		T26	5		T29	3600
all_pins[30]	transitions[0x0=>0x1]	1022845	1			T23	17		T26	4		T29	2141
all_pins[30]	transitions[0x1=>0x0]	1021920	1			T23	18		T26	4		T29	1906
all_pins[31]	values[0x0]	2794617	1			T23	54		T24	1		T25	1
all_pins[31]	values[0x1]	1708689	1			T23	28		T26	7		T29	3367
all_pins[31]	transitions[0x0=>0x1]	1022190	1			T23	13		T26	2		T29	2074
all_pins[31]	transitions[0x1=>0x0]	1017974	1			T23	23		T29	2307		T1	8097