Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[1]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[2]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[3]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[4]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[5]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[6]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[7]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[8]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[9]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[10]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[11]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[12]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[13]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[14]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[15]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[16]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[17]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[18]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[19]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[20]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[21]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[22]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[23]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[24]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[25]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[26]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[27]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[28]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[29]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[30]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[31]	14674819	1			T23	1271		T24	191		T25	589

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

278006065

1

T23

19791

T24

4643

T25

5530

auto[1]

191588143

1

T23

20881

T24

1469

T25

13318

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

376014844

1

T23

40672

T24

5757

T25

11269

auto[1]

93579364

1

T24

355

T25

7579

T26

250

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

348563076

1

T23

40672

T24

2942

T25

11227

auto[1]

121031132

1

T24

3170

T25

7621

T26

613

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5394012	1			T23	614		T24	23		T25	53
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4022774	1			T23	657		T24	3		T25	167
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1468163	1			T25	109		T26	6		T27	218
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1828256	1			T24	127		T26	6		T27	177
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	501672	1			T24	28		T25	144		T26	4
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1459942	1			T24	10		T25	116		T26	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5384392	1			T23	621		T24	37		T25	58
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4036833	1			T23	650		T24	6		T25	166
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1476431	1			T25	142		T27	195		T29	4537
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1819575	1			T24	106		T26	9		T27	158
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	498776	1			T24	36		T25	121		T26	3
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1458812	1			T24	6		T25	102		T26	9
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5386721	1			T23	610		T24	55		T25	51
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4035047	1			T23	661		T24	24		T25	190
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1474453	1			T24	4		T25	88		T27	215
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1818045	1			T24	76		T26	16		T27	178
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	500752	1			T24	20		T25	132		T26	5
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1459801	1			T24	12		T25	128		T26	6
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5391645	1			T23	612		T24	72		T25	47
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4024716	1			T23	659		T24	15		T25	209
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1469956	1			T24	2		T25	86		T26	6
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1830173	1			T24	73		T27	212		T29	7712
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	500421	1			T24	17		T25	124		T29	649
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1457908	1			T24	12		T25	123		T27	168
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5403769	1			T23	621		T24	76		T25	56
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4020084	1			T23	650		T24	24		T25	176
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1469221	1			T24	2		T25	129		T27	196
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1825167	1			T24	70		T26	4		T27	168
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	502869	1			T24	15		T25	104		T26	5
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1453709	1			T24	4		T25	124		T26	7
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5393328	1			T23	636		T24	48		T25	49
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4030569	1			T23	635		T24	14		T25	183
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1472273	1			T25	118		T27	206		T29	4573
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1822117	1			T24	99		T26	26		T27	166
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	499957	1			T24	28		T25	120		T26	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1456575	1			T24	2		T25	119		T26	6
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5390074	1			T23	633		T24	112		T25	57
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4027974	1			T23	638		T24	26		T25	189
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1473596	1			T24	2		T25	91		T27	170
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1822839	1			T24	34		T26	14		T27	240
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	502205	1			T24	13		T25	122		T26	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1458131	1			T24	4		T25	130		T26	3
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5403979	1			T23	670		T24	68		T25	55
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4016789	1			T23	601		T24	20		T25	170
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1469724	1			T24	6		T25	120		T27	156
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1824493	1			T24	72		T27	211		T29	6764
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	499169	1			T24	19		T25	136		T29	552
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1460665	1			T24	6		T25	108		T27	184
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5387062	1			T23	622		T24	68		T25	55
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4034871	1			T23	649		T24	14		T25	170
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1470921	1			T24	4		T25	140		T27	168
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1821264	1			T24	75		T26	7		T27	208
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	502073	1			T24	26		T25	120		T26	9
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1458628	1			T24	4		T25	104		T26	12
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5406370	1			T23	556		T24	98		T25	51
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4019118	1			T23	715		T24	29		T25	171
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1473360	1			T24	5		T25	128		T26	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1816765	1			T24	42		T26	5		T27	176
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	502785	1			T24	11		T25	103		T26	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1456421	1			T24	6		T25	136		T26	9
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5395280	1			T23	547		T24	61		T25	52
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4026889	1			T23	724		T24	19		T25	166
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1472058	1			T24	10		T25	144		T27	191
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1825567	1			T24	68		T26	8		T27	194
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	500208	1			T24	25		T25	107		T26	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1454817	1			T24	8		T25	120		T26	5
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5391542	1			T23	701		T24	35		T25	54
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4028935	1			T23	570		T24	18		T25	198
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1475397	1			T24	4		T25	101		T26	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1822323	1			T24	111		T26	7		T27	167
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	500453	1			T24	19		T25	144		T26	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1456169	1			T24	4		T25	92		T26	8
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5381515	1			T23	619		T24	109		T25	51
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4035741	1			T23	652		T24	24		T25	157
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1475057	1			T24	7		T25	142		T26	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1822143	1			T24	41		T26	5		T27	209
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	504280	1			T24	6		T25	109		T26	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1456083	1			T24	4		T25	130		T26	4
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5393592	1			T23	702		T24	96		T25	54
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4030123	1			T23	569		T24	24		T25	178
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1470522	1			T24	2		T25	102		T27	180
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1826980	1			T24	59		T27	199		T29	6914
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	501134	1			T24	6		T25	148		T26	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1452468	1			T24	4		T25	107		T26	16
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5386692	1			T23	576		T24	84		T25	53
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4031815	1			T23	695		T24	17		T25	158
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1474531	1			T24	4		T25	106		T26	3
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1823893	1			T24	59		T26	9		T27	212
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	496413	1			T24	17		T25	142		T26	6
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1461475	1			T24	10		T25	130		T26	16
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5383108	1			T23	614		T24	25		T25	53
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4035063	1			T23	657		T24	7		T25	192
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1470334	1			T25	120		T26	6		T27	192
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1827108	1			T24	121		T26	11		T27	172
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	502335	1			T24	36		T25	104		T26	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1456871	1			T24	2		T25	120		T26	3
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5383529	1			T23	598		T24	86		T25	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4039795	1			T23	673		T24	21		T25	185
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1468364	1			T24	11		T25	134		T27	147
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1826739	1			T24	48		T27	174		T29	7136
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	500799	1			T24	21		T25	110		T26	3
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1455593	1			T24	4		T25	106		T26	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5393296	1			T23	625		T24	20		T25	58
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4035821	1			T23	646		T24	3		T25	195
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1466076	1			T25	136		T27	185		T29	4732
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1822439	1			T24	144		T26	1		T27	168
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	501663	1			T24	22		T25	116		T26	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1455524	1			T24	2		T25	84		T26	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5393118	1			T23	613		T24	38		T25	51
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4032976	1			T23	658		T24	8		T25	167
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1466590	1			T24	2		T25	136		T26	3
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1830608	1			T24	97		T26	11		T27	210
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	500603	1			T24	32		T25	122		T26	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1450924	1			T24	14		T25	113		T26	11
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5402521	1			T23	590		T24	111		T25	57
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4027258	1			T23	681		T24	33		T25	198
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1462254	1			T24	8		T25	122		T26	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1825821	1			T24	24		T27	209		T29	7617
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	504105	1			T24	13		T25	110		T26	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1452860	1			T24	2		T25	102		T26	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5401866	1			T23	667		T24	108		T25	60
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4031158	1			T23	604		T24	30		T25	166
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1464775	1			T24	11		T25	127		T26	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1829468	1			T24	33		T26	14		T27	171
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	500783	1			T24	9		T25	106		T26	8
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1446769	1			T25	130		T26	7		T27	204
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5390750	1			T23	632		T24	82		T25	42
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4033395	1			T23	639		T24	22		T25	197
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1468104	1			T24	8		T25	110		T26	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1831103	1			T24	56		T26	3		T27	182
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	500965	1			T24	17		T25	126		T26	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1450502	1			T24	6		T25	114		T26	3
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5406473	1			T23	659		T24	59		T25	56
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4016757	1			T23	612		T24	16		T25	216
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1468314	1			T24	3		T25	110		T27	160
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1826268	1			T24	74		T26	6		T27	203
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	502810	1			T24	25		T25	116		T26	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1454197	1			T24	14		T25	91		T26	3
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5391814	1			T23	637		T24	77		T25	52
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4035345	1			T23	634		T24	25		T25	174
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1463911	1			T24	3		T25	104		T27	147
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1829023	1			T24	67		T26	13		T27	202
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	499142	1			T24	13		T25	139		T26	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1455584	1			T24	6		T25	120		T26	3
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5387492	1			T23	576		T24	85		T25	53
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4035366	1			T23	695		T24	37		T25	152
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1460423	1			T24	8		T25	132		T27	193
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1831655	1			T24	44		T26	19		T27	160
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	503081	1			T24	7		T25	116		T29	673
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1456802	1			T24	10		T25	136		T26	8
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5396887	1			T23	613		T24	64		T25	54
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4027026	1			T23	658		T24	14		T25	184
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1464749	1			T24	8		T25	108		T26	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1827880	1			T24	78		T26	14		T27	134
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	503636	1			T24	23		T25	119		T26	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1454641	1			T24	4		T25	124		T26	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5400983	1			T23	577		T24	85		T25	57
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4024626	1			T23	694		T24	36		T25	185
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1460525	1			T24	7		T25	128		T26	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1828563	1			T24	50		T26	2		T27	164
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	505962	1			T24	11		T25	127		T26	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1454160	1			T24	2		T25	92		T27	175
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5399732	1			T23	594		T24	52		T25	53
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4028616	1			T23	677		T24	8		T25	187
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1466108	1			T24	2		T25	122		T27	188
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1822656	1			T24	92		T26	12		T27	194
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	499630	1			T24	21		T25	84		T26	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1458077	1			T24	16		T25	143		T26	3
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5389377	1			T23	548		T24	67		T25	46
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4033790	1			T23	723		T24	15		T25	200
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1467942	1			T24	10		T25	111		T27	188
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1825215	1			T24	71		T26	10		T27	206
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	503342	1			T24	22		T25	114		T26	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1455153	1			T24	6		T25	118		T26	6
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5393847	1			T23	674		T24	67		T25	62
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4038985	1			T23	597		T24	29		T25	142
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1466792	1			T24	4		T25	94		T27	193
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1824973	1			T24	57		T26	1		T27	200
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	498164	1			T24	18		T25	136		T26	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1452058	1			T24	16		T25	155		T26	3
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5403930	1			T23	656		T24	81		T25	57
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4028985	1			T23	615		T24	37		T25	141
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1468256	1			T24	6		T25	144		T26	3
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1821646	1			T24	47		T26	4		T27	139
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	502212	1			T24	16		T25	114		T26	6
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1449790	1			T24	4		T25	133		T26	12
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5388911	1			T23	578		T24	27		T25	64
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4036242	1			T23	693		T24	5		T25	168
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1462807	1			T25	121		T27	162		T29	4404
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1825706	1			T24	109		T26	11		T27	204
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	504885	1			T24	42		T25	112		T26	4
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1456268	1			T24	8		T25	124		T26	4

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal