Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[1]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[2]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[3]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[4]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[5]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[6]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[7]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[8]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[9]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[10]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[11]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[12]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[13]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[14]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[15]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[16]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[17]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[18]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[19]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[20]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[21]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[22]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[23]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[24]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[25]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[26]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[27]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[28]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[29]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[30]	14674819	1			T23	1271		T24	191		T25	589
bins_for_gpio_bits[31]	14674819	1			T23	1271		T24	191		T25	589

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

278006065

1

T23

19791

T24

4643

T25

5530

auto[1]

191588143

1

T23

20881

T24

1469

T25

13318

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

277999117

1

T23

19791

T24

4643

T25

5537

auto[1]

191595091

1

T23

20881

T24

1469

T25

13311

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8429618	1			T23	614		T24	146		T25	137
bins_for_gpio_bits[0]	auto[0]	auto[1]	260554	1			T24	4		T25	26		T27	44
bins_for_gpio_bits[0]	auto[1]	auto[0]	260813	1			T24	4		T25	25		T27	44
bins_for_gpio_bits[0]	auto[1]	auto[1]	5723834	1			T23	657		T24	37		T25	401
bins_for_gpio_bits[1]	auto[0]	auto[0]	8419833	1			T23	621		T24	141		T25	167
bins_for_gpio_bits[1]	auto[0]	auto[1]	260341	1			T24	2		T25	33		T27	44
bins_for_gpio_bits[1]	auto[1]	auto[0]	260565	1			T24	2		T25	33		T26	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5734080	1			T23	650		T24	46		T25	356
bins_for_gpio_bits[2]	auto[0]	auto[0]	8419187	1			T23	610		T24	132		T25	116
bins_for_gpio_bits[2]	auto[0]	auto[1]	259810	1			T24	3		T25	23		T26	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	260032	1			T24	3		T25	23		T26	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5735790	1			T23	661		T24	53		T25	427
bins_for_gpio_bits[3]	auto[0]	auto[0]	8431221	1			T23	612		T24	145		T25	107
bins_for_gpio_bits[3]	auto[0]	auto[1]	260346	1			T24	2		T25	26		T27	43
bins_for_gpio_bits[3]	auto[1]	auto[0]	260553	1			T24	2		T25	26		T27	43
bins_for_gpio_bits[3]	auto[1]	auto[1]	5722699	1			T23	659		T24	42		T25	430
bins_for_gpio_bits[4]	auto[0]	auto[0]	8437486	1			T23	621		T24	146		T25	154
bins_for_gpio_bits[4]	auto[0]	auto[1]	260486	1			T24	2		T25	32		T27	52
bins_for_gpio_bits[4]	auto[1]	auto[0]	260671	1			T24	2		T25	31		T27	52
bins_for_gpio_bits[4]	auto[1]	auto[1]	5716176	1			T23	650		T24	41		T25	372
bins_for_gpio_bits[5]	auto[0]	auto[0]	8426750	1			T23	636		T24	146		T25	136
bins_for_gpio_bits[5]	auto[0]	auto[1]	260745	1			T24	1		T25	31		T26	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	260968	1			T24	1		T25	31		T26	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5726356	1			T23	635		T24	43		T25	391
bins_for_gpio_bits[6]	auto[0]	auto[0]	8426137	1			T23	633		T24	147		T25	124
bins_for_gpio_bits[6]	auto[0]	auto[1]	260178	1			T24	1		T25	25		T27	39
bins_for_gpio_bits[6]	auto[1]	auto[0]	260372	1			T24	1		T25	24		T27	40
bins_for_gpio_bits[6]	auto[1]	auto[1]	5728132	1			T23	638		T24	42		T25	416
bins_for_gpio_bits[7]	auto[0]	auto[0]	8437130	1			T23	670		T24	143		T25	144
bins_for_gpio_bits[7]	auto[0]	auto[1]	260836	1			T24	3		T25	31		T27	46
bins_for_gpio_bits[7]	auto[1]	auto[0]	261066	1			T24	3		T25	31		T27	46
bins_for_gpio_bits[7]	auto[1]	auto[1]	5715787	1			T23	601		T24	42		T25	383
bins_for_gpio_bits[8]	auto[0]	auto[0]	8418099	1			T23	622		T24	145		T25	167
bins_for_gpio_bits[8]	auto[0]	auto[1]	260905	1			T24	2		T25	28		T26	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	261148	1			T24	2		T25	28		T26	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	5734667	1			T23	649		T24	42		T25	366
bins_for_gpio_bits[9]	auto[0]	auto[0]	8436641	1			T23	556		T24	144		T25	147
bins_for_gpio_bits[9]	auto[0]	auto[1]	259648	1			T24	1		T25	32		T27	44
bins_for_gpio_bits[9]	auto[1]	auto[0]	259854	1			T24	1		T25	32		T27	44
bins_for_gpio_bits[9]	auto[1]	auto[1]	5718676	1			T23	715		T24	45		T25	378
bins_for_gpio_bits[10]	auto[0]	auto[0]	8432373	1			T23	547		T24	135		T25	166
bins_for_gpio_bits[10]	auto[0]	auto[1]	260345	1			T24	4		T25	30		T27	49
bins_for_gpio_bits[10]	auto[1]	auto[0]	260532	1			T24	4		T25	30		T27	49
bins_for_gpio_bits[10]	auto[1]	auto[1]	5721569	1			T23	724		T24	48		T25	363
bins_for_gpio_bits[11]	auto[0]	auto[0]	8428738	1			T23	701		T24	148		T25	128
bins_for_gpio_bits[11]	auto[0]	auto[1]	260296	1			T24	2		T25	28		T27	47
bins_for_gpio_bits[11]	auto[1]	auto[0]	260524	1			T24	2		T25	27		T27	47
bins_for_gpio_bits[11]	auto[1]	auto[1]	5725261	1			T23	570		T24	39		T25	406
bins_for_gpio_bits[12]	auto[0]	auto[0]	8418175	1			T23	619		T24	155		T25	163
bins_for_gpio_bits[12]	auto[0]	auto[1]	260321	1			T24	2		T25	30		T27	46
bins_for_gpio_bits[12]	auto[1]	auto[0]	260540	1			T24	2		T25	30		T27	46
bins_for_gpio_bits[12]	auto[1]	auto[1]	5735783	1			T23	652		T24	32		T25	366
bins_for_gpio_bits[13]	auto[0]	auto[0]	8431147	1			T23	702		T24	155		T25	130
bins_for_gpio_bits[13]	auto[0]	auto[1]	259738	1			T24	2		T25	26		T27	51
bins_for_gpio_bits[13]	auto[1]	auto[0]	259947	1			T24	2		T25	26		T27	51
bins_for_gpio_bits[13]	auto[1]	auto[1]	5723987	1			T23	569		T24	32		T25	407
bins_for_gpio_bits[14]	auto[0]	auto[0]	8423792	1			T23	576		T24	145		T25	131
bins_for_gpio_bits[14]	auto[0]	auto[1]	261108	1			T24	2		T25	28		T27	45
bins_for_gpio_bits[14]	auto[1]	auto[0]	261324	1			T24	2		T25	28		T26	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5728595	1			T23	695		T24	42		T25	402
bins_for_gpio_bits[15]	auto[0]	auto[0]	8420224	1			T23	614		T24	145		T25	145
bins_for_gpio_bits[15]	auto[0]	auto[1]	260119	1			T24	1		T25	28		T27	51
bins_for_gpio_bits[15]	auto[1]	auto[0]	260326	1			T24	1		T25	28		T27	51
bins_for_gpio_bits[15]	auto[1]	auto[1]	5734150	1			T23	657		T24	44		T25	388
bins_for_gpio_bits[16]	auto[0]	auto[0]	8418126	1			T23	598		T24	143		T25	150
bins_for_gpio_bits[16]	auto[0]	auto[1]	260282	1			T24	2		T25	38		T27	49
bins_for_gpio_bits[16]	auto[1]	auto[0]	260506	1			T24	2		T25	38		T27	49
bins_for_gpio_bits[16]	auto[1]	auto[1]	5735905	1			T23	673		T24	44		T25	363
bins_for_gpio_bits[17]	auto[0]	auto[0]	8421038	1			T23	625		T24	163		T25	164
bins_for_gpio_bits[17]	auto[0]	auto[1]	260543	1			T24	1		T25	30		T27	42
bins_for_gpio_bits[17]	auto[1]	auto[0]	260773	1			T24	1		T25	30		T27	42
bins_for_gpio_bits[17]	auto[1]	auto[1]	5732465	1			T23	646		T24	26		T25	365
bins_for_gpio_bits[18]	auto[0]	auto[0]	8429537	1			T23	613		T24	134		T25	154
bins_for_gpio_bits[18]	auto[0]	auto[1]	260555	1			T24	3		T25	33		T26	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	260779	1			T24	3		T25	33		T26	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5723948	1			T23	658		T24	51		T25	369
bins_for_gpio_bits[19]	auto[0]	auto[0]	8430111	1			T23	590		T24	142		T25	146
bins_for_gpio_bits[19]	auto[0]	auto[1]	260286	1			T24	1		T25	33		T27	52
bins_for_gpio_bits[19]	auto[1]	auto[0]	260485	1			T24	1		T25	33		T27	52
bins_for_gpio_bits[19]	auto[1]	auto[1]	5723937	1			T23	681		T24	47		T25	377
bins_for_gpio_bits[20]	auto[0]	auto[0]	8436059	1			T23	667		T24	152		T25	153
bins_for_gpio_bits[20]	auto[0]	auto[1]	259863	1			T25	35		T26	1		T27	47
bins_for_gpio_bits[20]	auto[1]	auto[0]	260050	1			T25	34		T26	1		T27	47
bins_for_gpio_bits[20]	auto[1]	auto[1]	5718847	1			T23	604		T24	39		T25	367
bins_for_gpio_bits[21]	auto[0]	auto[0]	8428649	1			T23	632		T24	144		T25	125
bins_for_gpio_bits[21]	auto[0]	auto[1]	261070	1			T24	2		T25	27		T27	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	261308	1			T24	2		T25	27		T27	40
bins_for_gpio_bits[21]	auto[1]	auto[1]	5723792	1			T23	639		T24	43		T25	410
bins_for_gpio_bits[22]	auto[0]	auto[0]	8440363	1			T23	659		T24	133		T25	135
bins_for_gpio_bits[22]	auto[0]	auto[1]	260476	1			T24	3		T25	31		T27	39
bins_for_gpio_bits[22]	auto[1]	auto[0]	260692	1			T24	3		T25	31		T27	39
bins_for_gpio_bits[22]	auto[1]	auto[1]	5713288	1			T23	612		T24	52		T25	392
bins_for_gpio_bits[23]	auto[0]	auto[0]	8423731	1			T23	637		T24	145		T25	127
bins_for_gpio_bits[23]	auto[0]	auto[1]	260787	1			T24	2		T25	29		T26	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	261017	1			T24	2		T25	29		T26	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	5729284	1			T23	634		T24	42		T25	404
bins_for_gpio_bits[24]	auto[0]	auto[0]	8418494	1			T23	576		T24	134		T25	161
bins_for_gpio_bits[24]	auto[0]	auto[1]	260838	1			T24	3		T25	24		T27	41
bins_for_gpio_bits[24]	auto[1]	auto[0]	261076	1			T24	3		T25	24		T26	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	5734411	1			T23	695		T24	51		T25	380
bins_for_gpio_bits[25]	auto[0]	auto[0]	8429080	1			T23	613		T24	149		T25	132
bins_for_gpio_bits[25]	auto[0]	auto[1]	260227	1			T24	1		T25	30		T26	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	260436	1			T24	1		T25	30		T26	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	5725076	1			T23	658		T24	40		T25	397
bins_for_gpio_bits[26]	auto[0]	auto[0]	8429385	1			T23	577		T24	141		T25	152
bins_for_gpio_bits[26]	auto[0]	auto[1]	260478	1			T24	1		T25	33		T27	41
bins_for_gpio_bits[26]	auto[1]	auto[0]	260686	1			T24	1		T25	33		T27	42
bins_for_gpio_bits[26]	auto[1]	auto[1]	5724270	1			T23	694		T24	48		T25	371
bins_for_gpio_bits[27]	auto[0]	auto[0]	8427369	1			T23	594		T24	143		T25	138
bins_for_gpio_bits[27]	auto[0]	auto[1]	260946	1			T24	3		T25	37		T27	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	261127	1			T24	3		T25	37		T27	47
bins_for_gpio_bits[27]	auto[1]	auto[1]	5725377	1			T23	677		T24	42		T25	377
bins_for_gpio_bits[28]	auto[0]	auto[0]	8421742	1			T23	548		T24	146		T25	123
bins_for_gpio_bits[28]	auto[0]	auto[1]	260546	1			T24	2		T25	35		T27	50
bins_for_gpio_bits[28]	auto[1]	auto[0]	260792	1			T24	2		T25	34		T27	51
bins_for_gpio_bits[28]	auto[1]	auto[1]	5731739	1			T23	723		T24	41		T25	397
bins_for_gpio_bits[29]	auto[0]	auto[0]	8425141	1			T23	674		T24	125		T25	131
bins_for_gpio_bits[29]	auto[0]	auto[1]	260282	1			T24	3		T25	25		T27	44
bins_for_gpio_bits[29]	auto[1]	auto[0]	260471	1			T24	3		T25	25		T27	44
bins_for_gpio_bits[29]	auto[1]	auto[1]	5728925	1			T23	597		T24	60		T25	408
bins_for_gpio_bits[30]	auto[0]	auto[0]	8433067	1			T23	656		T24	133		T25	169
bins_for_gpio_bits[30]	auto[0]	auto[1]	260542	1			T24	1		T25	32		T26	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	260765	1			T24	1		T25	32		T26	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5720445	1			T23	615		T24	56		T25	356
bins_for_gpio_bits[31]	auto[0]	auto[0]	8417150	1			T23	578		T24	134		T25	154
bins_for_gpio_bits[31]	auto[0]	auto[1]	260027	1			T24	2		T25	32		T27	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	260274	1			T24	2		T25	31		T27	45
bins_for_gpio_bits[31]	auto[1]	auto[1]	5737368	1			T23	693		T24	53		T25	372