Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8598307 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6333632 |
1 |
|
|
T26 |
10 |
|
T29 |
12415 |
|
T1 |
52326 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14121534 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
810405 |
1 |
|
|
T29 |
1189 |
|
T1 |
6470 |
|
T12 |
39080 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8549585 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6382354 |
1 |
|
|
T26 |
12 |
|
T29 |
11881 |
|
T1 |
54150 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2801508 |
1 |
|
|
T26 |
12 |
|
T29 |
5514 |
|
T1 |
25956 |
auto[1] |
auto[0] |
auto[1] |
408065 |
1 |
|
|
T29 |
610 |
|
T1 |
3517 |
|
T12 |
20413 |
auto[1] |
auto[1] |
auto[0] |
2770441 |
1 |
|
|
T29 |
5178 |
|
T1 |
21724 |
|
T12 |
123929 |
auto[1] |
auto[1] |
auto[1] |
402340 |
1 |
|
|
T29 |
579 |
|
T1 |
2953 |
|
T12 |
18667 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |