Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8564779 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6367160 |
1 |
|
|
T26 |
10 |
|
T29 |
11551 |
|
T1 |
55123 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12292959 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
2638980 |
1 |
|
|
T29 |
3971 |
|
T1 |
20528 |
|
T12 |
111274 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8581168 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6350771 |
1 |
|
|
T26 |
6 |
|
T29 |
11474 |
|
T1 |
54499 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1854772 |
1 |
|
|
T29 |
3892 |
|
T1 |
16293 |
|
T12 |
87933 |
auto[1] |
auto[0] |
auto[1] |
1319620 |
1 |
|
|
T29 |
2113 |
|
T1 |
9837 |
|
T12 |
55578 |
auto[1] |
auto[1] |
auto[0] |
1857019 |
1 |
|
|
T26 |
6 |
|
T29 |
3611 |
|
T1 |
17678 |
auto[1] |
auto[1] |
auto[1] |
1319360 |
1 |
|
|
T29 |
1858 |
|
T1 |
10691 |
|
T12 |
55696 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |