Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8572705 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
6359234 |
1 |
|
|
T26 |
6 |
|
T29 |
12142 |
|
T1 |
53398 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2792989 |
1 |
|
|
T26 |
5 |
|
T29 |
5516 |
|
T1 |
24283 |
| auto[1] |
auto[0] |
auto[1] |
407310 |
1 |
|
|
T26 |
1 |
|
T29 |
611 |
|
T1 |
3194 |
| auto[1] |
auto[1] |
auto[0] |
2758253 |
1 |
|
|
T29 |
5402 |
|
T1 |
22802 |
|
T12 |
123439 |
| auto[1] |
auto[1] |
auto[1] |
400682 |
1 |
|
|
T29 |
613 |
|
T1 |
3119 |
|
T12 |
18447 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |