Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8562186 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6369753 |
1 |
|
|
T29 |
13194 |
|
T1 |
54883 |
|
T12 |
289457 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12297566 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
2634373 |
1 |
|
|
T26 |
5 |
|
T29 |
4390 |
|
T1 |
20197 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8590041 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6341898 |
1 |
|
|
T26 |
5 |
|
T29 |
12661 |
|
T1 |
53497 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1857842 |
1 |
|
|
T29 |
4069 |
|
T1 |
16332 |
|
T12 |
87910 |
auto[1] |
auto[0] |
auto[1] |
1318910 |
1 |
|
|
T26 |
5 |
|
T29 |
1980 |
|
T1 |
10080 |
auto[1] |
auto[1] |
auto[0] |
1849683 |
1 |
|
|
T29 |
4202 |
|
T1 |
16968 |
|
T12 |
91593 |
auto[1] |
auto[1] |
auto[1] |
1315463 |
1 |
|
|
T29 |
2410 |
|
T1 |
10117 |
|
T12 |
56206 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |