Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8573904 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
6358035 |
1 |
|
|
T29 |
12532 |
|
T1 |
55115 |
|
T12 |
288894 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12300653 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
2631286 |
1 |
|
|
T29 |
4463 |
|
T1 |
19806 |
|
T12 |
112053 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8583538 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
6348401 |
1 |
|
|
T26 |
9 |
|
T29 |
12679 |
|
T1 |
53331 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1860794 |
1 |
|
|
T26 |
9 |
|
T29 |
4250 |
|
T1 |
16608 |
| auto[1] |
auto[0] |
auto[1] |
1318721 |
1 |
|
|
T29 |
2092 |
|
T1 |
9682 |
|
T12 |
56942 |
| auto[1] |
auto[1] |
auto[0] |
1856321 |
1 |
|
|
T29 |
3966 |
|
T1 |
16917 |
|
T12 |
88902 |
| auto[1] |
auto[1] |
auto[1] |
1312565 |
1 |
|
|
T29 |
2371 |
|
T1 |
10124 |
|
T12 |
55111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |