Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8562709 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
6369230 |
1 |
|
|
T26 |
14 |
|
T29 |
11854 |
|
T1 |
54630 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14121034 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
810905 |
1 |
|
|
T26 |
1 |
|
T29 |
1270 |
|
T1 |
6425 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8558897 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
| auto[1] |
6373042 |
1 |
|
|
T26 |
8 |
|
T29 |
12398 |
|
T1 |
54550 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2779865 |
1 |
|
|
T26 |
7 |
|
T29 |
5330 |
|
T1 |
23610 |
| auto[1] |
auto[0] |
auto[1] |
404955 |
1 |
|
|
T26 |
1 |
|
T29 |
599 |
|
T1 |
3152 |
| auto[1] |
auto[1] |
auto[0] |
2782272 |
1 |
|
|
T29 |
5798 |
|
T1 |
24515 |
|
T12 |
131174 |
| auto[1] |
auto[1] |
auto[1] |
405950 |
1 |
|
|
T29 |
671 |
|
T1 |
3273 |
|
T12 |
20276 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |