Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8556395 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6375544 |
1 |
|
|
T26 |
10 |
|
T29 |
13285 |
|
T1 |
55462 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14130267 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
801672 |
1 |
|
|
T29 |
1291 |
|
T1 |
6431 |
|
T12 |
37480 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8585469 |
1 |
|
|
T23 |
1271 |
|
T24 |
103 |
|
T25 |
349 |
auto[1] |
6346470 |
1 |
|
|
T26 |
10 |
|
T29 |
12146 |
|
T1 |
55433 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2755882 |
1 |
|
|
T26 |
10 |
|
T29 |
4749 |
|
T1 |
23295 |
auto[1] |
auto[0] |
auto[1] |
397372 |
1 |
|
|
T29 |
568 |
|
T1 |
2977 |
|
T12 |
18245 |
auto[1] |
auto[1] |
auto[0] |
2788916 |
1 |
|
|
T29 |
6106 |
|
T1 |
25707 |
|
T12 |
127014 |
auto[1] |
auto[1] |
auto[1] |
404300 |
1 |
|
|
T29 |
723 |
|
T1 |
3454 |
|
T12 |
19235 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |