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Group Instance : intr_event_lvllow_pin23
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin23

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin23
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin23
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin24
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin24

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin24
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin24
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin25
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin25

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin25
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin25
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin26
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin26

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin26
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin26
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin27
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin27

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin27
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin27
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin28
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin28

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin28
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin28
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin29
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin29

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin29
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin29
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin3
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin30
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin30

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin30
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin30
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin31
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin31

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin31
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin31
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin4
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin5
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin6
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin7
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0


Group Instance : intr_event_lvllow_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_event_lvllow_pin8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 0 4 100.00


Variables for Group Instance intr_event_lvllow_pin8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
intr_en 2 0 2 100.00 100 1 1 2
intr_state 2 0 2 100.00 100 1 1 2
type_ctrl_en 2 0 2 100.00 100 1 1 2


Crosses for Group Instance intr_event_lvllow_pin8
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_type_en_state 4 0 4 100.00 100 1 1 0

Go back
Group Instances:
intr_event_lvllow_pin23
intr_event_lvllow_pin24
intr_event_lvllow_pin25
intr_event_lvllow_pin26
intr_event_lvllow_pin27
intr_event_lvllow_pin28
intr_event_lvllow_pin29
intr_event_lvllow_pin3
intr_event_lvllow_pin30
intr_event_lvllow_pin31
intr_event_lvllow_pin4
intr_event_lvllow_pin5
intr_event_lvllow_pin6
intr_event_lvllow_pin7
intr_event_lvllow_pin8

Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8604968 1 T23 1271 T24 103 T25 349
auto[1] 6326971 1 T26 14 T29 11698 T1 52984


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11209040 1 T23 1271 T24 103 T25 349
auto[1] 3722899 1 T26 7 T29 8321 T1 33503


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8560571 1 T23 1271 T24 103 T25 349
auto[1] 6371368 1 T26 9 T29 12663 T1 54140


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1328866 1 T26 2 T29 2177 T1 10587
auto[1] auto[0] auto[1] 1873481 1 T26 7 T29 4536 T1 17492
auto[1] auto[1] auto[0] 1319603 1 T29 2165 T1 10050 T12 55628
auto[1] auto[1] auto[1] 1849418 1 T29 3785 T1 16011 T12 86727


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8562924 1 T23 1271 T24 103 T25 349
auto[1] 6369015 1 T29 12760 T1 55024 T12 297635


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11220447 1 T23 1271 T24 103 T25 349
auto[1] 3711492 1 T26 13 T29 7588 T1 33964


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8580247 1 T23 1271 T24 103 T25 349
auto[1] 6351692 1 T26 14 T29 12098 T1 54339


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1325518 1 T26 1 T29 2177 T1 10165
auto[1] auto[0] auto[1] 1855912 1 T26 13 T29 3858 T1 17028
auto[1] auto[1] auto[0] 1314682 1 T29 2333 T1 10210 T12 59402
auto[1] auto[1] auto[1] 1855580 1 T29 3730 T1 16936 T12 94960


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8587949 1 T23 1271 T24 103 T25 349
auto[1] 6343990 1 T29 11707 T1 54066 T12 291814


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11192643 1 T23 1271 T24 103 T25 349
auto[1] 3739296 1 T26 5 T29 7193 T1 34170


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8550133 1 T23 1271 T24 103 T25 349
auto[1] 6381806 1 T26 5 T29 11319 T1 54396


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1333463 1 T29 2207 T1 10564 T12 57448
auto[1] auto[0] auto[1] 1885961 1 T26 5 T29 3741 T1 18034
auto[1] auto[1] auto[0] 1309047 1 T29 1919 T1 9662 T12 53632
auto[1] auto[1] auto[1] 1853335 1 T29 3452 T1 16136 T12 87277


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8578424 1 T23 1271 T24 103 T25 349
auto[1] 6353515 1 T29 12438 T1 53084 T12 289659


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11203204 1 T23 1271 T24 103 T25 349
auto[1] 3728735 1 T26 4 T29 8102 T1 35014


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8558205 1 T23 1271 T24 103 T25 349
auto[1] 6373734 1 T26 5 T29 12331 T1 55815


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1323560 1 T26 1 T29 1927 T1 10492
auto[1] auto[0] auto[1] 1868676 1 T26 4 T29 3781 T1 17519
auto[1] auto[1] auto[0] 1321439 1 T29 2302 T1 10309 T12 57010
auto[1] auto[1] auto[1] 1860059 1 T29 4321 T1 17495 T12 90431


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8555790 1 T23 1271 T24 103 T25 349
auto[1] 6376149 1 T26 4 T29 12399 T1 55913


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11225990 1 T23 1271 T24 103 T25 349
auto[1] 3705949 1 T26 12 T29 8523 T1 33919


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8583654 1 T23 1271 T24 103 T25 349
auto[1] 6348285 1 T26 14 T29 13027 T1 54475


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1326350 1 T26 2 T29 2313 T1 10035
auto[1] auto[0] auto[1] 1854456 1 T26 12 T29 4397 T1 16249
auto[1] auto[1] auto[0] 1315986 1 T29 2191 T1 10521 T12 57368
auto[1] auto[1] auto[1] 1851493 1 T29 4126 T1 17670 T12 93716


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8571799 1 T23 1271 T24 103 T25 349
auto[1] 6360140 1 T26 14 T29 12012 T1 55887


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11215808 1 T23 1271 T24 103 T25 349
auto[1] 3716131 1 T29 7861 T1 34142 T12 177109


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8573698 1 T23 1271 T24 103 T25 349
auto[1] 6358241 1 T26 5 T29 12364 T1 54559


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1325358 1 T26 5 T29 2280 T1 10154
auto[1] auto[0] auto[1] 1873211 1 T29 4162 T1 16981 T12 84318
auto[1] auto[1] auto[0] 1316752 1 T29 2223 T1 10263 T12 57397
auto[1] auto[1] auto[1] 1842920 1 T29 3699 T1 17161 T12 92791


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8574427 1 T23 1271 T24 103 T25 349
auto[1] 6357512 1 T26 14 T29 11848 T1 53351


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11229803 1 T23 1271 T24 103 T25 349
auto[1] 3702136 1 T29 7795 T1 33279 T12 181204


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8600326 1 T23 1271 T24 103 T25 349
auto[1] 6331613 1 T26 5 T29 12175 T1 52985


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1313538 1 T26 5 T29 2439 T1 9923
auto[1] auto[0] auto[1] 1848410 1 T29 4184 T1 16771 T12 88909
auto[1] auto[1] auto[0] 1315939 1 T29 1941 T1 9783 T12 56938
auto[1] auto[1] auto[1] 1853726 1 T29 3611 T1 16508 T12 92295


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8562709 1 T23 1271 T24 103 T25 349
auto[1] 6369230 1 T26 14 T29 11854 T1 54630


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11202917 1 T23 1271 T24 103 T25 349
auto[1] 3729022 1 T26 1 T29 8799 T1 34103


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8556364 1 T23 1271 T24 103 T25 349
auto[1] 6375575 1 T26 5 T29 13439 T1 54726


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1328869 1 T26 4 T29 2314 T1 10179
auto[1] auto[0] auto[1] 1867308 1 T26 1 T29 4655 T1 17109
auto[1] auto[1] auto[0] 1317684 1 T29 2326 T1 10444 T12 59803
auto[1] auto[1] auto[1] 1861714 1 T29 4144 T1 16994 T12 95874


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8556395 1 T23 1271 T24 103 T25 349
auto[1] 6375544 1 T26 10 T29 13285 T1 55462


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11207107 1 T23 1271 T24 103 T25 349
auto[1] 3724832 1 T26 4 T29 7577 T1 32763


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8561915 1 T23 1271 T24 103 T25 349
auto[1] 6370024 1 T26 5 T29 11905 T1 51984


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1330425 1 T26 1 T29 2127 T1 9461
auto[1] auto[0] auto[1] 1871969 1 T26 4 T29 3667 T1 16145
auto[1] auto[1] auto[0] 1314767 1 T29 2201 T1 9760 T12 56038
auto[1] auto[1] auto[1] 1852863 1 T29 3910 T1 16618 T12 90125


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8570622 1 T23 1271 T24 103 T25 349
auto[1] 6361317 1 T26 14 T29 10922 T1 56559


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11236542 1 T23 1271 T24 103 T25 349
auto[1] 3695397 1 T26 1 T29 8415 T1 33973


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8610631 1 T23 1271 T24 103 T25 349
auto[1] 6321308 1 T26 5 T29 13020 T1 54148


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1307751 1 T26 4 T29 2554 T1 9645
auto[1] auto[0] auto[1] 1842001 1 T26 1 T29 4716 T1 16213
auto[1] auto[1] auto[0] 1318160 1 T29 2051 T1 10530 T12 57195
auto[1] auto[1] auto[1] 1853396 1 T29 3699 T1 17760 T12 93145


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8596637 1 T23 1271 T24 103 T25 349
auto[1] 6335302 1 T29 12996 T1 53399 T12 286241


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11208184 1 T23 1271 T24 103 T25 349
auto[1] 3723755 1 T26 3 T29 8569 T1 33172


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8560573 1 T23 1271 T24 103 T25 349
auto[1] 6371366 1 T26 14 T29 13014 T1 52633


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1330037 1 T26 11 T29 1890 T1 9445
auto[1] auto[0] auto[1] 1869247 1 T26 3 T29 3847 T1 15967
auto[1] auto[1] auto[0] 1317574 1 T29 2555 T1 10016 T12 54550
auto[1] auto[1] auto[1] 1854508 1 T29 4722 T1 17205 T12 85289


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8578353 1 T23 1271 T24 103 T25 349
auto[1] 6353586 1 T26 4 T29 12206 T1 53452


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11236687 1 T23 1271 T24 103 T25 349
auto[1] 3695252 1 T26 12 T29 7705 T1 34129


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8617624 1 T23 1271 T24 103 T25 349
auto[1] 6314315 1 T26 14 T29 11739 T1 54981


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1314601 1 T26 2 T29 2061 T1 10677
auto[1] auto[0] auto[1] 1854820 1 T26 12 T29 3774 T1 17411
auto[1] auto[1] auto[0] 1304462 1 T29 1973 T1 10175 T12 54973
auto[1] auto[1] auto[1] 1840432 1 T29 3931 T1 16718 T12 88417


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8540498 1 T23 1271 T24 103 T25 349
auto[1] 6391441 1 T26 14 T29 12886 T1 57080


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11225553 1 T23 1271 T24 103 T25 349
auto[1] 3706386 1 T26 6 T29 8332 T1 34842


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8589325 1 T23 1271 T24 103 T25 349
auto[1] 6342614 1 T26 14 T29 12854 T1 55532


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1313056 1 T26 8 T29 2117 T1 9722
auto[1] auto[0] auto[1] 1853259 1 T26 6 T29 3713 T1 16471
auto[1] auto[1] auto[0] 1323172 1 T29 2405 T1 10968 T12 55798
auto[1] auto[1] auto[1] 1853127 1 T29 4619 T1 18371 T12 88885


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8567626 1 T23 1271 T24 103 T25 349
auto[1] 6364313 1 T29 12239 T1 52692 T12 287133


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11205247 1 T23 1271 T24 103 T25 349
auto[1] 3726692 1 T26 13 T29 8523 T1 35085


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8553307 1 T23 1271 T24 103 T25 349
auto[1] 6378632 1 T26 19 T29 13098 T1 56508


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1322621 1 T26 6 T29 2143 T1 10837
auto[1] auto[0] auto[1] 1858602 1 T26 13 T29 4066 T1 17762
auto[1] auto[1] auto[0] 1329319 1 T29 2432 T1 10586 T12 56213
auto[1] auto[1] auto[1] 1868090 1 T29 4457 T1 17323 T12 87663


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded


Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8593406 1 T23 1271 T24 103 T25 349
auto[1] 6338533 1 T29 11869 T1 51715 T12 286156


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11207942 1 T23 1271 T24 103 T25 349
auto[1] 3723997 1 T26 2 T29 7980 T1 33824


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8561286 1 T23 1271 T24 103 T25 349
auto[1] 6370653 1 T26 5 T29 12517 T1 53782


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1329220 1 T26 3 T29 2289 T1 10070
auto[1] auto[0] auto[1] 1870162 1 T26 2 T29 3894 T1 17608
auto[1] auto[1] auto[0] 1317436 1 T29 2248 T1 9888 T12 56976
auto[1] auto[1] auto[1] 1853835 1 T29 4086 T1 16216 T12 89692


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%