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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 945
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T88 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3269637352 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:41 PM PDT 24 53490925 ps
T759 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3416569048 Jul 07 05:40:58 PM PDT 24 Jul 07 05:41:01 PM PDT 24 464390136 ps
T42 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.555689219 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:44 PM PDT 24 298022349 ps
T760 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2676039958 Jul 07 05:40:42 PM PDT 24 Jul 07 05:40:47 PM PDT 24 38583706 ps
T761 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.424874383 Jul 07 05:40:42 PM PDT 24 Jul 07 05:40:47 PM PDT 24 316330282 ps
T89 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2541955448 Jul 07 05:40:47 PM PDT 24 Jul 07 05:40:50 PM PDT 24 56621524 ps
T762 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4098534430 Jul 07 05:40:41 PM PDT 24 Jul 07 05:40:48 PM PDT 24 929464790 ps
T763 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3239039315 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 14519958 ps
T764 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3056358281 Jul 07 05:40:42 PM PDT 24 Jul 07 05:40:49 PM PDT 24 49433817 ps
T765 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.557680062 Jul 07 05:40:55 PM PDT 24 Jul 07 05:40:56 PM PDT 24 111194538 ps
T766 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2169828529 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:45 PM PDT 24 13040249 ps
T767 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1859232557 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:41 PM PDT 24 110834693 ps
T768 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.390027330 Jul 07 05:40:28 PM PDT 24 Jul 07 05:40:29 PM PDT 24 18257794 ps
T769 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2986638157 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:43 PM PDT 24 17800564 ps
T770 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3054972878 Jul 07 05:40:34 PM PDT 24 Jul 07 05:40:36 PM PDT 24 18115598 ps
T771 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4141147718 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:39 PM PDT 24 16604192 ps
T772 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4070495491 Jul 07 05:40:32 PM PDT 24 Jul 07 05:40:36 PM PDT 24 495400396 ps
T43 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.878159814 Jul 07 05:40:41 PM PDT 24 Jul 07 05:40:46 PM PDT 24 133237995 ps
T773 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3803812365 Jul 07 05:40:48 PM PDT 24 Jul 07 05:40:52 PM PDT 24 145477981 ps
T774 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1652642088 Jul 07 05:40:44 PM PDT 24 Jul 07 05:40:48 PM PDT 24 13251289 ps
T775 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1617236396 Jul 07 05:40:53 PM PDT 24 Jul 07 05:40:54 PM PDT 24 20232521 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2651349778 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:41 PM PDT 24 410135524 ps
T777 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3550230099 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:44 PM PDT 24 219022029 ps
T778 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2875518785 Jul 07 05:40:30 PM PDT 24 Jul 07 05:40:31 PM PDT 24 16153903 ps
T779 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1172691850 Jul 07 05:40:35 PM PDT 24 Jul 07 05:40:38 PM PDT 24 102643778 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2242029803 Jul 07 05:40:35 PM PDT 24 Jul 07 05:40:43 PM PDT 24 15207931 ps
T781 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.267296569 Jul 07 05:40:43 PM PDT 24 Jul 07 05:40:49 PM PDT 24 117319841 ps
T782 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1419012305 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:43 PM PDT 24 57382044 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3561539668 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:42 PM PDT 24 19906929 ps
T784 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1366668827 Jul 07 05:40:55 PM PDT 24 Jul 07 05:40:56 PM PDT 24 11831378 ps
T785 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1875010517 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:43 PM PDT 24 14402047 ps
T786 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1273222441 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:41 PM PDT 24 22362325 ps
T787 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2631499302 Jul 07 05:41:03 PM PDT 24 Jul 07 05:41:04 PM PDT 24 30762565 ps
T788 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3386343216 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:39 PM PDT 24 98607979 ps
T789 /workspace/coverage/cover_reg_top/8.gpio_intr_test.271557340 Jul 07 05:40:44 PM PDT 24 Jul 07 05:40:48 PM PDT 24 13629510 ps
T77 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.87898373 Jul 07 05:40:22 PM PDT 24 Jul 07 05:40:23 PM PDT 24 36662957 ps
T790 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2723638064 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:44 PM PDT 24 47478091 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1176552556 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:45 PM PDT 24 34783081 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.88072236 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:41 PM PDT 24 346137739 ps
T793 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3100151793 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 149337173 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.700488842 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:42 PM PDT 24 90314831 ps
T795 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1692214800 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:43 PM PDT 24 60490507 ps
T796 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2583704280 Jul 07 05:40:32 PM PDT 24 Jul 07 05:40:35 PM PDT 24 94931569 ps
T797 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2194856409 Jul 07 05:40:43 PM PDT 24 Jul 07 05:40:48 PM PDT 24 78148378 ps
T798 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2188031249 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:45 PM PDT 24 113027379 ps
T799 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2574451645 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:39 PM PDT 24 30081917 ps
T800 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4115920108 Jul 07 05:40:35 PM PDT 24 Jul 07 05:40:37 PM PDT 24 13776360 ps
T801 /workspace/coverage/cover_reg_top/38.gpio_intr_test.1763044191 Jul 07 05:40:41 PM PDT 24 Jul 07 05:40:45 PM PDT 24 14008926 ps
T802 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.305385569 Jul 07 05:40:44 PM PDT 24 Jul 07 05:40:49 PM PDT 24 15874162 ps
T78 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1664601323 Jul 07 05:40:41 PM PDT 24 Jul 07 05:40:46 PM PDT 24 29025359 ps
T803 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4189353145 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:40 PM PDT 24 138574946 ps
T804 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2555380841 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:36 PM PDT 24 436377503 ps
T805 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1828634286 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 132499632 ps
T806 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3080930001 Jul 07 05:40:54 PM PDT 24 Jul 07 05:40:55 PM PDT 24 35112384 ps
T807 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2696995014 Jul 07 05:40:43 PM PDT 24 Jul 07 05:40:47 PM PDT 24 94560284 ps
T808 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1765198269 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:44 PM PDT 24 93308519 ps
T809 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2868543660 Jul 07 05:40:46 PM PDT 24 Jul 07 05:40:50 PM PDT 24 25343844 ps
T810 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.808309093 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 287634838 ps
T811 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1395590299 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:39 PM PDT 24 52116351 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1478208899 Jul 07 05:40:26 PM PDT 24 Jul 07 05:40:28 PM PDT 24 117548182 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.143059009 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:35 PM PDT 24 21691848 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.797245267 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 19328810 ps
T815 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2518106064 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:44 PM PDT 24 63275778 ps
T816 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.850035466 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:40 PM PDT 24 36781819 ps
T817 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4055123418 Jul 07 05:40:34 PM PDT 24 Jul 07 05:40:37 PM PDT 24 71312502 ps
T818 /workspace/coverage/cover_reg_top/31.gpio_intr_test.694649857 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 21270844 ps
T819 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3951546488 Jul 07 05:40:35 PM PDT 24 Jul 07 05:40:37 PM PDT 24 24710585 ps
T79 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1500663560 Jul 07 05:40:32 PM PDT 24 Jul 07 05:40:46 PM PDT 24 13070974 ps
T820 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.454904764 Jul 07 05:40:32 PM PDT 24 Jul 07 05:40:36 PM PDT 24 926762842 ps
T821 /workspace/coverage/cover_reg_top/39.gpio_intr_test.314912747 Jul 07 05:40:43 PM PDT 24 Jul 07 05:40:48 PM PDT 24 16808451 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3104628244 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:35 PM PDT 24 68437062 ps
T823 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1799809575 Jul 07 05:40:35 PM PDT 24 Jul 07 05:40:38 PM PDT 24 41156865 ps
T824 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3176856584 Jul 07 05:40:37 PM PDT 24 Jul 07 05:40:40 PM PDT 24 69624076 ps
T825 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2746321561 Jul 07 05:40:47 PM PDT 24 Jul 07 05:40:49 PM PDT 24 23783094 ps
T826 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3946849091 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:44 PM PDT 24 544531176 ps
T827 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3549800346 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:35 PM PDT 24 254522033 ps
T828 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3344873938 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:39 PM PDT 24 49684910 ps
T829 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1357340325 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:35 PM PDT 24 23062137 ps
T830 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3213980278 Jul 07 05:40:41 PM PDT 24 Jul 07 05:40:46 PM PDT 24 45665652 ps
T831 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1049631477 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:42 PM PDT 24 15450014 ps
T832 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4009911909 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:42 PM PDT 24 70287803 ps
T833 /workspace/coverage/cover_reg_top/28.gpio_intr_test.328089418 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:45 PM PDT 24 16332952 ps
T834 /workspace/coverage/cover_reg_top/40.gpio_intr_test.871486390 Jul 07 05:40:36 PM PDT 24 Jul 07 05:40:39 PM PDT 24 34521400 ps
T835 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2247882319 Jul 07 05:40:47 PM PDT 24 Jul 07 05:40:49 PM PDT 24 47883409 ps
T836 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2892371116 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:42 PM PDT 24 37648745 ps
T80 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3006323004 Jul 07 05:40:43 PM PDT 24 Jul 07 05:40:47 PM PDT 24 19100741 ps
T837 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2698918043 Jul 07 05:40:44 PM PDT 24 Jul 07 05:40:48 PM PDT 24 45077984 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4019149334 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:36 PM PDT 24 18971534 ps
T839 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1069040310 Jul 07 05:40:38 PM PDT 24 Jul 07 05:40:41 PM PDT 24 20874467 ps
T840 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3658506888 Jul 07 05:40:34 PM PDT 24 Jul 07 05:40:37 PM PDT 24 105325029 ps
T841 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3845974152 Jul 07 05:40:42 PM PDT 24 Jul 07 05:40:47 PM PDT 24 127528687 ps
T842 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4128737611 Jul 07 05:40:39 PM PDT 24 Jul 07 05:40:43 PM PDT 24 35413208 ps
T843 /workspace/coverage/cover_reg_top/1.gpio_intr_test.913945136 Jul 07 05:40:34 PM PDT 24 Jul 07 05:40:36 PM PDT 24 14976003 ps
T844 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4292581604 Jul 07 05:40:33 PM PDT 24 Jul 07 05:40:35 PM PDT 24 31624823 ps
T845 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1586886649 Jul 07 05:40:40 PM PDT 24 Jul 07 05:40:45 PM PDT 24 21847296 ps
T846 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2692303145 Jul 07 05:47:34 PM PDT 24 Jul 07 05:47:35 PM PDT 24 118596636 ps
T847 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3964679749 Jul 07 05:47:37 PM PDT 24 Jul 07 05:47:38 PM PDT 24 510798613 ps
T848 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3126725789 Jul 07 05:47:29 PM PDT 24 Jul 07 05:47:30 PM PDT 24 84827409 ps
T849 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3206568950 Jul 07 05:47:34 PM PDT 24 Jul 07 05:47:36 PM PDT 24 54127062 ps
T850 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1513866776 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:30 PM PDT 24 202158633 ps
T851 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3007917008 Jul 07 05:47:24 PM PDT 24 Jul 07 05:47:26 PM PDT 24 29123634 ps
T852 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.907345993 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:35 PM PDT 24 144019964 ps
T853 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2929732682 Jul 07 05:47:25 PM PDT 24 Jul 07 05:47:26 PM PDT 24 72732677 ps
T854 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2118667481 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:36 PM PDT 24 58039544 ps
T855 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.341119514 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 875729908 ps
T856 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1994324162 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 45238283 ps
T857 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3567122381 Jul 07 05:47:22 PM PDT 24 Jul 07 05:47:24 PM PDT 24 247127446 ps
T858 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.179019070 Jul 07 05:47:37 PM PDT 24 Jul 07 05:47:39 PM PDT 24 258732039 ps
T859 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1289506909 Jul 07 05:47:30 PM PDT 24 Jul 07 05:47:31 PM PDT 24 47886969 ps
T860 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3249358481 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:37 PM PDT 24 115595266 ps
T861 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2481217023 Jul 07 05:47:27 PM PDT 24 Jul 07 05:47:28 PM PDT 24 393200577 ps
T862 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4220517120 Jul 07 05:47:37 PM PDT 24 Jul 07 05:47:38 PM PDT 24 46358970 ps
T863 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2066957221 Jul 07 05:47:29 PM PDT 24 Jul 07 05:47:30 PM PDT 24 31520092 ps
T864 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.707335794 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:36 PM PDT 24 42753599 ps
T865 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2792730933 Jul 07 05:47:24 PM PDT 24 Jul 07 05:47:25 PM PDT 24 44173607 ps
T866 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3277317393 Jul 07 05:47:34 PM PDT 24 Jul 07 05:47:35 PM PDT 24 54728553 ps
T867 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4075961502 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:35 PM PDT 24 38434064 ps
T868 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2426395591 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 210678693 ps
T869 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3042216970 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:22 PM PDT 24 83863299 ps
T870 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3124190613 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:37 PM PDT 24 67383624 ps
T871 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.919210962 Jul 07 05:47:32 PM PDT 24 Jul 07 05:47:33 PM PDT 24 66789812 ps
T872 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1487108640 Jul 07 05:47:24 PM PDT 24 Jul 07 05:47:25 PM PDT 24 319700600 ps
T873 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1835382597 Jul 07 05:47:27 PM PDT 24 Jul 07 05:47:28 PM PDT 24 80741182 ps
T874 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.496614209 Jul 07 05:47:39 PM PDT 24 Jul 07 05:47:40 PM PDT 24 44725371 ps
T875 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4152472286 Jul 07 05:47:31 PM PDT 24 Jul 07 05:47:33 PM PDT 24 140798039 ps
T876 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.660884195 Jul 07 05:47:37 PM PDT 24 Jul 07 05:47:38 PM PDT 24 60393079 ps
T877 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2969598484 Jul 07 05:47:19 PM PDT 24 Jul 07 05:47:21 PM PDT 24 79909126 ps
T878 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2643748860 Jul 07 05:47:25 PM PDT 24 Jul 07 05:47:26 PM PDT 24 78529844 ps
T879 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.805974192 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 236816403 ps
T880 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2189008638 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:34 PM PDT 24 82172853 ps
T881 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3258618213 Jul 07 05:47:24 PM PDT 24 Jul 07 05:47:26 PM PDT 24 627541743 ps
T882 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1469493173 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 38008740 ps
T883 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1555381523 Jul 07 05:47:22 PM PDT 24 Jul 07 05:47:23 PM PDT 24 40513977 ps
T884 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1180715754 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:37 PM PDT 24 81121587 ps
T885 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1468378884 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:30 PM PDT 24 291220193 ps
T886 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.36304135 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:37 PM PDT 24 111992802 ps
T887 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2873050285 Jul 07 05:47:22 PM PDT 24 Jul 07 05:47:24 PM PDT 24 39228250 ps
T888 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3431908070 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:23 PM PDT 24 52075899 ps
T889 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2057798655 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:34 PM PDT 24 207516911 ps
T890 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2969970717 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:30 PM PDT 24 88626637 ps
T891 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.825429002 Jul 07 05:47:38 PM PDT 24 Jul 07 05:47:39 PM PDT 24 153186938 ps
T892 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2818770722 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:29 PM PDT 24 415584216 ps
T893 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2761178918 Jul 07 05:47:29 PM PDT 24 Jul 07 05:47:31 PM PDT 24 51421901 ps
T894 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4035213019 Jul 07 05:47:25 PM PDT 24 Jul 07 05:47:26 PM PDT 24 55990073 ps
T895 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1028353898 Jul 07 05:47:19 PM PDT 24 Jul 07 05:47:20 PM PDT 24 82669329 ps
T896 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4276890421 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:23 PM PDT 24 69155954 ps
T897 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371838938 Jul 07 05:47:38 PM PDT 24 Jul 07 05:47:39 PM PDT 24 35109751 ps
T898 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2378750919 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:23 PM PDT 24 24356460 ps
T899 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4100032214 Jul 07 05:47:27 PM PDT 24 Jul 07 05:47:29 PM PDT 24 115128683 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3765066737 Jul 07 05:47:29 PM PDT 24 Jul 07 05:47:31 PM PDT 24 203374138 ps
T901 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937243717 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:22 PM PDT 24 421569152 ps
T902 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.252715734 Jul 07 05:47:41 PM PDT 24 Jul 07 05:47:43 PM PDT 24 91472914 ps
T903 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.900502424 Jul 07 05:47:32 PM PDT 24 Jul 07 05:47:34 PM PDT 24 101427844 ps
T904 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.390048682 Jul 07 05:47:18 PM PDT 24 Jul 07 05:47:20 PM PDT 24 99064684 ps
T905 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1934970318 Jul 07 05:47:34 PM PDT 24 Jul 07 05:47:36 PM PDT 24 81377503 ps
T906 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3054475972 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:23 PM PDT 24 35203776 ps
T907 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.161636787 Jul 07 05:47:23 PM PDT 24 Jul 07 05:47:24 PM PDT 24 59269015 ps
T908 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.434149387 Jul 07 05:47:17 PM PDT 24 Jul 07 05:47:18 PM PDT 24 35131816 ps
T909 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.668794421 Jul 07 05:47:20 PM PDT 24 Jul 07 05:47:22 PM PDT 24 38858089 ps
T910 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1972730000 Jul 07 05:47:22 PM PDT 24 Jul 07 05:47:23 PM PDT 24 233778952 ps
T911 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154491954 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:36 PM PDT 24 70032917 ps
T912 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.770983933 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:37 PM PDT 24 188148539 ps
T913 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644940283 Jul 07 05:47:32 PM PDT 24 Jul 07 05:47:33 PM PDT 24 373832792 ps
T914 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.664627612 Jul 07 05:47:32 PM PDT 24 Jul 07 05:47:33 PM PDT 24 30231456 ps
T915 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.936418953 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 92289799 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3457190224 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:23 PM PDT 24 281310778 ps
T917 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.521517909 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:35 PM PDT 24 682747905 ps
T918 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2119006689 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:29 PM PDT 24 178585251 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3483995655 Jul 07 05:47:26 PM PDT 24 Jul 07 05:47:27 PM PDT 24 161180486 ps
T920 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.871970317 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:34 PM PDT 24 37733374 ps
T921 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693652376 Jul 07 05:47:21 PM PDT 24 Jul 07 05:47:23 PM PDT 24 48517272 ps
T922 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3800380551 Jul 07 05:47:27 PM PDT 24 Jul 07 05:47:29 PM PDT 24 152635919 ps
T923 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1063939643 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:36 PM PDT 24 147560221 ps
T924 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1926830626 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:35 PM PDT 24 122922788 ps
T925 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1715767599 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:30 PM PDT 24 370543045 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.818943611 Jul 07 05:47:23 PM PDT 24 Jul 07 05:47:24 PM PDT 24 202426490 ps
T927 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.201156749 Jul 07 05:47:20 PM PDT 24 Jul 07 05:47:22 PM PDT 24 54651679 ps
T928 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2893587849 Jul 07 05:47:32 PM PDT 24 Jul 07 05:47:33 PM PDT 24 33908074 ps
T929 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1831157266 Jul 07 05:47:23 PM PDT 24 Jul 07 05:47:24 PM PDT 24 97706794 ps
T930 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1910776413 Jul 07 05:47:37 PM PDT 24 Jul 07 05:47:39 PM PDT 24 493416213 ps
T931 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1422341121 Jul 07 05:47:29 PM PDT 24 Jul 07 05:47:30 PM PDT 24 104859953 ps
T932 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2819824735 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 142698261 ps
T933 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2666064150 Jul 07 05:47:23 PM PDT 24 Jul 07 05:47:25 PM PDT 24 270225212 ps
T934 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1047190078 Jul 07 05:47:35 PM PDT 24 Jul 07 05:47:37 PM PDT 24 109911793 ps
T935 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3110553263 Jul 07 05:47:23 PM PDT 24 Jul 07 05:47:25 PM PDT 24 361040095 ps
T936 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1680908211 Jul 07 05:47:31 PM PDT 24 Jul 07 05:47:33 PM PDT 24 47562059 ps
T937 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.145304879 Jul 07 05:47:28 PM PDT 24 Jul 07 05:47:29 PM PDT 24 156147192 ps
T938 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2093491821 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:34 PM PDT 24 491753169 ps
T939 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3328940027 Jul 07 05:47:38 PM PDT 24 Jul 07 05:47:40 PM PDT 24 378778117 ps
T940 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1773646926 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:38 PM PDT 24 128647914 ps
T941 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.979877801 Jul 07 05:47:26 PM PDT 24 Jul 07 05:47:28 PM PDT 24 72698320 ps
T942 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1453822682 Jul 07 05:47:29 PM PDT 24 Jul 07 05:47:31 PM PDT 24 143861991 ps
T943 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1149533655 Jul 07 05:47:27 PM PDT 24 Jul 07 05:47:28 PM PDT 24 25380455 ps
T944 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.546306657 Jul 07 05:47:36 PM PDT 24 Jul 07 05:47:39 PM PDT 24 379319166 ps
T945 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1726615561 Jul 07 05:47:33 PM PDT 24 Jul 07 05:47:35 PM PDT 24 39288245 ps

Test location /workspace/coverage/default/9.gpio_stress_all.3877833303
Short name T1
Test name
Test status
Simulation time 75288966577 ps
CPU time 227.2 seconds
Started Jul 07 05:44:57 PM PDT 24
Finished Jul 07 05:48:44 PM PDT 24
Peak memory 198728 kb
Host smart-379a490d-7a3d-4187-b55c-0b1d499867c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877833303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3877833303
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.638932758
Short name T16
Test name
Test status
Simulation time 1018058821 ps
CPU time 3.24 seconds
Started Jul 07 05:45:58 PM PDT 24
Finished Jul 07 05:46:02 PM PDT 24
Peak memory 198672 kb
Host smart-f6599f04-e6e0-4301-9b87-e639c9e5ccd1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638932758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.638932758
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1492341123
Short name T12
Test name
Test status
Simulation time 59001587425 ps
CPU time 1521.54 seconds
Started Jul 07 05:44:47 PM PDT 24
Finished Jul 07 06:10:09 PM PDT 24
Peak memory 198856 kb
Host smart-e579ff5c-15a5-4c5a-821e-b3322aee07cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1492341123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1492341123
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2127681202
Short name T40
Test name
Test status
Simulation time 123343626 ps
CPU time 1.35 seconds
Started Jul 07 05:40:55 PM PDT 24
Finished Jul 07 05:40:57 PM PDT 24
Peak memory 198540 kb
Host smart-1615b72d-5993-44c6-b151-5ca0b4a28a65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127681202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2127681202
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3952756265
Short name T65
Test name
Test status
Simulation time 63218042 ps
CPU time 0.81 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 196684 kb
Host smart-61e41ea5-830a-4bc3-87ce-eeb08d4b68b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952756265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3952756265
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2895177027
Short name T151
Test name
Test status
Simulation time 125173439 ps
CPU time 0.61 seconds
Started Jul 07 05:46:02 PM PDT 24
Finished Jul 07 05:46:03 PM PDT 24
Peak memory 194876 kb
Host smart-dd618115-d2b7-4578-9663-9d167ad3323b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895177027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2895177027
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4041900554
Short name T46
Test name
Test status
Simulation time 83304232 ps
CPU time 0.94 seconds
Started Jul 07 05:44:11 PM PDT 24
Finished Jul 07 05:44:12 PM PDT 24
Peak memory 215392 kb
Host smart-4903d617-ab63-45c0-915d-a88ce2d9fc52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041900554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4041900554
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2930857204
Short name T86
Test name
Test status
Simulation time 19815285 ps
CPU time 0.67 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 195304 kb
Host smart-1befd81e-02ae-428e-8844-192f103a257e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930857204 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2930857204
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1172691850
Short name T779
Test name
Test status
Simulation time 102643778 ps
CPU time 1.46 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:38 PM PDT 24
Peak memory 198508 kb
Host smart-82f08fb9-639a-4309-9e30-52fc5b5bd312
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172691850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1172691850
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.555689219
Short name T42
Test name
Test status
Simulation time 298022349 ps
CPU time 1.37 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 198732 kb
Host smart-091132c5-5c13-4921-bb5b-e4de1ed18c63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555689219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.555689219
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3383034678
Short name T76
Test name
Test status
Simulation time 416630460 ps
CPU time 0.82 seconds
Started Jul 07 05:40:53 PM PDT 24
Finished Jul 07 05:40:54 PM PDT 24
Peak memory 196448 kb
Host smart-f56e4031-db67-454b-8f19-2f3249d86b4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383034678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3383034678
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2453796014
Short name T731
Test name
Test status
Simulation time 253442907 ps
CPU time 3.28 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 197904 kb
Host smart-3ef6b336-fdfe-4264-988a-f52e20243418
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453796014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2453796014
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1715056708
Short name T732
Test name
Test status
Simulation time 19066289 ps
CPU time 0.57 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 195152 kb
Host smart-656d47d6-0074-488f-ad75-bb41e28e54ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715056708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1715056708
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2947014374
Short name T726
Test name
Test status
Simulation time 34041596 ps
CPU time 0.7 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 192252 kb
Host smart-d3637648-3582-4e5e-9da3-c04c0db964ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947014374 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2947014374
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1741099822
Short name T747
Test name
Test status
Simulation time 31394040 ps
CPU time 0.6 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 195764 kb
Host smart-fe62d0ff-d1ef-44fa-ba3e-9ba2c2b58cf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741099822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1741099822
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.190804142
Short name T721
Test name
Test status
Simulation time 18330684 ps
CPU time 0.64 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 194248 kb
Host smart-8ae32b16-8b7a-4eee-be4f-5f89701eac6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190804142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.190804142
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.797245267
Short name T814
Test name
Test status
Simulation time 19328810 ps
CPU time 0.62 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 195252 kb
Host smart-50f032b2-adae-484a-8ae9-111cc82f9425
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797245267 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.797245267
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1584039148
Short name T740
Test name
Test status
Simulation time 137024388 ps
CPU time 1.44 seconds
Started Jul 07 05:40:56 PM PDT 24
Finished Jul 07 05:40:57 PM PDT 24
Peak memory 198572 kb
Host smart-4cee5772-8129-463e-8822-94ef8f451ba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584039148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1584039148
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1664601323
Short name T78
Test name
Test status
Simulation time 29025359 ps
CPU time 0.76 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 196100 kb
Host smart-2c52e906-3f71-4ca3-8893-403fc83e8552
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664601323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1664601323
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.454904764
Short name T820
Test name
Test status
Simulation time 926762842 ps
CPU time 3.36 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 197892 kb
Host smart-cd1a8074-64a8-4e75-91de-2d67e577ac70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454904764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.454904764
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1472891742
Short name T75
Test name
Test status
Simulation time 22654306 ps
CPU time 0.67 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:38 PM PDT 24
Peak memory 195500 kb
Host smart-f1ae4aba-e8cd-4409-9d80-1def44d280bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472891742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1472891742
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1176552556
Short name T791
Test name
Test status
Simulation time 34783081 ps
CPU time 0.68 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 197932 kb
Host smart-16b3b045-5354-40fb-8274-efd956b9836d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176552556 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1176552556
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3071907411
Short name T69
Test name
Test status
Simulation time 141109966 ps
CPU time 0.61 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 195112 kb
Host smart-df5afdeb-669a-4b35-b65b-349125ec08d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071907411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3071907411
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.913945136
Short name T843
Test name
Test status
Simulation time 14976003 ps
CPU time 0.64 seconds
Started Jul 07 05:40:34 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 194448 kb
Host smart-06984881-6015-4a6e-a4ac-223a3b09011b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913945136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.913945136
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1765198269
Short name T808
Test name
Test status
Simulation time 93308519 ps
CPU time 0.79 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 197636 kb
Host smart-579eae9c-9ded-4ea6-a007-7b6e11a08ff9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765198269 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1765198269
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.201289176
Short name T746
Test name
Test status
Simulation time 43867861 ps
CPU time 2.32 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 198760 kb
Host smart-f192b842-7d86-4ba2-b3fa-19aca04e1511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201289176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.201289176
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.424874383
Short name T761
Test name
Test status
Simulation time 316330282 ps
CPU time 1.11 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 198540 kb
Host smart-ea55bb6e-36dc-4ccd-acb0-0dd709ca9f48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424874383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.424874383
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.280368865
Short name T751
Test name
Test status
Simulation time 20392325 ps
CPU time 0.9 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 198632 kb
Host smart-991dd12d-54e2-4097-86a7-9b87f7bdfd1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280368865 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.280368865
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2723638064
Short name T790
Test name
Test status
Simulation time 47478091 ps
CPU time 0.57 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 195064 kb
Host smart-0d4db5c6-826b-4bfc-afbd-27a0f3efa82a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723638064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2723638064
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1652642088
Short name T774
Test name
Test status
Simulation time 13251289 ps
CPU time 0.58 seconds
Started Jul 07 05:40:44 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 194296 kb
Host smart-ac92ddb7-b432-4a1a-8684-f47814fb846e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652642088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1652642088
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1505076005
Short name T758
Test name
Test status
Simulation time 26813664 ps
CPU time 1.22 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 198396 kb
Host smart-4d82ec90-51ba-474b-ac7d-479490e8ab65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505076005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1505076005
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1630832675
Short name T33
Test name
Test status
Simulation time 1738354934 ps
CPU time 1.61 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 198756 kb
Host smart-ded4fea3-62bf-40ab-a04c-a0ea2bade6dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630832675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1630832675
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.850035466
Short name T816
Test name
Test status
Simulation time 36781819 ps
CPU time 1.72 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 198748 kb
Host smart-499db636-2163-4127-9852-ed9fd19bd985
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850035466 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.850035466
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2171923893
Short name T68
Test name
Test status
Simulation time 18050227 ps
CPU time 0.64 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 196144 kb
Host smart-2c0f55e1-8861-43bb-afd9-98c902585e14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171923893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2171923893
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2518106064
Short name T815
Test name
Test status
Simulation time 63275778 ps
CPU time 0.63 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 194492 kb
Host smart-2892174a-13fd-4626-b2b3-46fd07bd52a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518106064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2518106064
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1787384865
Short name T85
Test name
Test status
Simulation time 56984928 ps
CPU time 0.75 seconds
Started Jul 07 05:41:00 PM PDT 24
Finished Jul 07 05:41:01 PM PDT 24
Peak memory 197552 kb
Host smart-3dcc34ff-ac4c-404c-82bb-c9308085371a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787384865 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1787384865
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1799809575
Short name T823
Test name
Test status
Simulation time 41156865 ps
CPU time 1.15 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:38 PM PDT 24
Peak memory 198716 kb
Host smart-6e657e2e-579f-430e-b9bb-4f45957d515c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799809575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1799809575
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2583704280
Short name T796
Test name
Test status
Simulation time 94931569 ps
CPU time 1.22 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 198744 kb
Host smart-8298577c-66eb-44da-9924-50ecda8227b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583704280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2583704280
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1459696372
Short name T718
Test name
Test status
Simulation time 27135380 ps
CPU time 1.22 seconds
Started Jul 07 05:40:55 PM PDT 24
Finished Jul 07 05:40:56 PM PDT 24
Peak memory 198736 kb
Host smart-d4cc170a-7573-4262-8aa6-ede470f66cd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459696372 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1459696372
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2875518785
Short name T778
Test name
Test status
Simulation time 16153903 ps
CPU time 0.62 seconds
Started Jul 07 05:40:30 PM PDT 24
Finished Jul 07 05:40:31 PM PDT 24
Peak memory 195556 kb
Host smart-e57f1b9a-7253-48b5-98fd-455b1c7cd55d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875518785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2875518785
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1658831195
Short name T755
Test name
Test status
Simulation time 44555722 ps
CPU time 0.61 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 194388 kb
Host smart-8f9c84d1-c64b-4913-976a-b9424850638f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658831195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1658831195
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.4292581604
Short name T844
Test name
Test status
Simulation time 31624823 ps
CPU time 0.82 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 196880 kb
Host smart-212d489a-7ab1-4808-be75-7762b7b81625
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292581604 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.4292581604
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.267296569
Short name T781
Test name
Test status
Simulation time 117319841 ps
CPU time 2.46 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 198680 kb
Host smart-8f6dc811-aa59-46c8-90ab-2a4f289ea6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267296569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.267296569
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1478208899
Short name T812
Test name
Test status
Simulation time 117548182 ps
CPU time 1.38 seconds
Started Jul 07 05:40:26 PM PDT 24
Finished Jul 07 05:40:28 PM PDT 24
Peak memory 198680 kb
Host smart-2b8edf4b-3586-42be-81ac-7c625ed5d976
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478208899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1478208899
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1156674180
Short name T723
Test name
Test status
Simulation time 107388554 ps
CPU time 1.37 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 198792 kb
Host smart-d1f7e3d6-0f91-46a5-be61-b3cc2e375571
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156674180 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1156674180
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3951546488
Short name T819
Test name
Test status
Simulation time 24710585 ps
CPU time 0.61 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 195576 kb
Host smart-c19edefe-104d-4b06-9104-55353d15abe7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951546488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3951546488
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2854930716
Short name T725
Test name
Test status
Simulation time 13723593 ps
CPU time 0.61 seconds
Started Jul 07 05:40:31 PM PDT 24
Finished Jul 07 05:40:32 PM PDT 24
Peak memory 194332 kb
Host smart-8e962772-328e-40da-aa3c-3a43968a2e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854930716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2854930716
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3561539668
Short name T783
Test name
Test status
Simulation time 19906929 ps
CPU time 0.89 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 198100 kb
Host smart-70387aa2-d4d0-49c9-82f2-2c8b29494664
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561539668 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3561539668
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1395590299
Short name T811
Test name
Test status
Simulation time 52116351 ps
CPU time 1.26 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 198788 kb
Host smart-328cb6b8-444b-4cd7-b2a9-5db6b3188e58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395590299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1395590299
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2651349778
Short name T776
Test name
Test status
Simulation time 410135524 ps
CPU time 1.4 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 198652 kb
Host smart-f3e19f5e-0431-406c-8b20-14168d89785e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651349778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2651349778
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4109776988
Short name T724
Test name
Test status
Simulation time 36133482 ps
CPU time 0.97 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 198632 kb
Host smart-3341e6e4-dd65-4c8f-8376-f561954e1637
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109776988 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.4109776988
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3344873938
Short name T828
Test name
Test status
Simulation time 49684910 ps
CPU time 0.67 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 196052 kb
Host smart-58e3f89c-7210-48c4-b259-16a389348abc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344873938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3344873938
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3100151793
Short name T793
Test name
Test status
Simulation time 149337173 ps
CPU time 0.62 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 194396 kb
Host smart-fc600930-a877-468f-8e73-47aa3023e187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100151793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3100151793
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3631739451
Short name T83
Test name
Test status
Simulation time 18678449 ps
CPU time 0.64 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 195556 kb
Host smart-4d9c9104-a2f7-4806-a3ca-a7bc22bf4408
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631739451 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3631739451
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2555380841
Short name T804
Test name
Test status
Simulation time 436377503 ps
CPU time 1.71 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 198720 kb
Host smart-9e632fb5-972f-4101-a335-532e934dcd35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555380841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2555380841
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.437592792
Short name T716
Test name
Test status
Simulation time 78163886 ps
CPU time 1.1 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 198748 kb
Host smart-059768f6-855e-4139-b661-e2f9651431f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437592792 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.437592792
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4128737611
Short name T842
Test name
Test status
Simulation time 35413208 ps
CPU time 0.57 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 194672 kb
Host smart-80be744c-4f3a-426a-b802-461c7585fc82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128737611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4128737611
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2169828529
Short name T766
Test name
Test status
Simulation time 13040249 ps
CPU time 0.57 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 194292 kb
Host smart-36be7794-c798-4a6f-8466-05e7742bd62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169828529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2169828529
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2541955448
Short name T89
Test name
Test status
Simulation time 56621524 ps
CPU time 0.75 seconds
Started Jul 07 05:40:47 PM PDT 24
Finished Jul 07 05:40:50 PM PDT 24
Peak memory 197080 kb
Host smart-8d5aaa50-828e-4d07-a83c-42ca1349d196
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541955448 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2541955448
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.659952652
Short name T733
Test name
Test status
Simulation time 404674921 ps
CPU time 2.21 seconds
Started Jul 07 05:40:29 PM PDT 24
Finished Jul 07 05:40:32 PM PDT 24
Peak memory 198772 kb
Host smart-bc978c2c-d278-4668-876b-6a2537f6fadf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659952652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.659952652
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.4189353145
Short name T803
Test name
Test status
Simulation time 138574946 ps
CPU time 0.93 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 198464 kb
Host smart-ea847e54-895e-4e8c-ad69-11cf3e35c2b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189353145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.4189353145
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2676039958
Short name T760
Test name
Test status
Simulation time 38583706 ps
CPU time 1.67 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 198828 kb
Host smart-cfd3cf74-6789-4dac-a81f-243cbc655886
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676039958 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2676039958
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4270368826
Short name T73
Test name
Test status
Simulation time 52772934 ps
CPU time 0.64 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 195568 kb
Host smart-b840d31c-26da-4d5b-806a-fd37b89eb916
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270368826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4270368826
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2574451645
Short name T799
Test name
Test status
Simulation time 30081917 ps
CPU time 0.57 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 194360 kb
Host smart-a01b7fc1-45e7-4926-8fff-07a875949500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574451645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2574451645
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2696995014
Short name T807
Test name
Test status
Simulation time 94560284 ps
CPU time 0.74 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 196636 kb
Host smart-0327bfba-1f27-4cd3-a783-4dbb0b2d9c2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696995014 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2696995014
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.700488842
Short name T794
Test name
Test status
Simulation time 90314831 ps
CPU time 1.69 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 198732 kb
Host smart-2d067f41-d0ec-4581-8dd1-d2ef339f5d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700488842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.700488842
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3349732834
Short name T32
Test name
Test status
Simulation time 868926871 ps
CPU time 1.53 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 198728 kb
Host smart-4da88491-2d15-4e1f-ac5e-0a7f63ef6218
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349732834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3349732834
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1273222441
Short name T786
Test name
Test status
Simulation time 22362325 ps
CPU time 0.76 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 198572 kb
Host smart-968eba46-21c3-4312-8fb6-269d49ff2d03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273222441 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1273222441
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4115920108
Short name T800
Test name
Test status
Simulation time 13776360 ps
CPU time 0.62 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 195568 kb
Host smart-c9417346-3015-4a9a-ade7-fe8dc5617fd4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115920108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4115920108
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3270428469
Short name T717
Test name
Test status
Simulation time 14263672 ps
CPU time 0.63 seconds
Started Jul 07 05:40:44 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 194352 kb
Host smart-0cd58cdc-2c30-4317-b46b-540e17f44df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270428469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3270428469
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1631990709
Short name T74
Test name
Test status
Simulation time 19479823 ps
CPU time 0.71 seconds
Started Jul 07 05:40:31 PM PDT 24
Finished Jul 07 05:40:32 PM PDT 24
Peak memory 197004 kb
Host smart-0eeb1039-e974-4476-9c5a-dea97f76dca7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631990709 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1631990709
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3803812365
Short name T773
Test name
Test status
Simulation time 145477981 ps
CPU time 2.68 seconds
Started Jul 07 05:40:48 PM PDT 24
Finished Jul 07 05:40:52 PM PDT 24
Peak memory 198784 kb
Host smart-f34a4fdc-ed08-43ed-ae94-d3f5dde3b189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803812365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3803812365
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1936181347
Short name T91
Test name
Test status
Simulation time 257315095 ps
CPU time 1.15 seconds
Started Jul 07 05:40:29 PM PDT 24
Finished Jul 07 05:40:31 PM PDT 24
Peak memory 198776 kb
Host smart-60d2fe56-b307-479d-b094-0f795d133566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936181347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1936181347
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.378087203
Short name T728
Test name
Test status
Simulation time 117343541 ps
CPU time 0.82 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:33 PM PDT 24
Peak memory 198620 kb
Host smart-04edfb32-aa5e-40e1-bb28-512d1a0b3927
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378087203 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.378087203
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3248559488
Short name T745
Test name
Test status
Simulation time 12262656 ps
CPU time 0.63 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 196060 kb
Host smart-c8317c03-2b18-44de-919b-6180c76275de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248559488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3248559488
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1049631477
Short name T831
Test name
Test status
Simulation time 15450014 ps
CPU time 0.62 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 194344 kb
Host smart-1d881afd-e14d-464d-b2d6-1709e1e8a16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049631477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1049631477
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2631499302
Short name T787
Test name
Test status
Simulation time 30762565 ps
CPU time 0.64 seconds
Started Jul 07 05:41:03 PM PDT 24
Finished Jul 07 05:41:04 PM PDT 24
Peak memory 195136 kb
Host smart-d8e8d471-cc2e-4569-bfa4-ddae3a2c3739
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631499302 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2631499302
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2194856409
Short name T797
Test name
Test status
Simulation time 78148378 ps
CPU time 1.13 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 198784 kb
Host smart-5238a1ee-239e-4043-a8e7-d39803a73d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194856409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2194856409
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.878159814
Short name T43
Test name
Test status
Simulation time 133237995 ps
CPU time 1.16 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 198752 kb
Host smart-0a23b085-b3c2-4ec6-b0d9-9048c1345d4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878159814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.878159814
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3845974152
Short name T841
Test name
Test status
Simulation time 127528687 ps
CPU time 1 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 198624 kb
Host smart-7d0ccb92-f210-492e-9708-a76c5bc23f0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845974152 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3845974152
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.305385569
Short name T802
Test name
Test status
Simulation time 15874162 ps
CPU time 0.63 seconds
Started Jul 07 05:40:44 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 196200 kb
Host smart-e589ea21-a0df-41ff-8f05-806e77a8513e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305385569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.305385569
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1692214800
Short name T795
Test name
Test status
Simulation time 60490507 ps
CPU time 0.58 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 194364 kb
Host smart-60a436be-c94e-47a7-af76-acb27b225423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692214800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1692214800
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3269637352
Short name T88
Test name
Test status
Simulation time 53490925 ps
CPU time 0.74 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 197540 kb
Host smart-7e48af64-1bb6-4c78-88f4-4096c2463559
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269637352 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3269637352
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3550230099
Short name T777
Test name
Test status
Simulation time 219022029 ps
CPU time 2.22 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 198720 kb
Host smart-ee109017-a685-4761-b42d-55349d9ed385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550230099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3550230099
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2676247860
Short name T34
Test name
Test status
Simulation time 78565113 ps
CPU time 1.18 seconds
Started Jul 07 05:40:45 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 198752 kb
Host smart-1415ec25-1b58-48f9-98ed-c0b104d4305c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676247860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2676247860
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.88072236
Short name T792
Test name
Test status
Simulation time 346137739 ps
CPU time 1.5 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 198756 kb
Host smart-ceb72011-4483-44a0-b836-323bfc466ebc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88072236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.88072236
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1393842051
Short name T70
Test name
Test status
Simulation time 22163194 ps
CPU time 0.65 seconds
Started Jul 07 05:40:46 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 195492 kb
Host smart-0692ecb8-b6db-4b17-92b0-22f5a30ae707
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393842051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1393842051
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3386343216
Short name T788
Test name
Test status
Simulation time 98607979 ps
CPU time 0.97 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 198636 kb
Host smart-623c7823-dd24-4cad-af92-cd269407cf58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386343216 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3386343216
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3006323004
Short name T80
Test name
Test status
Simulation time 19100741 ps
CPU time 0.6 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 194632 kb
Host smart-b1908c30-4fbe-412a-8f09-7e489ebc6939
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006323004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3006323004
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3213980278
Short name T830
Test name
Test status
Simulation time 45665652 ps
CPU time 0.57 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 194800 kb
Host smart-878fe393-8d02-47f5-a745-2adbd8073fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213980278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3213980278
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.390027330
Short name T768
Test name
Test status
Simulation time 18257794 ps
CPU time 0.76 seconds
Started Jul 07 05:40:28 PM PDT 24
Finished Jul 07 05:40:29 PM PDT 24
Peak memory 196428 kb
Host smart-579f2bc5-81a5-4759-a329-f64549b7b850
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390027330 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.390027330
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3056358281
Short name T764
Test name
Test status
Simulation time 49433817 ps
CPU time 2.31 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 198576 kb
Host smart-4af7ef6f-44e9-4b6b-8b2b-a53ea721b5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056358281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3056358281
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2698918043
Short name T837
Test name
Test status
Simulation time 45077984 ps
CPU time 0.58 seconds
Started Jul 07 05:40:44 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 194316 kb
Host smart-27421a6e-8a51-4f7f-8c8a-1e94455dd2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698918043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2698918043
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4255457663
Short name T748
Test name
Test status
Simulation time 16606134 ps
CPU time 0.61 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 194436 kb
Host smart-2da0effe-f8e8-4901-be81-8a3e3022fe3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255457663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4255457663
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2188031249
Short name T798
Test name
Test status
Simulation time 113027379 ps
CPU time 0.6 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 194416 kb
Host smart-bc253935-e888-4ed3-a705-2e1442cd3599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188031249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2188031249
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3452605203
Short name T736
Test name
Test status
Simulation time 12792788 ps
CPU time 0.57 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 194372 kb
Host smart-69fdbcd8-2875-404a-951d-6e3cd61bca7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452605203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3452605203
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1934578077
Short name T729
Test name
Test status
Simulation time 13017369 ps
CPU time 0.63 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 194400 kb
Host smart-a257607d-0f7b-4944-a773-9edf1ef1c84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934578077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1934578077
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2746321561
Short name T825
Test name
Test status
Simulation time 23783094 ps
CPU time 0.6 seconds
Started Jul 07 05:40:47 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 195040 kb
Host smart-8fa17c08-c0db-4c68-a133-87f89da5b485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746321561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2746321561
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4192060204
Short name T750
Test name
Test status
Simulation time 50653799 ps
CPU time 0.56 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 194300 kb
Host smart-f76288bd-7c00-4548-ad71-eae71e0fd1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192060204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4192060204
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.75886416
Short name T735
Test name
Test status
Simulation time 16917554 ps
CPU time 0.62 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 194632 kb
Host smart-79c97c96-0c9c-426a-a4c3-73baeb1120ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75886416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.75886416
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.328089418
Short name T833
Test name
Test status
Simulation time 16332952 ps
CPU time 0.57 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 194988 kb
Host smart-608c6215-926c-4af7-821d-2268587f4664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328089418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.328089418
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2892371116
Short name T836
Test name
Test status
Simulation time 37648745 ps
CPU time 0.63 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 194368 kb
Host smart-334c63c6-839f-494a-85cd-4079581801c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892371116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2892371116
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.87898373
Short name T77
Test name
Test status
Simulation time 36662957 ps
CPU time 0.89 seconds
Started Jul 07 05:40:22 PM PDT 24
Finished Jul 07 05:40:23 PM PDT 24
Peak memory 197504 kb
Host smart-8beadcce-ba28-4956-bb55-2e5305676a77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87898373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
gpio_csr_aliasing.87898373
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4098534430
Short name T762
Test name
Test status
Simulation time 929464790 ps
CPU time 2.45 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 197468 kb
Host smart-07ac47de-c65b-489b-ba58-c4c8dc291904
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098534430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4098534430
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3669286830
Short name T753
Test name
Test status
Simulation time 27680773 ps
CPU time 0.65 seconds
Started Jul 07 05:41:00 PM PDT 24
Finished Jul 07 05:41:00 PM PDT 24
Peak memory 195540 kb
Host smart-cf2ff4b0-a326-47e5-8491-606d603bdc94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669286830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3669286830
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1586886649
Short name T845
Test name
Test status
Simulation time 21847296 ps
CPU time 1.05 seconds
Started Jul 07 05:40:40 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 198368 kb
Host smart-6101a295-cc63-4a5c-bcd9-d58eca096979
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586886649 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1586886649
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1500663560
Short name T79
Test name
Test status
Simulation time 13070974 ps
CPU time 0.61 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 194364 kb
Host smart-7d5812e0-e613-4d08-9d2a-0f707384e3e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500663560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1500663560
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3080930001
Short name T806
Test name
Test status
Simulation time 35112384 ps
CPU time 0.59 seconds
Started Jul 07 05:40:54 PM PDT 24
Finished Jul 07 05:40:55 PM PDT 24
Peak memory 194976 kb
Host smart-409f3f36-7d1e-4206-9345-0adefb0b3e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080930001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3080930001
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2666156879
Short name T84
Test name
Test status
Simulation time 31608663 ps
CPU time 0.73 seconds
Started Jul 07 05:40:49 PM PDT 24
Finished Jul 07 05:40:50 PM PDT 24
Peak memory 196644 kb
Host smart-013b040c-5444-488a-b497-4a38f31a7fb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666156879 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2666156879
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3416569048
Short name T759
Test name
Test status
Simulation time 464390136 ps
CPU time 2.51 seconds
Started Jul 07 05:40:58 PM PDT 24
Finished Jul 07 05:41:01 PM PDT 24
Peak memory 198688 kb
Host smart-5d06cc60-13f2-43df-9156-17458ef8a68b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416569048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3416569048
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3104628244
Short name T822
Test name
Test status
Simulation time 68437062 ps
CPU time 0.83 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 198280 kb
Host smart-8069c88b-949e-482d-a92b-e85eb3f14136
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104628244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3104628244
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3239039315
Short name T763
Test name
Test status
Simulation time 14519958 ps
CPU time 0.59 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 194368 kb
Host smart-b7d8dae6-250b-4e00-93b3-98cfa2607710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239039315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3239039315
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.694649857
Short name T818
Test name
Test status
Simulation time 21270844 ps
CPU time 0.58 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 194412 kb
Host smart-2d6603aa-3412-4736-874f-b17cfbed2f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694649857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.694649857
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3615804664
Short name T730
Test name
Test status
Simulation time 34245521 ps
CPU time 0.58 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 194320 kb
Host smart-23e79fb6-39cc-4d31-bebf-5bdb06d8a260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615804664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3615804664
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1419012305
Short name T782
Test name
Test status
Simulation time 57382044 ps
CPU time 0.59 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 194440 kb
Host smart-c1a76b11-133b-4508-bb1f-c1869db83682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419012305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1419012305
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1875010517
Short name T785
Test name
Test status
Simulation time 14402047 ps
CPU time 0.58 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 194384 kb
Host smart-727599c3-5e1e-498a-8cb0-87b4e1150bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875010517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1875010517
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2285847818
Short name T754
Test name
Test status
Simulation time 18692803 ps
CPU time 0.55 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 194344 kb
Host smart-7c9afef0-9f28-4f80-abde-03d36215d985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285847818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2285847818
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2247882319
Short name T835
Test name
Test status
Simulation time 47883409 ps
CPU time 0.56 seconds
Started Jul 07 05:40:47 PM PDT 24
Finished Jul 07 05:40:49 PM PDT 24
Peak memory 194332 kb
Host smart-85efb494-316f-4837-83b3-01d0b55058f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247882319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2247882319
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2158374769
Short name T756
Test name
Test status
Simulation time 16408671 ps
CPU time 0.58 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 194360 kb
Host smart-d7d5f529-f690-4396-af22-7ac4ee37f28b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158374769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2158374769
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1763044191
Short name T801
Test name
Test status
Simulation time 14008926 ps
CPU time 0.61 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 194340 kb
Host smart-f72645a3-2492-4e5c-be88-bc18d718921b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763044191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1763044191
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.314912747
Short name T821
Test name
Test status
Simulation time 16808451 ps
CPU time 0.58 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 194320 kb
Host smart-d20fc706-f05f-49a9-9b7b-0836010dc215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314912747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.314912747
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2485243628
Short name T757
Test name
Test status
Simulation time 68523225 ps
CPU time 0.86 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 196212 kb
Host smart-495628a9-ef16-4438-bf4b-2fe5eb3cacc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485243628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2485243628
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1560273689
Short name T72
Test name
Test status
Simulation time 292412370 ps
CPU time 2.95 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 197804 kb
Host smart-bb737810-f03d-4956-82f6-08697fce13c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560273689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1560273689
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2835093477
Short name T67
Test name
Test status
Simulation time 20674455 ps
CPU time 0.65 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 196076 kb
Host smart-0b20ba50-f5db-4be7-9bcb-a10be8f4550e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835093477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2835093477
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.143059009
Short name T813
Test name
Test status
Simulation time 21691848 ps
CPU time 0.75 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 198360 kb
Host smart-bfa45ac1-8bf9-4f09-a718-27dc5f42ef99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143059009 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.143059009
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4141147718
Short name T771
Test name
Test status
Simulation time 16604192 ps
CPU time 0.67 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 195564 kb
Host smart-99c16a37-494d-4592-bdac-77693943a804
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141147718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4141147718
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3549800346
Short name T827
Test name
Test status
Simulation time 254522033 ps
CPU time 0.6 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 194264 kb
Host smart-fcd77037-c380-472b-8b9f-6125620193d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549800346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3549800346
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2242029803
Short name T780
Test name
Test status
Simulation time 15207931 ps
CPU time 0.73 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 196920 kb
Host smart-c7526028-d6dc-46c1-b10b-5dfc0d0af3b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242029803 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2242029803
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3777845185
Short name T741
Test name
Test status
Simulation time 594820341 ps
CPU time 2.59 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 198720 kb
Host smart-7721ab8b-92fc-4731-8a2d-7d9fffc732d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777845185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3777845185
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3658506888
Short name T840
Test name
Test status
Simulation time 105325029 ps
CPU time 1.42 seconds
Started Jul 07 05:40:34 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 198772 kb
Host smart-2fe43b3f-808c-467c-bf7d-f7ddbe19f540
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658506888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3658506888
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.871486390
Short name T834
Test name
Test status
Simulation time 34521400 ps
CPU time 0.56 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:39 PM PDT 24
Peak memory 194340 kb
Host smart-078b6049-11ef-47c8-a1dc-443523f7550e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871486390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.871486390
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2880151219
Short name T738
Test name
Test status
Simulation time 16705606 ps
CPU time 0.59 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 194296 kb
Host smart-c17126e6-b424-4496-8176-421db4f504e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880151219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2880151219
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2033677172
Short name T744
Test name
Test status
Simulation time 16549053 ps
CPU time 0.63 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 194988 kb
Host smart-e4a6781e-b9e3-4cc3-b93e-25b3a2a0dfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033677172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2033677172
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2930950119
Short name T743
Test name
Test status
Simulation time 36775204 ps
CPU time 0.61 seconds
Started Jul 07 05:40:51 PM PDT 24
Finished Jul 07 05:40:52 PM PDT 24
Peak memory 194420 kb
Host smart-a7df1fad-c4b3-4663-901e-561f221b6484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930950119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2930950119
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2888138452
Short name T737
Test name
Test status
Simulation time 45079559 ps
CPU time 0.55 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 194200 kb
Host smart-9cc2aa05-243c-4610-9033-ca77d65d8a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888138452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2888138452
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3546197636
Short name T722
Test name
Test status
Simulation time 21835968 ps
CPU time 0.58 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 194320 kb
Host smart-0b6ebc52-a66d-412d-be30-9db5380dcbec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546197636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3546197636
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1596422159
Short name T720
Test name
Test status
Simulation time 13250464 ps
CPU time 0.58 seconds
Started Jul 07 05:40:51 PM PDT 24
Finished Jul 07 05:40:52 PM PDT 24
Peak memory 194404 kb
Host smart-cdad4c37-d3b2-4ed5-9461-e8beb60cc02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596422159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1596422159
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2986638157
Short name T769
Test name
Test status
Simulation time 17800564 ps
CPU time 0.62 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:43 PM PDT 24
Peak memory 195104 kb
Host smart-f2f33ee7-0743-4c33-ba69-c79a9d95eb2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986638157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2986638157
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1617236396
Short name T775
Test name
Test status
Simulation time 20232521 ps
CPU time 0.58 seconds
Started Jul 07 05:40:53 PM PDT 24
Finished Jul 07 05:40:54 PM PDT 24
Peak memory 194996 kb
Host smart-128c78f2-1e36-432c-b09b-6908a61300f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617236396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1617236396
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2964580201
Short name T719
Test name
Test status
Simulation time 14270541 ps
CPU time 0.61 seconds
Started Jul 07 05:40:43 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 194456 kb
Host smart-5ab3ec0c-5de2-4d5c-a068-13ec7612f506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964580201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2964580201
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2227829492
Short name T715
Test name
Test status
Simulation time 41384586 ps
CPU time 1.24 seconds
Started Jul 07 05:40:41 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 198800 kb
Host smart-78c606e6-d229-4963-94aa-a30b7a842259
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227829492 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2227829492
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4111186510
Short name T71
Test name
Test status
Simulation time 13120148 ps
CPU time 0.56 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:46 PM PDT 24
Peak memory 193812 kb
Host smart-8c2c25f4-b94d-4cf1-9560-9e906b9da6d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111186510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4111186510
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1069040310
Short name T839
Test name
Test status
Simulation time 20874467 ps
CPU time 0.6 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 195080 kb
Host smart-6ef30f7b-65f3-499d-8f0c-f74199332e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069040310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1069040310
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1828634286
Short name T805
Test name
Test status
Simulation time 132499632 ps
CPU time 0.91 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 197136 kb
Host smart-a66faf5e-667a-4d39-ade6-030109e050af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828634286 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1828634286
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1859232557
Short name T767
Test name
Test status
Simulation time 110834693 ps
CPU time 2.41 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:41 PM PDT 24
Peak memory 198756 kb
Host smart-c4299b14-4dde-4f0f-84c7-693f5ecda41e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859232557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1859232557
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3946849091
Short name T826
Test name
Test status
Simulation time 544531176 ps
CPU time 1.09 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:44 PM PDT 24
Peak memory 198772 kb
Host smart-4d19f89e-f472-48a6-a0a2-a3b054f75777
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946849091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3946849091
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4019149334
Short name T838
Test name
Test status
Simulation time 18971534 ps
CPU time 0.82 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 198648 kb
Host smart-44e7c032-bb81-4a94-b955-e5174004c219
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019149334 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4019149334
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3802084290
Short name T749
Test name
Test status
Simulation time 28951791 ps
CPU time 0.56 seconds
Started Jul 07 05:40:31 PM PDT 24
Finished Jul 07 05:40:32 PM PDT 24
Peak memory 193984 kb
Host smart-ab49c808-4cab-4a86-bf35-164a1b637a92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802084290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3802084290
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3054972878
Short name T770
Test name
Test status
Simulation time 18115598 ps
CPU time 0.57 seconds
Started Jul 07 05:40:34 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 194348 kb
Host smart-45f6cb83-4c50-4b24-acd3-46038da0dfdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054972878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3054972878
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3176856584
Short name T824
Test name
Test status
Simulation time 69624076 ps
CPU time 0.73 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 196756 kb
Host smart-b62dec9d-1377-43f5-889c-568d4eeec4d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176856584 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3176856584
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4070495491
Short name T772
Test name
Test status
Simulation time 495400396 ps
CPU time 3.17 seconds
Started Jul 07 05:40:32 PM PDT 24
Finished Jul 07 05:40:36 PM PDT 24
Peak memory 198744 kb
Host smart-b3ab2d75-63f0-4fa1-8dac-476c87a8c285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070495491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4070495491
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2413412344
Short name T41
Test name
Test status
Simulation time 86363001 ps
CPU time 1.13 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:47 PM PDT 24
Peak memory 198728 kb
Host smart-f87a2fe8-7ea9-4ae4-a1e0-43b6ba3d5ddf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413412344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2413412344
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.4009911909
Short name T832
Test name
Test status
Simulation time 70287803 ps
CPU time 0.78 seconds
Started Jul 07 05:40:38 PM PDT 24
Finished Jul 07 05:40:42 PM PDT 24
Peak memory 198564 kb
Host smart-8e342040-e524-47a3-bc81-543355c9d5e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009911909 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.4009911909
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1366668827
Short name T784
Test name
Test status
Simulation time 11831378 ps
CPU time 0.56 seconds
Started Jul 07 05:40:55 PM PDT 24
Finished Jul 07 05:40:56 PM PDT 24
Peak memory 195236 kb
Host smart-0f10e3e5-c265-4d6b-957c-7c56571e0574
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366668827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1366668827
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3895744587
Short name T727
Test name
Test status
Simulation time 48260462 ps
CPU time 0.56 seconds
Started Jul 07 05:41:09 PM PDT 24
Finished Jul 07 05:41:10 PM PDT 24
Peak memory 194300 kb
Host smart-bbd5cee8-18e7-41eb-9a70-abc1e6ba57cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895744587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3895744587
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.473128031
Short name T82
Test name
Test status
Simulation time 39227742 ps
CPU time 0.65 seconds
Started Jul 07 05:40:48 PM PDT 24
Finished Jul 07 05:40:50 PM PDT 24
Peak memory 196136 kb
Host smart-20dbfe80-6f66-4c33-b88e-1ef773ca1945
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473128031 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.473128031
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3979636872
Short name T734
Test name
Test status
Simulation time 46450206 ps
CPU time 2.33 seconds
Started Jul 07 05:41:04 PM PDT 24
Finished Jul 07 05:41:07 PM PDT 24
Peak memory 198720 kb
Host smart-45e1b118-c13e-4ee3-af65-a5dd8cc5c0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979636872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3979636872
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.808309093
Short name T810
Test name
Test status
Simulation time 287634838 ps
CPU time 1.16 seconds
Started Jul 07 05:40:37 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 198760 kb
Host smart-b53a474c-fb61-4e8c-83a0-c3e11e8142c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808309093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.808309093
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2868543660
Short name T809
Test name
Test status
Simulation time 25343844 ps
CPU time 1.12 seconds
Started Jul 07 05:40:46 PM PDT 24
Finished Jul 07 05:40:50 PM PDT 24
Peak memory 198556 kb
Host smart-86299900-9079-4f2c-baa2-0d7844c818d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868543660 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2868543660
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1357340325
Short name T829
Test name
Test status
Simulation time 23062137 ps
CPU time 0.6 seconds
Started Jul 07 05:40:33 PM PDT 24
Finished Jul 07 05:40:35 PM PDT 24
Peak memory 193972 kb
Host smart-5126eab2-e7bd-40dd-982f-bb6c4ae47702
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357340325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1357340325
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.271557340
Short name T789
Test name
Test status
Simulation time 13629510 ps
CPU time 0.57 seconds
Started Jul 07 05:40:44 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 194308 kb
Host smart-4b119ff3-c9e3-4e5f-87ac-9d9eea0bd321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271557340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.271557340
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3168464566
Short name T87
Test name
Test status
Simulation time 22025069 ps
CPU time 0.71 seconds
Started Jul 07 05:40:30 PM PDT 24
Finished Jul 07 05:40:31 PM PDT 24
Peak memory 196268 kb
Host smart-f60556af-0d42-4707-8e7e-13e96360cf9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168464566 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3168464566
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4037785268
Short name T752
Test name
Test status
Simulation time 53007609 ps
CPU time 2.68 seconds
Started Jul 07 05:40:39 PM PDT 24
Finished Jul 07 05:40:45 PM PDT 24
Peak memory 198788 kb
Host smart-0317dae8-e1fc-4db6-990b-9c52065c3841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037785268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4037785268
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.4011823093
Short name T742
Test name
Test status
Simulation time 268379270 ps
CPU time 1.15 seconds
Started Jul 07 05:40:36 PM PDT 24
Finished Jul 07 05:40:40 PM PDT 24
Peak memory 198752 kb
Host smart-03f2ad6d-70f2-4704-9493-bb6bf75c3971
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011823093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.4011823093
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.557680062
Short name T765
Test name
Test status
Simulation time 111194538 ps
CPU time 0.77 seconds
Started Jul 07 05:40:55 PM PDT 24
Finished Jul 07 05:40:56 PM PDT 24
Peak memory 198484 kb
Host smart-0ca243b7-8794-4443-8f05-159853701125
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557680062 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.557680062
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1450481385
Short name T66
Test name
Test status
Simulation time 14458779 ps
CPU time 0.66 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:38 PM PDT 24
Peak memory 195640 kb
Host smart-06588b98-4fd2-4dc3-9cbf-8e9533398e8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450481385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1450481385
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3409695984
Short name T739
Test name
Test status
Simulation time 14547268 ps
CPU time 0.59 seconds
Started Jul 07 05:40:35 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 194420 kb
Host smart-ea9464eb-feef-4b7e-b887-f4e618e547de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409695984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3409695984
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.5919557
Short name T81
Test name
Test status
Simulation time 15864746 ps
CPU time 0.64 seconds
Started Jul 07 05:40:44 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 195464 kb
Host smart-de68341c-0e03-4fa2-b286-ee6d86ea9941
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5919557 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.gpio_same_csr_outstanding.5919557
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4055123418
Short name T817
Test name
Test status
Simulation time 71312502 ps
CPU time 1.63 seconds
Started Jul 07 05:40:34 PM PDT 24
Finished Jul 07 05:40:37 PM PDT 24
Peak memory 198748 kb
Host smart-52cc214a-c404-4543-b681-a62e48ac26d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055123418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4055123418
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1760323219
Short name T92
Test name
Test status
Simulation time 109514802 ps
CPU time 1.37 seconds
Started Jul 07 05:40:42 PM PDT 24
Finished Jul 07 05:40:48 PM PDT 24
Peak memory 198552 kb
Host smart-5c0a2a2a-b496-4a6a-b7a2-3e926c2e6da7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760323219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1760323219
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2372597581
Short name T621
Test name
Test status
Simulation time 30686536 ps
CPU time 0.59 seconds
Started Jul 07 05:44:12 PM PDT 24
Finished Jul 07 05:44:13 PM PDT 24
Peak memory 195360 kb
Host smart-305aea28-9e1a-4cbe-93c6-ccca96764fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372597581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2372597581
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4199754711
Short name T30
Test name
Test status
Simulation time 189012577 ps
CPU time 0.9 seconds
Started Jul 07 05:44:11 PM PDT 24
Finished Jul 07 05:44:12 PM PDT 24
Peak memory 196376 kb
Host smart-00d86ecf-89f9-4c52-aeb0-4e61d1b559ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199754711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4199754711
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.685943824
Short name T262
Test name
Test status
Simulation time 284969774 ps
CPU time 14.71 seconds
Started Jul 07 05:44:08 PM PDT 24
Finished Jul 07 05:44:23 PM PDT 24
Peak memory 198704 kb
Host smart-c9f06903-9239-447e-b891-36ad6c0284cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685943824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.685943824
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2247706452
Short name T173
Test name
Test status
Simulation time 144303717 ps
CPU time 0.92 seconds
Started Jul 07 05:44:14 PM PDT 24
Finished Jul 07 05:44:15 PM PDT 24
Peak memory 197384 kb
Host smart-629d2569-dd8a-4977-b0f0-b22ae6455229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247706452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2247706452
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1571913646
Short name T108
Test name
Test status
Simulation time 139636573 ps
CPU time 1.06 seconds
Started Jul 07 05:44:10 PM PDT 24
Finished Jul 07 05:44:12 PM PDT 24
Peak memory 196760 kb
Host smart-315bdade-aec9-44f1-ace8-aa703f132e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571913646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1571913646
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1333560089
Short name T101
Test name
Test status
Simulation time 75756611 ps
CPU time 3.16 seconds
Started Jul 07 05:44:09 PM PDT 24
Finished Jul 07 05:44:12 PM PDT 24
Peak memory 198776 kb
Host smart-e69791ee-a21e-44a9-9e64-33689c606499
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333560089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1333560089
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3582739312
Short name T356
Test name
Test status
Simulation time 60950273 ps
CPU time 1.36 seconds
Started Jul 07 05:44:08 PM PDT 24
Finished Jul 07 05:44:09 PM PDT 24
Peak memory 197020 kb
Host smart-9dbfd747-9e21-4228-b91d-644caf056903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582739312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3582739312
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2842975062
Short name T189
Test name
Test status
Simulation time 21774765 ps
CPU time 0.78 seconds
Started Jul 07 05:44:03 PM PDT 24
Finished Jul 07 05:44:05 PM PDT 24
Peak memory 195984 kb
Host smart-cf3c22c6-9a62-4401-8aed-3f907bded6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842975062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2842975062
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2341342047
Short name T197
Test name
Test status
Simulation time 185001504 ps
CPU time 1.25 seconds
Started Jul 07 05:44:09 PM PDT 24
Finished Jul 07 05:44:11 PM PDT 24
Peak memory 198080 kb
Host smart-d3db377c-0140-472e-aae1-5f08055c3678
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341342047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2341342047
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3307171104
Short name T113
Test name
Test status
Simulation time 576439970 ps
CPU time 2.83 seconds
Started Jul 07 05:44:11 PM PDT 24
Finished Jul 07 05:44:14 PM PDT 24
Peak memory 198516 kb
Host smart-ea975b38-a1cd-435d-a911-552f2fda47e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307171104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3307171104
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.355084342
Short name T296
Test name
Test status
Simulation time 38061897 ps
CPU time 0.96 seconds
Started Jul 07 05:44:05 PM PDT 24
Finished Jul 07 05:44:06 PM PDT 24
Peak memory 196036 kb
Host smart-96c1f358-c4dc-419d-a179-faa6f949ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355084342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.355084342
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3800585383
Short name T348
Test name
Test status
Simulation time 37594545 ps
CPU time 1.22 seconds
Started Jul 07 05:44:05 PM PDT 24
Finished Jul 07 05:44:07 PM PDT 24
Peak memory 197252 kb
Host smart-5dffc9e5-b898-4117-897d-9ceede413fb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800585383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3800585383
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1324879466
Short name T272
Test name
Test status
Simulation time 17978121215 ps
CPU time 100.82 seconds
Started Jul 07 05:44:09 PM PDT 24
Finished Jul 07 05:45:50 PM PDT 24
Peak memory 198848 kb
Host smart-d3091dd6-c1ea-429e-a09f-1310c9b5f622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324879466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1324879466
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3807567903
Short name T62
Test name
Test status
Simulation time 64699218031 ps
CPU time 1742.94 seconds
Started Jul 07 05:44:06 PM PDT 24
Finished Jul 07 06:13:09 PM PDT 24
Peak memory 198932 kb
Host smart-ca7c57ca-40a5-4d74-8718-4fdd6721cf3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3807567903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3807567903
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1084112069
Short name T192
Test name
Test status
Simulation time 17232947 ps
CPU time 0.55 seconds
Started Jul 07 05:44:14 PM PDT 24
Finished Jul 07 05:44:15 PM PDT 24
Peak memory 193468 kb
Host smart-fe0376df-ec81-4f6e-b8a9-08893030e3a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084112069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1084112069
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1966560569
Short name T142
Test name
Test status
Simulation time 33210601 ps
CPU time 0.85 seconds
Started Jul 07 05:44:13 PM PDT 24
Finished Jul 07 05:44:14 PM PDT 24
Peak memory 196100 kb
Host smart-aa5ad7a9-75f6-4a71-bd1e-ffd8955247eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966560569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1966560569
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3512209125
Short name T705
Test name
Test status
Simulation time 4305139535 ps
CPU time 22.34 seconds
Started Jul 07 05:44:14 PM PDT 24
Finished Jul 07 05:44:36 PM PDT 24
Peak memory 198812 kb
Host smart-76c8e505-032b-4865-a92d-2fc491d9c559
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512209125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3512209125
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1588321607
Short name T156
Test name
Test status
Simulation time 249581761 ps
CPU time 1.06 seconds
Started Jul 07 05:44:11 PM PDT 24
Finished Jul 07 05:44:12 PM PDT 24
Peak memory 197280 kb
Host smart-15d16d12-623b-410b-8c8f-255c0e4ac08d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588321607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1588321607
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2816328547
Short name T226
Test name
Test status
Simulation time 69542602 ps
CPU time 1.24 seconds
Started Jul 07 05:44:10 PM PDT 24
Finished Jul 07 05:44:11 PM PDT 24
Peak memory 196824 kb
Host smart-feb18a33-bfe8-47df-9e8a-75ba99d33d38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816328547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2816328547
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.500461114
Short name T495
Test name
Test status
Simulation time 191881512 ps
CPU time 1.56 seconds
Started Jul 07 05:44:10 PM PDT 24
Finished Jul 07 05:44:12 PM PDT 24
Peak memory 197468 kb
Host smart-aba94c8e-2005-4461-b6ef-70ce36edd461
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500461114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.500461114
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2272283329
Short name T368
Test name
Test status
Simulation time 134496813 ps
CPU time 3.46 seconds
Started Jul 07 05:44:16 PM PDT 24
Finished Jul 07 05:44:20 PM PDT 24
Peak memory 197656 kb
Host smart-f44f7422-aee5-4766-8f3e-62e0076853da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272283329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2272283329
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1788653092
Short name T686
Test name
Test status
Simulation time 36916632 ps
CPU time 0.96 seconds
Started Jul 07 05:44:12 PM PDT 24
Finished Jul 07 05:44:14 PM PDT 24
Peak memory 196736 kb
Host smart-55ed1b91-d52f-4ed0-91fd-64315df5b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788653092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1788653092
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3764390446
Short name T150
Test name
Test status
Simulation time 44372156 ps
CPU time 0.69 seconds
Started Jul 07 05:44:09 PM PDT 24
Finished Jul 07 05:44:10 PM PDT 24
Peak memory 195784 kb
Host smart-3b5f93a3-9b66-4984-83f3-7314a632ce92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764390446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3764390446
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.955544683
Short name T425
Test name
Test status
Simulation time 51072456 ps
CPU time 2.46 seconds
Started Jul 07 05:44:14 PM PDT 24
Finished Jul 07 05:44:17 PM PDT 24
Peak memory 198692 kb
Host smart-2d3c6327-c242-4f37-8146-d8c5d257b99a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955544683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.955544683
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1070131720
Short name T35
Test name
Test status
Simulation time 1651005451 ps
CPU time 1 seconds
Started Jul 07 05:44:22 PM PDT 24
Finished Jul 07 05:44:23 PM PDT 24
Peak memory 215436 kb
Host smart-146cc5ea-68e0-4b3c-b129-e215216cd67c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070131720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1070131720
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1957086388
Short name T116
Test name
Test status
Simulation time 53901235 ps
CPU time 1.09 seconds
Started Jul 07 05:44:12 PM PDT 24
Finished Jul 07 05:44:13 PM PDT 24
Peak memory 197128 kb
Host smart-ba4f576d-14ad-48e2-9f16-3f6b9df95b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957086388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1957086388
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3020468193
Short name T590
Test name
Test status
Simulation time 72820068 ps
CPU time 1.31 seconds
Started Jul 07 05:44:11 PM PDT 24
Finished Jul 07 05:44:13 PM PDT 24
Peak memory 196528 kb
Host smart-f05150ae-3685-484b-82be-456b2db08614
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020468193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3020468193
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.204070463
Short name T502
Test name
Test status
Simulation time 2265251609 ps
CPU time 57.17 seconds
Started Jul 07 05:44:15 PM PDT 24
Finished Jul 07 05:45:13 PM PDT 24
Peak memory 198804 kb
Host smart-ccd85492-6fbd-46ba-b21b-6f8725b02a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204070463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.204070463
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.200106165
Short name T391
Test name
Test status
Simulation time 15188922 ps
CPU time 0.58 seconds
Started Jul 07 05:45:00 PM PDT 24
Finished Jul 07 05:45:01 PM PDT 24
Peak memory 195380 kb
Host smart-b64e0576-c071-440e-88e3-67f3a8843d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200106165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.200106165
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2892553203
Short name T131
Test name
Test status
Simulation time 46378482 ps
CPU time 0.68 seconds
Started Jul 07 05:45:07 PM PDT 24
Finished Jul 07 05:45:08 PM PDT 24
Peak memory 195560 kb
Host smart-59980677-7a55-4469-ad50-9ec2c8115e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892553203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2892553203
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1492639045
Short name T149
Test name
Test status
Simulation time 1012531393 ps
CPU time 8.69 seconds
Started Jul 07 05:45:03 PM PDT 24
Finished Jul 07 05:45:12 PM PDT 24
Peak memory 196888 kb
Host smart-17e68762-37a8-42d1-aed7-1192a7d95eb5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492639045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1492639045
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.713117795
Short name T673
Test name
Test status
Simulation time 57345101 ps
CPU time 0.82 seconds
Started Jul 07 05:44:59 PM PDT 24
Finished Jul 07 05:45:00 PM PDT 24
Peak memory 196468 kb
Host smart-81b4be56-ec12-4ff8-a39c-6ddde3024be9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713117795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.713117795
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.264164055
Short name T577
Test name
Test status
Simulation time 131858897 ps
CPU time 1.16 seconds
Started Jul 07 05:44:58 PM PDT 24
Finished Jul 07 05:45:00 PM PDT 24
Peak memory 197464 kb
Host smart-5baee6d6-d539-4bf6-a510-06127df987eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264164055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.264164055
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.524447092
Short name T244
Test name
Test status
Simulation time 1739246027 ps
CPU time 3.96 seconds
Started Jul 07 05:45:06 PM PDT 24
Finished Jul 07 05:45:10 PM PDT 24
Peak memory 198768 kb
Host smart-b60f65e1-237a-4298-92a2-7bf9b3e3ebbe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524447092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.524447092
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.828807201
Short name T322
Test name
Test status
Simulation time 64253503 ps
CPU time 2.04 seconds
Started Jul 07 05:45:00 PM PDT 24
Finished Jul 07 05:45:02 PM PDT 24
Peak memory 197840 kb
Host smart-9e78b228-fe97-4aa5-bf2f-c0ba54a22659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828807201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
828807201
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3316062213
Short name T617
Test name
Test status
Simulation time 65185484 ps
CPU time 1.26 seconds
Started Jul 07 05:44:56 PM PDT 24
Finished Jul 07 05:44:58 PM PDT 24
Peak memory 197744 kb
Host smart-b4741822-ebe4-4683-8341-21f93ce6d542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316062213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3316062213
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1877791380
Short name T588
Test name
Test status
Simulation time 50930356 ps
CPU time 1.05 seconds
Started Jul 07 05:44:56 PM PDT 24
Finished Jul 07 05:44:57 PM PDT 24
Peak memory 196704 kb
Host smart-5b169974-734a-4738-9409-c779a1183cad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877791380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1877791380
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2638370394
Short name T161
Test name
Test status
Simulation time 60354756 ps
CPU time 2.94 seconds
Started Jul 07 05:45:02 PM PDT 24
Finished Jul 07 05:45:05 PM PDT 24
Peak memory 198664 kb
Host smart-f1c26587-61e7-4a39-b761-d6bdcd44ecc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638370394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2638370394
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.498570978
Short name T231
Test name
Test status
Simulation time 42623199 ps
CPU time 0.88 seconds
Started Jul 07 05:44:56 PM PDT 24
Finished Jul 07 05:44:57 PM PDT 24
Peak memory 196060 kb
Host smart-a3c6aa7d-ec9e-4fbe-91c6-228286cd6e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498570978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.498570978
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2830431622
Short name T423
Test name
Test status
Simulation time 182877948 ps
CPU time 1.35 seconds
Started Jul 07 05:44:56 PM PDT 24
Finished Jul 07 05:44:57 PM PDT 24
Peak memory 197388 kb
Host smart-d8e2e42e-94f3-4908-b3b4-0a82026035a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830431622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2830431622
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2329944599
Short name T10
Test name
Test status
Simulation time 9704989235 ps
CPU time 107.22 seconds
Started Jul 07 05:45:03 PM PDT 24
Finished Jul 07 05:46:51 PM PDT 24
Peak memory 198808 kb
Host smart-fff61163-f699-487b-baaa-0d656a95a25b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329944599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2329944599
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.371442392
Short name T659
Test name
Test status
Simulation time 180721333950 ps
CPU time 1208.18 seconds
Started Jul 07 05:44:59 PM PDT 24
Finished Jul 07 06:05:08 PM PDT 24
Peak memory 199196 kb
Host smart-36fedf5d-4fca-4152-a0af-cf67cac96d65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=371442392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.371442392
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.656040857
Short name T340
Test name
Test status
Simulation time 75221024 ps
CPU time 0.6 seconds
Started Jul 07 05:45:11 PM PDT 24
Finished Jul 07 05:45:12 PM PDT 24
Peak memory 195524 kb
Host smart-c2366476-9314-4146-bbc3-f83925b2ff5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656040857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.656040857
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.667682303
Short name T603
Test name
Test status
Simulation time 76637564 ps
CPU time 0.95 seconds
Started Jul 07 05:45:09 PM PDT 24
Finished Jul 07 05:45:10 PM PDT 24
Peak memory 197904 kb
Host smart-821c2b2f-1cca-42c1-8fcc-3ed3b7f5cbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667682303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.667682303
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3267400312
Short name T550
Test name
Test status
Simulation time 329886157 ps
CPU time 8.03 seconds
Started Jul 07 05:45:07 PM PDT 24
Finished Jul 07 05:45:15 PM PDT 24
Peak memory 196268 kb
Host smart-94b6d699-73cb-4133-8824-04f2ac1c3614
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267400312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3267400312
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3133760461
Short name T421
Test name
Test status
Simulation time 91720871 ps
CPU time 1.11 seconds
Started Jul 07 05:45:05 PM PDT 24
Finished Jul 07 05:45:07 PM PDT 24
Peak memory 197196 kb
Host smart-03a541e9-b38c-4747-b18b-8d619dd2517f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133760461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3133760461
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2935855652
Short name T95
Test name
Test status
Simulation time 25076820 ps
CPU time 0.89 seconds
Started Jul 07 05:45:08 PM PDT 24
Finished Jul 07 05:45:09 PM PDT 24
Peak memory 197064 kb
Host smart-b364e1c0-bb00-4cc0-9033-f4ff8b21489b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935855652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2935855652
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2847368186
Short name T349
Test name
Test status
Simulation time 52321501 ps
CPU time 1.5 seconds
Started Jul 07 05:45:02 PM PDT 24
Finished Jul 07 05:45:04 PM PDT 24
Peak memory 197308 kb
Host smart-90f67957-2e5c-4449-bed1-049846f5f979
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847368186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2847368186
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3411588267
Short name T177
Test name
Test status
Simulation time 169291022 ps
CPU time 3.13 seconds
Started Jul 07 05:45:03 PM PDT 24
Finished Jul 07 05:45:07 PM PDT 24
Peak memory 198752 kb
Host smart-de3b6645-cc84-4d5c-874d-1690bb98247e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411588267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3411588267
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1463654662
Short name T193
Test name
Test status
Simulation time 118508180 ps
CPU time 1.22 seconds
Started Jul 07 05:45:06 PM PDT 24
Finished Jul 07 05:45:08 PM PDT 24
Peak memory 197236 kb
Host smart-65a33c7c-dfd4-48a1-ae40-57f244a38ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463654662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1463654662
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1591418806
Short name T334
Test name
Test status
Simulation time 93319230 ps
CPU time 1.01 seconds
Started Jul 07 05:45:04 PM PDT 24
Finished Jul 07 05:45:05 PM PDT 24
Peak memory 197352 kb
Host smart-e1361c39-27ca-4069-9e7d-427a75a182bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591418806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1591418806
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1588749031
Short name T553
Test name
Test status
Simulation time 1489575411 ps
CPU time 4.26 seconds
Started Jul 07 05:45:06 PM PDT 24
Finished Jul 07 05:45:10 PM PDT 24
Peak memory 198612 kb
Host smart-ec000224-b3c9-4e41-beb9-301ceb3a296b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588749031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1588749031
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3404633813
Short name T374
Test name
Test status
Simulation time 180203782 ps
CPU time 0.95 seconds
Started Jul 07 05:45:00 PM PDT 24
Finished Jul 07 05:45:01 PM PDT 24
Peak memory 197652 kb
Host smart-e957b02c-a08a-4fc2-9c12-5a502bded86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404633813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3404633813
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.297859675
Short name T330
Test name
Test status
Simulation time 51504195 ps
CPU time 1.1 seconds
Started Jul 07 05:45:03 PM PDT 24
Finished Jul 07 05:45:05 PM PDT 24
Peak memory 196948 kb
Host smart-bff49d50-d5d9-450d-b24d-43ded5285f22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297859675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.297859675
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2737284862
Short name T666
Test name
Test status
Simulation time 4344897884 ps
CPU time 50.97 seconds
Started Jul 07 05:45:05 PM PDT 24
Finished Jul 07 05:45:56 PM PDT 24
Peak memory 198844 kb
Host smart-7cec302c-07b6-479e-9f3f-14160398c6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737284862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2737284862
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.471183778
Short name T549
Test name
Test status
Simulation time 79647717528 ps
CPU time 1276.05 seconds
Started Jul 07 05:45:12 PM PDT 24
Finished Jul 07 06:06:28 PM PDT 24
Peak memory 198924 kb
Host smart-2136ea91-a6ed-4bb4-9750-50d8e47d1f47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=471183778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.471183778
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1800238575
Short name T287
Test name
Test status
Simulation time 50096587 ps
CPU time 0.58 seconds
Started Jul 07 05:45:10 PM PDT 24
Finished Jul 07 05:45:11 PM PDT 24
Peak memory 194644 kb
Host smart-5c35b2cf-f0ac-4f49-9aed-6ba642a0d22d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800238575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1800238575
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3760759120
Short name T670
Test name
Test status
Simulation time 25467509 ps
CPU time 0.84 seconds
Started Jul 07 05:45:06 PM PDT 24
Finished Jul 07 05:45:07 PM PDT 24
Peak memory 197200 kb
Host smart-c0ac36e2-1dea-443f-8cc1-916bf94af412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760759120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3760759120
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3578537624
Short name T117
Test name
Test status
Simulation time 14972202511 ps
CPU time 27.49 seconds
Started Jul 07 05:45:10 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 197436 kb
Host smart-6bef142b-9a4b-4b79-8d31-2f98bc9f7ef2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578537624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3578537624
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1221941765
Short name T271
Test name
Test status
Simulation time 120748604 ps
CPU time 0.64 seconds
Started Jul 07 05:45:14 PM PDT 24
Finished Jul 07 05:45:15 PM PDT 24
Peak memory 195176 kb
Host smart-e9451caf-21eb-4ce7-b926-218079968380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221941765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1221941765
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1538987309
Short name T290
Test name
Test status
Simulation time 93226706 ps
CPU time 0.9 seconds
Started Jul 07 05:45:06 PM PDT 24
Finished Jul 07 05:45:07 PM PDT 24
Peak memory 197068 kb
Host smart-eeb12013-69e6-43bb-92da-cf489296ebd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538987309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1538987309
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3719978262
Short name T180
Test name
Test status
Simulation time 376497982 ps
CPU time 3.84 seconds
Started Jul 07 05:45:09 PM PDT 24
Finished Jul 07 05:45:13 PM PDT 24
Peak memory 198692 kb
Host smart-a1e49290-3912-4013-a250-22b3a5c915cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719978262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3719978262
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2657079261
Short name T64
Test name
Test status
Simulation time 576228662 ps
CPU time 3.32 seconds
Started Jul 07 05:45:08 PM PDT 24
Finished Jul 07 05:45:11 PM PDT 24
Peak memory 198780 kb
Host smart-4246a5c5-31d2-4995-a364-58e9f004b2be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657079261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2657079261
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1983395267
Short name T506
Test name
Test status
Simulation time 255653745 ps
CPU time 1.33 seconds
Started Jul 07 05:45:08 PM PDT 24
Finished Jul 07 05:45:10 PM PDT 24
Peak memory 198768 kb
Host smart-c264c0e6-57c4-4c01-bf32-07de2d77f9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983395267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1983395267
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1566750659
Short name T308
Test name
Test status
Simulation time 60698740 ps
CPU time 1.43 seconds
Started Jul 07 05:45:07 PM PDT 24
Finished Jul 07 05:45:09 PM PDT 24
Peak memory 198640 kb
Host smart-b7d002b9-9705-43df-879a-7fa700656c68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566750659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1566750659
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1789658263
Short name T438
Test name
Test status
Simulation time 88701431 ps
CPU time 3.91 seconds
Started Jul 07 05:45:11 PM PDT 24
Finished Jul 07 05:45:15 PM PDT 24
Peak memory 198896 kb
Host smart-47a099b8-1548-4dc4-b82b-fb6d0afdc183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789658263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1789658263
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2356223009
Short name T346
Test name
Test status
Simulation time 84943530 ps
CPU time 0.91 seconds
Started Jul 07 05:45:08 PM PDT 24
Finished Jul 07 05:45:09 PM PDT 24
Peak memory 196128 kb
Host smart-21e28ed7-f66e-426a-b75f-f14a8b0feb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356223009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2356223009
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.258183525
Short name T709
Test name
Test status
Simulation time 351251314 ps
CPU time 1.37 seconds
Started Jul 07 05:45:12 PM PDT 24
Finished Jul 07 05:45:14 PM PDT 24
Peak memory 197584 kb
Host smart-33b6bccf-94ae-4e96-91e2-93e136512e40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258183525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.258183525
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3654088658
Short name T265
Test name
Test status
Simulation time 25536946170 ps
CPU time 139.36 seconds
Started Jul 07 05:45:14 PM PDT 24
Finished Jul 07 05:47:34 PM PDT 24
Peak memory 198812 kb
Host smart-9617621a-46fe-4348-bed2-d7cfa02ccfac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654088658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3654088658
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.209263113
Short name T358
Test name
Test status
Simulation time 39252419 ps
CPU time 0.6 seconds
Started Jul 07 05:45:18 PM PDT 24
Finished Jul 07 05:45:19 PM PDT 24
Peak memory 194684 kb
Host smart-80b024b7-5f0a-451b-9dcc-9669fd61075a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209263113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.209263113
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4117405351
Short name T24
Test name
Test status
Simulation time 78161479 ps
CPU time 0.83 seconds
Started Jul 07 05:45:13 PM PDT 24
Finished Jul 07 05:45:14 PM PDT 24
Peak memory 196624 kb
Host smart-44736cf1-0bc7-420c-8a5d-689dd4b65676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117405351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4117405351
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1190031132
Short name T352
Test name
Test status
Simulation time 1879843649 ps
CPU time 19.67 seconds
Started Jul 07 05:45:14 PM PDT 24
Finished Jul 07 05:45:34 PM PDT 24
Peak memory 197508 kb
Host smart-86004ac3-5d06-4d6d-8519-301eeb8e146f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190031132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1190031132
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2270306024
Short name T665
Test name
Test status
Simulation time 145030156 ps
CPU time 0.72 seconds
Started Jul 07 05:45:15 PM PDT 24
Finished Jul 07 05:45:16 PM PDT 24
Peak memory 196108 kb
Host smart-097fa00b-b315-4ebc-adf4-fe71ebfc5b5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270306024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2270306024
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3618246288
Short name T399
Test name
Test status
Simulation time 15291425 ps
CPU time 0.65 seconds
Started Jul 07 05:45:19 PM PDT 24
Finished Jul 07 05:45:20 PM PDT 24
Peak memory 194908 kb
Host smart-1ee24a8f-6fb0-4289-9471-6223778764f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618246288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3618246288
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3059074035
Short name T136
Test name
Test status
Simulation time 354577641 ps
CPU time 3.83 seconds
Started Jul 07 05:45:17 PM PDT 24
Finished Jul 07 05:45:22 PM PDT 24
Peak memory 198752 kb
Host smart-8bcf47c9-0781-4823-be55-d5fa88a7b2ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059074035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3059074035
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1513155789
Short name T655
Test name
Test status
Simulation time 1077735040 ps
CPU time 3.59 seconds
Started Jul 07 05:45:14 PM PDT 24
Finished Jul 07 05:45:18 PM PDT 24
Peak memory 198032 kb
Host smart-e8fccab3-faf9-4742-b51a-84231a7013e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513155789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1513155789
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2443541200
Short name T311
Test name
Test status
Simulation time 125376328 ps
CPU time 0.8 seconds
Started Jul 07 05:45:16 PM PDT 24
Finished Jul 07 05:45:17 PM PDT 24
Peak memory 196208 kb
Host smart-65ef3af5-1af3-4f9e-bfb5-66307047073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443541200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2443541200
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2604624095
Short name T201
Test name
Test status
Simulation time 251869606 ps
CPU time 1.38 seconds
Started Jul 07 05:45:18 PM PDT 24
Finished Jul 07 05:45:20 PM PDT 24
Peak memory 197720 kb
Host smart-379e7891-af40-4f16-9bd6-17ec1e37d398
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604624095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2604624095
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3750331456
Short name T2
Test name
Test status
Simulation time 581318435 ps
CPU time 6.37 seconds
Started Jul 07 05:45:17 PM PDT 24
Finished Jul 07 05:45:24 PM PDT 24
Peak memory 198628 kb
Host smart-2ddd0866-3854-46d4-8588-5667a4acd5f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750331456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3750331456
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1820446489
Short name T514
Test name
Test status
Simulation time 51131007 ps
CPU time 1.15 seconds
Started Jul 07 05:45:14 PM PDT 24
Finished Jul 07 05:45:15 PM PDT 24
Peak memory 198716 kb
Host smart-c1a243d8-a422-4eb9-8f80-11b7c913f4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820446489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1820446489
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1442659343
Short name T232
Test name
Test status
Simulation time 123571384 ps
CPU time 1.03 seconds
Started Jul 07 05:45:14 PM PDT 24
Finished Jul 07 05:45:15 PM PDT 24
Peak memory 196400 kb
Host smart-b3e512c2-5d40-46d9-834c-5d4ff344d662
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442659343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1442659343
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2154928178
Short name T298
Test name
Test status
Simulation time 13636911221 ps
CPU time 39.39 seconds
Started Jul 07 05:45:17 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 198776 kb
Host smart-f20b02c1-b6d1-444b-ad1c-39f8b7145e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154928178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2154928178
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.79471496
Short name T326
Test name
Test status
Simulation time 34441093 ps
CPU time 0.55 seconds
Started Jul 07 05:45:18 PM PDT 24
Finished Jul 07 05:45:18 PM PDT 24
Peak memory 195700 kb
Host smart-e8c69b4e-e1b9-42a4-ac49-8ce736108af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79471496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.79471496
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3911199786
Short name T445
Test name
Test status
Simulation time 24252938 ps
CPU time 0.79 seconds
Started Jul 07 05:45:19 PM PDT 24
Finished Jul 07 05:45:20 PM PDT 24
Peak memory 196852 kb
Host smart-d7913208-3feb-49bd-b23c-ef830a2d70a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911199786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3911199786
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2402197097
Short name T274
Test name
Test status
Simulation time 1477683484 ps
CPU time 18.22 seconds
Started Jul 07 05:45:18 PM PDT 24
Finished Jul 07 05:45:37 PM PDT 24
Peak memory 197628 kb
Host smart-a41450c0-503f-413a-8d85-e64a70100b76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402197097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2402197097
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1296309560
Short name T347
Test name
Test status
Simulation time 215711240 ps
CPU time 0.82 seconds
Started Jul 07 05:45:16 PM PDT 24
Finished Jul 07 05:45:17 PM PDT 24
Peak memory 196492 kb
Host smart-149d2b75-f62b-40a3-bb32-9150d520881b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296309560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1296309560
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3995397049
Short name T221
Test name
Test status
Simulation time 90620712 ps
CPU time 1.56 seconds
Started Jul 07 05:45:16 PM PDT 24
Finished Jul 07 05:45:18 PM PDT 24
Peak memory 197712 kb
Host smart-484492a8-bf5b-48f1-8dd2-3836b040250f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995397049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3995397049
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3387505643
Short name T396
Test name
Test status
Simulation time 465187331 ps
CPU time 3.61 seconds
Started Jul 07 05:45:19 PM PDT 24
Finished Jul 07 05:45:23 PM PDT 24
Peak memory 198808 kb
Host smart-e6d609e1-dbb5-47a6-96a8-45a825397d1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387505643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3387505643
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1458825213
Short name T476
Test name
Test status
Simulation time 38126454 ps
CPU time 1.31 seconds
Started Jul 07 05:45:23 PM PDT 24
Finished Jul 07 05:45:25 PM PDT 24
Peak memory 197380 kb
Host smart-4c46317c-5cc4-42b4-bebf-63f9cc383bd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458825213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1458825213
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2178856386
Short name T284
Test name
Test status
Simulation time 69449099 ps
CPU time 1.4 seconds
Started Jul 07 05:45:19 PM PDT 24
Finished Jul 07 05:45:21 PM PDT 24
Peak memory 198644 kb
Host smart-44cfc33e-43bd-490d-856c-8c63e07fa5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178856386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2178856386
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.982139003
Short name T579
Test name
Test status
Simulation time 16563707 ps
CPU time 0.78 seconds
Started Jul 07 05:45:16 PM PDT 24
Finished Jul 07 05:45:17 PM PDT 24
Peak memory 196148 kb
Host smart-31248276-8be1-4eeb-a21f-f9cd6c72e6cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982139003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.982139003
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3435242375
Short name T571
Test name
Test status
Simulation time 622465448 ps
CPU time 5.38 seconds
Started Jul 07 05:45:22 PM PDT 24
Finished Jul 07 05:45:27 PM PDT 24
Peak memory 198620 kb
Host smart-0cd920d8-930d-4657-8f7e-4937b3792cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435242375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3435242375
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3943964156
Short name T541
Test name
Test status
Simulation time 378510097 ps
CPU time 1.26 seconds
Started Jul 07 05:45:15 PM PDT 24
Finished Jul 07 05:45:16 PM PDT 24
Peak memory 196620 kb
Host smart-7179bd8d-1021-4dff-84a8-c0d29841c5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943964156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3943964156
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.9113887
Short name T335
Test name
Test status
Simulation time 26269270 ps
CPU time 0.69 seconds
Started Jul 07 05:45:13 PM PDT 24
Finished Jul 07 05:45:14 PM PDT 24
Peak memory 194848 kb
Host smart-1f28b57b-02b5-400c-80d6-49373c69a164
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9113887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.9113887
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3033639021
Short name T277
Test name
Test status
Simulation time 5168051350 ps
CPU time 156.81 seconds
Started Jul 07 05:45:21 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 198840 kb
Host smart-782b4191-92e9-4961-8bd3-f39cb525df38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033639021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3033639021
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2647263210
Short name T688
Test name
Test status
Simulation time 57593522814 ps
CPU time 1707.59 seconds
Started Jul 07 05:45:17 PM PDT 24
Finished Jul 07 06:13:45 PM PDT 24
Peak memory 198920 kb
Host smart-be69ed18-f1f0-4015-9977-2483f60f60a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2647263210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2647263210
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3326872685
Short name T230
Test name
Test status
Simulation time 12525574 ps
CPU time 0.58 seconds
Started Jul 07 05:45:22 PM PDT 24
Finished Jul 07 05:45:23 PM PDT 24
Peak memory 194672 kb
Host smart-fd76ac93-849f-4a98-94fa-0de57f56ab9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326872685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3326872685
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.4028437831
Short name T641
Test name
Test status
Simulation time 114315783 ps
CPU time 0.76 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:26 PM PDT 24
Peak memory 196060 kb
Host smart-c27188f0-55bf-49c7-83f9-a6cf56a446bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028437831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.4028437831
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1604582023
Short name T710
Test name
Test status
Simulation time 3475026675 ps
CPU time 23.65 seconds
Started Jul 07 05:45:34 PM PDT 24
Finished Jul 07 05:45:58 PM PDT 24
Peak memory 198160 kb
Host smart-92518523-d1c5-4746-9cd0-333a52cf2c92
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604582023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1604582023
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1991962673
Short name T97
Test name
Test status
Simulation time 76764566 ps
CPU time 0.64 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:26 PM PDT 24
Peak memory 195404 kb
Host smart-c3aa2360-a01a-46b0-b830-c69154e41bcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991962673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1991962673
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.426415415
Short name T440
Test name
Test status
Simulation time 52174407 ps
CPU time 0.67 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:27 PM PDT 24
Peak memory 194888 kb
Host smart-2d41d8d4-f2d8-4bcc-88e9-f3959329f7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426415415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.426415415
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2826983849
Short name T383
Test name
Test status
Simulation time 329927172 ps
CPU time 3.12 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 198660 kb
Host smart-a418a085-9e26-4b10-8572-368ca5f54a10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826983849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2826983849
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4045268287
Short name T379
Test name
Test status
Simulation time 1753564677 ps
CPU time 2.36 seconds
Started Jul 07 05:45:26 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 198728 kb
Host smart-ef303789-acec-497d-91a0-ea27a4d18fd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045268287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4045268287
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1867438639
Short name T260
Test name
Test status
Simulation time 66915302 ps
CPU time 1.25 seconds
Started Jul 07 05:45:27 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 198680 kb
Host smart-096b9586-532b-4e31-a796-05aee295342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867438639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1867438639
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.895130058
Short name T456
Test name
Test status
Simulation time 33873632 ps
CPU time 0.7 seconds
Started Jul 07 05:45:26 PM PDT 24
Finished Jul 07 05:45:27 PM PDT 24
Peak memory 195040 kb
Host smart-a60df661-ce14-46e4-8714-db1d7accc972
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895130058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.895130058
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.902989485
Short name T459
Test name
Test status
Simulation time 538219054 ps
CPU time 2.46 seconds
Started Jul 07 05:45:26 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 198656 kb
Host smart-c7b201aa-28f8-4027-9d06-f83da020afe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902989485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.902989485
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.111210899
Short name T154
Test name
Test status
Simulation time 337615941 ps
CPU time 1.33 seconds
Started Jul 07 05:45:20 PM PDT 24
Finished Jul 07 05:45:21 PM PDT 24
Peak memory 197440 kb
Host smart-a920043b-0bc5-44bf-a2b6-8f8432527aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111210899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.111210899
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1140909173
Short name T516
Test name
Test status
Simulation time 52568687 ps
CPU time 0.98 seconds
Started Jul 07 05:45:20 PM PDT 24
Finished Jul 07 05:45:21 PM PDT 24
Peak memory 196944 kb
Host smart-9ade2a42-2435-4b5b-9b44-86b026640f10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140909173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1140909173
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2280745868
Short name T29
Test name
Test status
Simulation time 9136432782 ps
CPU time 53.86 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 198792 kb
Host smart-9ad66061-01c8-4245-b214-7e7de45f471f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280745868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2280745868
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.815197365
Short name T566
Test name
Test status
Simulation time 14576166837 ps
CPU time 465.62 seconds
Started Jul 07 05:45:23 PM PDT 24
Finished Jul 07 05:53:09 PM PDT 24
Peak memory 198892 kb
Host smart-53f31b4f-1c84-43fa-81e4-5ca6e084b078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=815197365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.815197365
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2610692697
Short name T38
Test name
Test status
Simulation time 13390493 ps
CPU time 0.59 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:25 PM PDT 24
Peak memory 195352 kb
Host smart-94bdf922-c1e6-46b1-bb60-ee0e7b260c94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610692697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2610692697
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.644354949
Short name T214
Test name
Test status
Simulation time 63975024 ps
CPU time 0.64 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:45:34 PM PDT 24
Peak memory 194796 kb
Host smart-d44fa39f-c9a4-4ee5-a372-6f9b54061505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644354949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.644354949
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3871751250
Short name T466
Test name
Test status
Simulation time 953235486 ps
CPU time 12.6 seconds
Started Jul 07 05:45:22 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 197820 kb
Host smart-19dd1507-64f9-43fa-b032-081b1bad7378
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871751250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3871751250
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.513788910
Short name T497
Test name
Test status
Simulation time 246160059 ps
CPU time 0.91 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:27 PM PDT 24
Peak memory 197644 kb
Host smart-b754ed3d-7ca7-4469-afde-a5bfa3c90d00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513788910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.513788910
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.222497516
Short name T17
Test name
Test status
Simulation time 39296478 ps
CPU time 1.14 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:45:34 PM PDT 24
Peak memory 197384 kb
Host smart-4651777b-89ed-4ce3-8052-5d4f258cc807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222497516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.222497516
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3333643247
Short name T464
Test name
Test status
Simulation time 41652855 ps
CPU time 1.61 seconds
Started Jul 07 05:45:34 PM PDT 24
Finished Jul 07 05:45:36 PM PDT 24
Peak memory 197088 kb
Host smart-aad16361-3e61-49a5-a8e4-5171db3af784
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333643247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3333643247
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3006888735
Short name T202
Test name
Test status
Simulation time 353556109 ps
CPU time 3.31 seconds
Started Jul 07 05:45:21 PM PDT 24
Finished Jul 07 05:45:24 PM PDT 24
Peak memory 198772 kb
Host smart-f029d4e8-0a89-4e24-af05-c9b909fbb03d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006888735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3006888735
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.807531793
Short name T130
Test name
Test status
Simulation time 50927537 ps
CPU time 0.72 seconds
Started Jul 07 05:45:34 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 196188 kb
Host smart-6647c886-ab5d-49bf-88a1-638559ccea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807531793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.807531793
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3647014303
Short name T281
Test name
Test status
Simulation time 24047563 ps
CPU time 0.92 seconds
Started Jul 07 05:45:23 PM PDT 24
Finished Jul 07 05:45:24 PM PDT 24
Peak memory 196740 kb
Host smart-388d4477-24cb-42e8-8329-dbc279ea45e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647014303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3647014303
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.762809772
Short name T8
Test name
Test status
Simulation time 298694197 ps
CPU time 3.96 seconds
Started Jul 07 05:45:25 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 198896 kb
Host smart-56830fca-31d6-4b5c-b74d-de8c3b413369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762809772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.762809772
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.202283192
Short name T384
Test name
Test status
Simulation time 52777223 ps
CPU time 0.95 seconds
Started Jul 07 05:45:24 PM PDT 24
Finished Jul 07 05:45:25 PM PDT 24
Peak memory 196928 kb
Host smart-ae1f4718-944b-4490-af58-d0696c7ab9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202283192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.202283192
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.672419366
Short name T589
Test name
Test status
Simulation time 148515985 ps
CPU time 1.2 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 198672 kb
Host smart-f259b117-381c-4747-a61e-cf2d2dbac5cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672419366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.672419366
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.327746422
Short name T252
Test name
Test status
Simulation time 3400749482 ps
CPU time 53.46 seconds
Started Jul 07 05:45:26 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 198800 kb
Host smart-8b37ccb0-435e-4bd6-9769-bdb7865936e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327746422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.327746422
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1219374460
Short name T711
Test name
Test status
Simulation time 89519783106 ps
CPU time 1098.24 seconds
Started Jul 07 05:45:30 PM PDT 24
Finished Jul 07 06:03:49 PM PDT 24
Peak memory 198884 kb
Host smart-962a1443-7042-4a64-83c4-8a395d4fca4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1219374460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1219374460
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3926675487
Short name T310
Test name
Test status
Simulation time 56104644 ps
CPU time 0.57 seconds
Started Jul 07 05:45:31 PM PDT 24
Finished Jul 07 05:45:31 PM PDT 24
Peak memory 195320 kb
Host smart-960a9ef2-7da3-4949-be10-b4d37aa28424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926675487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3926675487
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1608438757
Short name T572
Test name
Test status
Simulation time 138462234 ps
CPU time 0.8 seconds
Started Jul 07 05:45:29 PM PDT 24
Finished Jul 07 05:45:30 PM PDT 24
Peak memory 196048 kb
Host smart-822aea45-4187-48f8-8aba-13e24699d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608438757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1608438757
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3297151061
Short name T314
Test name
Test status
Simulation time 298862338 ps
CPU time 8.28 seconds
Started Jul 07 05:45:30 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 197304 kb
Host smart-f2a12314-5879-4a13-b861-052a430e67c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297151061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3297151061
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1242382105
Short name T567
Test name
Test status
Simulation time 23224005 ps
CPU time 0.67 seconds
Started Jul 07 05:45:30 PM PDT 24
Finished Jul 07 05:45:31 PM PDT 24
Peak memory 196000 kb
Host smart-b2fbbc5f-6cd7-4ee6-9115-709a615adfd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242382105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1242382105
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.522739898
Short name T593
Test name
Test status
Simulation time 87063171 ps
CPU time 1.31 seconds
Started Jul 07 05:45:28 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 196744 kb
Host smart-118f8ddf-2c88-4232-b49d-5b95b8a8d13c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522739898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.522739898
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3037421515
Short name T184
Test name
Test status
Simulation time 240961911 ps
CPU time 2.64 seconds
Started Jul 07 05:45:31 PM PDT 24
Finished Jul 07 05:45:34 PM PDT 24
Peak memory 198704 kb
Host smart-6248e73f-3ff9-41a1-a6c2-5f854b31ae5b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037421515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3037421515
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.964152348
Short name T369
Test name
Test status
Simulation time 1252628503 ps
CPU time 1.69 seconds
Started Jul 07 05:45:29 PM PDT 24
Finished Jul 07 05:45:31 PM PDT 24
Peak memory 197404 kb
Host smart-3e5949f5-446f-40e3-a453-4a58cf69663a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964152348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
964152348
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.4119215029
Short name T112
Test name
Test status
Simulation time 146970501 ps
CPU time 1.06 seconds
Started Jul 07 05:45:29 PM PDT 24
Finished Jul 07 05:45:30 PM PDT 24
Peak memory 196668 kb
Host smart-1c5aaea9-626f-4eb3-a65d-98b4a8bbe318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119215029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.4119215029
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3803732321
Short name T176
Test name
Test status
Simulation time 78401471 ps
CPU time 1.37 seconds
Started Jul 07 05:45:28 PM PDT 24
Finished Jul 07 05:45:30 PM PDT 24
Peak memory 197712 kb
Host smart-c76bca74-bd33-4aeb-831e-116c747520f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803732321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3803732321
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3613958388
Short name T698
Test name
Test status
Simulation time 165211420 ps
CPU time 2.31 seconds
Started Jul 07 05:45:29 PM PDT 24
Finished Jul 07 05:45:32 PM PDT 24
Peak memory 198580 kb
Host smart-5cae213c-9aa2-4527-8405-f016a7c12a82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613958388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3613958388
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1471101945
Short name T556
Test name
Test status
Simulation time 54984131 ps
CPU time 1.49 seconds
Started Jul 07 05:45:27 PM PDT 24
Finished Jul 07 05:45:28 PM PDT 24
Peak memory 198720 kb
Host smart-46449cfe-c60a-4968-ac03-83408c0823d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471101945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1471101945
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3961973027
Short name T174
Test name
Test status
Simulation time 52497311 ps
CPU time 1.46 seconds
Started Jul 07 05:45:26 PM PDT 24
Finished Jul 07 05:45:27 PM PDT 24
Peak memory 198984 kb
Host smart-d78bef0d-c059-4650-bc4a-d4dfd15fd887
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961973027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3961973027
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3373388479
Short name T656
Test name
Test status
Simulation time 16759840654 ps
CPU time 117.57 seconds
Started Jul 07 05:45:32 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 198804 kb
Host smart-72bd40c8-d84a-4d85-9cb7-ca97f2e7e25e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373388479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3373388479
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.4174487987
Short name T607
Test name
Test status
Simulation time 14151094 ps
CPU time 0.61 seconds
Started Jul 07 05:45:37 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 194872 kb
Host smart-f54d3c55-dee8-4570-8675-74eab13247cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174487987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.4174487987
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3448533447
Short name T563
Test name
Test status
Simulation time 118747320 ps
CPU time 0.73 seconds
Started Jul 07 05:45:28 PM PDT 24
Finished Jul 07 05:45:29 PM PDT 24
Peak memory 195532 kb
Host smart-b7cc6ab0-0d65-4973-8c36-35245fed6fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448533447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3448533447
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2436207626
Short name T204
Test name
Test status
Simulation time 1902677294 ps
CPU time 24.37 seconds
Started Jul 07 05:45:35 PM PDT 24
Finished Jul 07 05:46:00 PM PDT 24
Peak memory 197572 kb
Host smart-59430771-144d-4be1-b0e4-8188c1d481a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436207626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2436207626
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1809236960
Short name T132
Test name
Test status
Simulation time 101552448 ps
CPU time 0.96 seconds
Started Jul 07 05:45:35 PM PDT 24
Finished Jul 07 05:45:36 PM PDT 24
Peak memory 197500 kb
Host smart-bdf741aa-e1f6-4074-a80a-be9cedcb300d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809236960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1809236960
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1203799233
Short name T475
Test name
Test status
Simulation time 61377285 ps
CPU time 1.07 seconds
Started Jul 07 05:45:34 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 197512 kb
Host smart-e34dc057-63ef-4b27-9ba6-57d785cbdd87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203799233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1203799233
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3359831858
Short name T416
Test name
Test status
Simulation time 501100468 ps
CPU time 1.98 seconds
Started Jul 07 05:45:30 PM PDT 24
Finished Jul 07 05:45:32 PM PDT 24
Peak memory 198652 kb
Host smart-821abfbf-283e-487b-84f0-a318262591c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359831858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3359831858
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.816057349
Short name T545
Test name
Test status
Simulation time 119640976 ps
CPU time 1.99 seconds
Started Jul 07 05:45:32 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 196900 kb
Host smart-c0240aa3-5d3b-4bb3-a254-79a77be7434e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816057349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
816057349
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.205117321
Short name T205
Test name
Test status
Simulation time 686474702 ps
CPU time 1.33 seconds
Started Jul 07 05:45:32 PM PDT 24
Finished Jul 07 05:45:34 PM PDT 24
Peak memory 196544 kb
Host smart-e959f6ed-1c57-4b74-8a04-0d75f597e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205117321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.205117321
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1189206141
Short name T714
Test name
Test status
Simulation time 336292090 ps
CPU time 1.42 seconds
Started Jul 07 05:45:35 PM PDT 24
Finished Jul 07 05:45:36 PM PDT 24
Peak memory 198820 kb
Host smart-622ef6d1-ad4b-41a9-a3fb-5b341ffbc5a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189206141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1189206141
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2051986944
Short name T660
Test name
Test status
Simulation time 68472408 ps
CPU time 1.41 seconds
Started Jul 07 05:45:35 PM PDT 24
Finished Jul 07 05:45:37 PM PDT 24
Peak memory 198676 kb
Host smart-af5cc87b-f39a-465b-9b3a-d7f07a53a4d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051986944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2051986944
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.229931896
Short name T511
Test name
Test status
Simulation time 165233674 ps
CPU time 1.13 seconds
Started Jul 07 05:45:30 PM PDT 24
Finished Jul 07 05:45:32 PM PDT 24
Peak memory 196276 kb
Host smart-1200e401-a75f-4a44-94ed-a13948496ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229931896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.229931896
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3191193981
Short name T305
Test name
Test status
Simulation time 167781205 ps
CPU time 0.95 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:45:34 PM PDT 24
Peak memory 196216 kb
Host smart-9fb78a49-6b0c-42c8-a999-7951c7b9b820
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191193981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3191193981
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.474990947
Short name T410
Test name
Test status
Simulation time 39661645949 ps
CPU time 135.71 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:47:49 PM PDT 24
Peak memory 198808 kb
Host smart-074c2c13-41e2-46e0-a149-68640d4dd397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474990947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.474990947
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3943606325
Short name T513
Test name
Test status
Simulation time 23555826 ps
CPU time 0.57 seconds
Started Jul 07 05:45:35 PM PDT 24
Finished Jul 07 05:45:36 PM PDT 24
Peak memory 195380 kb
Host smart-e5e0148a-1d55-48c0-bc72-045e1aca8a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943606325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3943606325
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3942224926
Short name T679
Test name
Test status
Simulation time 256358370 ps
CPU time 0.94 seconds
Started Jul 07 05:45:37 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 196480 kb
Host smart-8d201914-b698-42ca-bb27-4f36be34ddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942224926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3942224926
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2792971722
Short name T615
Test name
Test status
Simulation time 5790301403 ps
CPU time 12.56 seconds
Started Jul 07 05:45:37 PM PDT 24
Finished Jul 07 05:45:50 PM PDT 24
Peak memory 197752 kb
Host smart-d43356f3-5181-41a9-857b-63bac85356a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792971722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2792971722
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2139640199
Short name T694
Test name
Test status
Simulation time 43692787 ps
CPU time 0.74 seconds
Started Jul 07 05:45:39 PM PDT 24
Finished Jul 07 05:45:40 PM PDT 24
Peak memory 195460 kb
Host smart-715c8e1c-25bd-4480-8cb4-1d8646616383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139640199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2139640199
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2994511793
Short name T168
Test name
Test status
Simulation time 283112151 ps
CPU time 1.14 seconds
Started Jul 07 05:45:40 PM PDT 24
Finished Jul 07 05:45:41 PM PDT 24
Peak memory 196636 kb
Host smart-e35d942b-826a-49dc-aa08-a3e771a55e9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994511793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2994511793
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1887641927
Short name T56
Test name
Test status
Simulation time 159911714 ps
CPU time 3.44 seconds
Started Jul 07 05:45:36 PM PDT 24
Finished Jul 07 05:45:40 PM PDT 24
Peak memory 198668 kb
Host smart-b03e0805-68ae-446a-a9fc-17181dc4fc16
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887641927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1887641927
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3142086010
Short name T135
Test name
Test status
Simulation time 85318613 ps
CPU time 1.28 seconds
Started Jul 07 05:45:42 PM PDT 24
Finished Jul 07 05:45:44 PM PDT 24
Peak memory 196344 kb
Host smart-1afae48d-db42-4d80-b996-00d7ecc230e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142086010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3142086010
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1414096211
Short name T207
Test name
Test status
Simulation time 84500436 ps
CPU time 0.98 seconds
Started Jul 07 05:45:36 PM PDT 24
Finished Jul 07 05:45:37 PM PDT 24
Peak memory 197408 kb
Host smart-d81c8ee0-8642-4436-a9cd-d6694f29eca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414096211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1414096211
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1920013107
Short name T453
Test name
Test status
Simulation time 114409224 ps
CPU time 1.3 seconds
Started Jul 07 05:45:33 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 197756 kb
Host smart-3f54d0a0-e177-47a2-b83f-7d6946fbf503
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920013107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1920013107
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2170862520
Short name T575
Test name
Test status
Simulation time 207787157 ps
CPU time 5.1 seconds
Started Jul 07 05:45:38 PM PDT 24
Finished Jul 07 05:45:43 PM PDT 24
Peak memory 198688 kb
Host smart-a8a2382c-5071-4d72-8bf9-7186c7cddbf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170862520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2170862520
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.751822348
Short name T325
Test name
Test status
Simulation time 352044950 ps
CPU time 1.51 seconds
Started Jul 07 05:45:36 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 196260 kb
Host smart-57348502-a423-46ba-8843-41a0a9de069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751822348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.751822348
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1167816737
Short name T647
Test name
Test status
Simulation time 66930707 ps
CPU time 1.13 seconds
Started Jul 07 05:45:34 PM PDT 24
Finished Jul 07 05:45:35 PM PDT 24
Peak memory 196184 kb
Host smart-c8b7a910-8877-4461-a8e7-d418987c9057
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167816737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1167816737
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3751670254
Short name T677
Test name
Test status
Simulation time 2305738917 ps
CPU time 26.74 seconds
Started Jul 07 05:45:37 PM PDT 24
Finished Jul 07 05:46:04 PM PDT 24
Peak memory 198804 kb
Host smart-3f6fb649-53fc-4fe2-9442-af00ac5c8ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751670254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3751670254
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.3599073714
Short name T60
Test name
Test status
Simulation time 153832951784 ps
CPU time 1734.49 seconds
Started Jul 07 05:45:37 PM PDT 24
Finished Jul 07 06:14:32 PM PDT 24
Peak memory 198904 kb
Host smart-26c53480-7efa-4512-98cb-645361f998e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3599073714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.3599073714
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2186490314
Short name T264
Test name
Test status
Simulation time 13546867 ps
CPU time 0.63 seconds
Started Jul 07 05:44:19 PM PDT 24
Finished Jul 07 05:44:20 PM PDT 24
Peak memory 195364 kb
Host smart-a6cebb11-3ad6-44f8-9d11-f8f43027222a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186490314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2186490314
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2818913876
Short name T447
Test name
Test status
Simulation time 81618961 ps
CPU time 0.68 seconds
Started Jul 07 05:44:16 PM PDT 24
Finished Jul 07 05:44:17 PM PDT 24
Peak memory 194816 kb
Host smart-3af885b7-fd76-4899-976e-a4f539542ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818913876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2818913876
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.885239245
Short name T610
Test name
Test status
Simulation time 12436871320 ps
CPU time 18.4 seconds
Started Jul 07 05:44:24 PM PDT 24
Finished Jul 07 05:44:43 PM PDT 24
Peak memory 197532 kb
Host smart-cdc34710-ce27-47a2-85ec-1a52b1347f8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885239245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.885239245
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.994251067
Short name T370
Test name
Test status
Simulation time 73813878 ps
CPU time 1 seconds
Started Jul 07 05:44:18 PM PDT 24
Finished Jul 07 05:44:19 PM PDT 24
Peak memory 198912 kb
Host smart-99032adf-5134-42d3-aa22-2532e7a63a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994251067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.994251067
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2016147215
Short name T128
Test name
Test status
Simulation time 90707204 ps
CPU time 0.88 seconds
Started Jul 07 05:44:15 PM PDT 24
Finished Jul 07 05:44:16 PM PDT 24
Peak memory 196304 kb
Host smart-dbe540b9-3a51-4caf-a434-7d4c2323da83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016147215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2016147215
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3141128026
Short name T181
Test name
Test status
Simulation time 47472912 ps
CPU time 1.92 seconds
Started Jul 07 05:44:19 PM PDT 24
Finished Jul 07 05:44:21 PM PDT 24
Peak memory 198420 kb
Host smart-62636dd4-f2a8-4c36-ac75-ac2556b6b24a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141128026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3141128026
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1048567723
Short name T507
Test name
Test status
Simulation time 93117357 ps
CPU time 2.17 seconds
Started Jul 07 05:44:22 PM PDT 24
Finished Jul 07 05:44:25 PM PDT 24
Peak memory 197784 kb
Host smart-246ad8e8-c945-4d03-b473-e399ecd544e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048567723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1048567723
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4147176284
Short name T504
Test name
Test status
Simulation time 330207454 ps
CPU time 1.15 seconds
Started Jul 07 05:44:14 PM PDT 24
Finished Jul 07 05:44:16 PM PDT 24
Peak memory 196588 kb
Host smart-cb6663c7-3e03-42c8-a108-8263e77577f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147176284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4147176284
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.7759021
Short name T153
Test name
Test status
Simulation time 84910705 ps
CPU time 0.84 seconds
Started Jul 07 05:44:22 PM PDT 24
Finished Jul 07 05:44:23 PM PDT 24
Peak memory 196156 kb
Host smart-f93ff484-b55f-4028-a8ae-11f70401126e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7759021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_pu
lldown.7759021
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3817369809
Short name T288
Test name
Test status
Simulation time 733166567 ps
CPU time 3.93 seconds
Started Jul 07 05:44:21 PM PDT 24
Finished Jul 07 05:44:25 PM PDT 24
Peak memory 198616 kb
Host smart-5f50c9ab-594e-422a-aac2-9775a8ecbf65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817369809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3817369809
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3406579439
Short name T37
Test name
Test status
Simulation time 597528709 ps
CPU time 0.93 seconds
Started Jul 07 05:44:23 PM PDT 24
Finished Jul 07 05:44:25 PM PDT 24
Peak memory 215184 kb
Host smart-69e7b6d1-8dab-4bdd-ade5-c6e5d782355e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406579439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3406579439
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1088172996
Short name T361
Test name
Test status
Simulation time 85605200 ps
CPU time 0.88 seconds
Started Jul 07 05:44:15 PM PDT 24
Finished Jul 07 05:44:16 PM PDT 24
Peak memory 196004 kb
Host smart-2af62ef2-415b-412e-af5b-688f1f1eda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088172996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1088172996
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2052377101
Short name T602
Test name
Test status
Simulation time 105396437 ps
CPU time 1.1 seconds
Started Jul 07 05:44:15 PM PDT 24
Finished Jul 07 05:44:16 PM PDT 24
Peak memory 196224 kb
Host smart-1b1ddb11-97bc-4a95-8714-d24c894b1794
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052377101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2052377101
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1706744768
Short name T644
Test name
Test status
Simulation time 5242842844 ps
CPU time 151.25 seconds
Started Jul 07 05:44:22 PM PDT 24
Finished Jul 07 05:46:54 PM PDT 24
Peak memory 198824 kb
Host smart-2cf16f3a-3620-47d2-8d72-ea373c636282
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706744768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1706744768
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3407170789
Short name T203
Test name
Test status
Simulation time 87912622 ps
CPU time 0.58 seconds
Started Jul 07 05:45:45 PM PDT 24
Finished Jul 07 05:45:45 PM PDT 24
Peak memory 195316 kb
Host smart-d69a6501-cbe1-4814-bf57-9d4a865050d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407170789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3407170789
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.703721675
Short name T198
Test name
Test status
Simulation time 57906985 ps
CPU time 0.89 seconds
Started Jul 07 05:45:40 PM PDT 24
Finished Jul 07 05:45:41 PM PDT 24
Peak memory 196700 kb
Host smart-6e3629a8-a794-4909-9b60-1e66944e2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703721675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.703721675
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2407883416
Short name T294
Test name
Test status
Simulation time 2849873445 ps
CPU time 23.54 seconds
Started Jul 07 05:45:40 PM PDT 24
Finished Jul 07 05:46:04 PM PDT 24
Peak memory 197556 kb
Host smart-b24b14d5-09e3-4f4d-9131-da031833aad5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407883416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2407883416
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3565484900
Short name T254
Test name
Test status
Simulation time 866849498 ps
CPU time 0.99 seconds
Started Jul 07 05:45:42 PM PDT 24
Finished Jul 07 05:45:44 PM PDT 24
Peak memory 197104 kb
Host smart-747561ca-09f8-448b-863e-26cd13eb0712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565484900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3565484900
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.874945038
Short name T367
Test name
Test status
Simulation time 301715334 ps
CPU time 1.21 seconds
Started Jul 07 05:45:38 PM PDT 24
Finished Jul 07 05:45:40 PM PDT 24
Peak memory 196464 kb
Host smart-48c2fa03-fce0-4e82-8492-af42853f4ec9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874945038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.874945038
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2015134591
Short name T691
Test name
Test status
Simulation time 135062669 ps
CPU time 2.37 seconds
Started Jul 07 05:45:40 PM PDT 24
Finished Jul 07 05:45:43 PM PDT 24
Peak memory 198764 kb
Host smart-6238ac2c-9c4c-49fa-a51e-1b87c53ffcb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015134591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2015134591
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3191175330
Short name T297
Test name
Test status
Simulation time 126232824 ps
CPU time 2.59 seconds
Started Jul 07 05:45:39 PM PDT 24
Finished Jul 07 05:45:42 PM PDT 24
Peak memory 198756 kb
Host smart-d8289ec7-2111-410f-9aec-5521ec251fc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191175330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3191175330
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4173045265
Short name T124
Test name
Test status
Simulation time 72014080 ps
CPU time 0.89 seconds
Started Jul 07 05:45:36 PM PDT 24
Finished Jul 07 05:45:37 PM PDT 24
Peak memory 197192 kb
Host smart-0d61428d-e6b3-4479-a97d-9772782dae20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173045265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4173045265
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3213563259
Short name T479
Test name
Test status
Simulation time 83543588 ps
CPU time 1.04 seconds
Started Jul 07 05:45:37 PM PDT 24
Finished Jul 07 05:45:38 PM PDT 24
Peak memory 196620 kb
Host smart-75891044-328f-449c-8bfb-e225c4a4e01a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213563259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3213563259
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3073135337
Short name T561
Test name
Test status
Simulation time 64305118 ps
CPU time 2.88 seconds
Started Jul 07 05:45:43 PM PDT 24
Finished Jul 07 05:45:47 PM PDT 24
Peak memory 198588 kb
Host smart-6df361c4-45a2-464d-93f2-6f421a941aa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073135337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3073135337
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.248082504
Short name T422
Test name
Test status
Simulation time 82498908 ps
CPU time 0.97 seconds
Started Jul 07 05:45:41 PM PDT 24
Finished Jul 07 05:45:42 PM PDT 24
Peak memory 197116 kb
Host smart-16f732c9-158d-4645-9dc2-5e7de98feb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248082504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.248082504
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.777944236
Short name T470
Test name
Test status
Simulation time 144046519 ps
CPU time 0.88 seconds
Started Jul 07 05:45:39 PM PDT 24
Finished Jul 07 05:45:40 PM PDT 24
Peak memory 196900 kb
Host smart-f4747339-c0fd-4291-9964-6cbb49800d70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777944236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.777944236
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1960214648
Short name T540
Test name
Test status
Simulation time 22100559450 ps
CPU time 137.24 seconds
Started Jul 07 05:45:42 PM PDT 24
Finished Jul 07 05:48:00 PM PDT 24
Peak memory 198776 kb
Host smart-2ea66a9e-e42d-436a-93a8-ff0a74b68899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960214648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1960214648
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3211603429
Short name T299
Test name
Test status
Simulation time 45809909 ps
CPU time 0.6 seconds
Started Jul 07 05:45:44 PM PDT 24
Finished Jul 07 05:45:45 PM PDT 24
Peak memory 195372 kb
Host smart-50e488e6-d8cc-4675-a1cd-98a69ff6d303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211603429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3211603429
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.33996451
Short name T246
Test name
Test status
Simulation time 148737411 ps
CPU time 0.9 seconds
Started Jul 07 05:45:47 PM PDT 24
Finished Jul 07 05:45:48 PM PDT 24
Peak memory 197032 kb
Host smart-6ec5aeef-6251-4b7d-a091-4e7ce56904db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33996451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.33996451
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2658826959
Short name T680
Test name
Test status
Simulation time 6309548621 ps
CPU time 17.26 seconds
Started Jul 07 05:45:49 PM PDT 24
Finished Jul 07 05:46:06 PM PDT 24
Peak memory 197560 kb
Host smart-960d0202-230b-4e27-85ef-1018c4c071bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658826959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2658826959
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2875702469
Short name T661
Test name
Test status
Simulation time 22611058 ps
CPU time 0.64 seconds
Started Jul 07 05:45:44 PM PDT 24
Finished Jul 07 05:45:45 PM PDT 24
Peak memory 195136 kb
Host smart-9318f58f-ac41-4b57-a252-116b8f191c5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875702469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2875702469
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3145326778
Short name T493
Test name
Test status
Simulation time 39700518 ps
CPU time 0.91 seconds
Started Jul 07 05:45:47 PM PDT 24
Finished Jul 07 05:45:48 PM PDT 24
Peak memory 197412 kb
Host smart-769c6172-916a-4686-83fd-1ffd4cb0b0ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145326778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3145326778
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2949677796
Short name T167
Test name
Test status
Simulation time 61698952 ps
CPU time 2.49 seconds
Started Jul 07 05:45:48 PM PDT 24
Finished Jul 07 05:45:51 PM PDT 24
Peak memory 197216 kb
Host smart-a270b95b-ebc3-4001-ba24-8505ecda28b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949677796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2949677796
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2640832724
Short name T148
Test name
Test status
Simulation time 231303532 ps
CPU time 2.3 seconds
Started Jul 07 05:45:47 PM PDT 24
Finished Jul 07 05:45:50 PM PDT 24
Peak memory 198764 kb
Host smart-b26e7689-b1c1-4e91-a449-4d08863ba31e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640832724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2640832724
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1910490620
Short name T191
Test name
Test status
Simulation time 122524168 ps
CPU time 0.8 seconds
Started Jul 07 05:45:41 PM PDT 24
Finished Jul 07 05:45:42 PM PDT 24
Peak memory 196920 kb
Host smart-6a693639-f7d0-477d-a51a-66495c2ea6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910490620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1910490620
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3340857571
Short name T146
Test name
Test status
Simulation time 62649737 ps
CPU time 0.75 seconds
Started Jul 07 05:45:42 PM PDT 24
Finished Jul 07 05:45:44 PM PDT 24
Peak memory 195928 kb
Host smart-53118ba5-a3f5-46b3-bdd1-4c3acb3edb3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340857571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3340857571
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4152997067
Short name T363
Test name
Test status
Simulation time 565281478 ps
CPU time 2.06 seconds
Started Jul 07 05:45:43 PM PDT 24
Finished Jul 07 05:45:46 PM PDT 24
Peak memory 198688 kb
Host smart-26b73be5-3860-44d2-9348-12eb7c58dd57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152997067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4152997067
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.45197196
Short name T515
Test name
Test status
Simulation time 232364887 ps
CPU time 0.99 seconds
Started Jul 07 05:45:44 PM PDT 24
Finished Jul 07 05:45:46 PM PDT 24
Peak memory 196860 kb
Host smart-79c566f5-7bee-445d-9244-f963a976a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45197196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.45197196
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3581668624
Short name T159
Test name
Test status
Simulation time 106750000 ps
CPU time 1.14 seconds
Started Jul 07 05:45:42 PM PDT 24
Finished Jul 07 05:45:43 PM PDT 24
Peak memory 196520 kb
Host smart-4f6079f5-28aa-48ef-b60a-259aba4ec296
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581668624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3581668624
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1077806931
Short name T253
Test name
Test status
Simulation time 6355538155 ps
CPU time 160.78 seconds
Started Jul 07 05:45:46 PM PDT 24
Finished Jul 07 05:48:27 PM PDT 24
Peak memory 198788 kb
Host smart-edd53df5-821c-49f7-aece-f716f3843e41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077806931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1077806931
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.648342395
Short name T690
Test name
Test status
Simulation time 16947528489 ps
CPU time 192.41 seconds
Started Jul 07 05:45:44 PM PDT 24
Finished Jul 07 05:48:57 PM PDT 24
Peak memory 198868 kb
Host smart-77697a65-0797-48ae-9923-93d71047c0b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=648342395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.648342395
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.234942961
Short name T528
Test name
Test status
Simulation time 10855458 ps
CPU time 0.6 seconds
Started Jul 07 05:45:48 PM PDT 24
Finished Jul 07 05:45:49 PM PDT 24
Peak memory 194596 kb
Host smart-53527ea2-b9be-4bec-a8c3-5a7354cc32dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234942961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.234942961
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.4115247724
Short name T451
Test name
Test status
Simulation time 64390634 ps
CPU time 0.92 seconds
Started Jul 07 05:45:50 PM PDT 24
Finished Jul 07 05:45:51 PM PDT 24
Peak memory 197240 kb
Host smart-19bed979-3142-4b61-8883-18f6b7fb775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115247724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.4115247724
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.371717196
Short name T365
Test name
Test status
Simulation time 2604785045 ps
CPU time 26.48 seconds
Started Jul 07 05:45:47 PM PDT 24
Finished Jul 07 05:46:13 PM PDT 24
Peak memory 197564 kb
Host smart-9ed25a42-662e-4b46-afda-6148eece1db1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371717196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.371717196
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1288226334
Short name T239
Test name
Test status
Simulation time 172453775 ps
CPU time 0.73 seconds
Started Jul 07 05:45:48 PM PDT 24
Finished Jul 07 05:45:49 PM PDT 24
Peak memory 197192 kb
Host smart-6a33246f-30ec-4910-bdd0-94a3e03f0261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288226334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1288226334
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2686299431
Short name T412
Test name
Test status
Simulation time 85661055 ps
CPU time 0.75 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:53 PM PDT 24
Peak memory 196188 kb
Host smart-e91aab6b-fa88-4fb8-8caf-5f57d35ccbcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686299431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2686299431
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3530399212
Short name T599
Test name
Test status
Simulation time 33889473 ps
CPU time 1.38 seconds
Started Jul 07 05:45:50 PM PDT 24
Finished Jul 07 05:45:52 PM PDT 24
Peak memory 197492 kb
Host smart-bb0a5ee5-b24b-43c8-8db2-38895dd7a769
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530399212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3530399212
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.782413542
Short name T548
Test name
Test status
Simulation time 643372100 ps
CPU time 3.22 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:55 PM PDT 24
Peak memory 196552 kb
Host smart-13451597-cf9b-4bba-969e-e996bb08e869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782413542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
782413542
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1846127796
Short name T275
Test name
Test status
Simulation time 118024675 ps
CPU time 1.22 seconds
Started Jul 07 05:45:46 PM PDT 24
Finished Jul 07 05:45:47 PM PDT 24
Peak memory 197780 kb
Host smart-ff0fdbb1-1549-4c56-9ee4-93c8ebfaac95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846127796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1846127796
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.445211225
Short name T520
Test name
Test status
Simulation time 59609567 ps
CPU time 0.71 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:53 PM PDT 24
Peak memory 195024 kb
Host smart-bcf04a03-5ec8-447f-a1dd-397e145bf52d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445211225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.445211225
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4198199801
Short name T341
Test name
Test status
Simulation time 31014730 ps
CPU time 1.35 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:53 PM PDT 24
Peak memory 198692 kb
Host smart-2ebe974d-8329-4f58-9d7d-4f853110a480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198199801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4198199801
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3890043960
Short name T390
Test name
Test status
Simulation time 1169225647 ps
CPU time 1.29 seconds
Started Jul 07 05:45:46 PM PDT 24
Finished Jul 07 05:45:47 PM PDT 24
Peak memory 196280 kb
Host smart-9bc7b165-ff2b-428a-829f-a4c96d827868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890043960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3890043960
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2577209011
Short name T676
Test name
Test status
Simulation time 208719417 ps
CPU time 1.06 seconds
Started Jul 07 05:45:46 PM PDT 24
Finished Jul 07 05:45:48 PM PDT 24
Peak memory 197080 kb
Host smart-fbe5d2c0-4fc8-41b5-938d-3a5b4ef5c569
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577209011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2577209011
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2404733123
Short name T306
Test name
Test status
Simulation time 4010605377 ps
CPU time 109.24 seconds
Started Jul 07 05:45:48 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 198740 kb
Host smart-b5ac1c60-f557-4575-9456-996343810013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404733123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2404733123
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.327237537
Short name T58
Test name
Test status
Simulation time 343623941443 ps
CPU time 1832.08 seconds
Started Jul 07 05:45:49 PM PDT 24
Finished Jul 07 06:16:22 PM PDT 24
Peak memory 198952 kb
Host smart-0d68d14a-738c-417a-a2f7-c546ff046cb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=327237537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.327237537
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3416394497
Short name T324
Test name
Test status
Simulation time 18245149 ps
CPU time 0.54 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:52 PM PDT 24
Peak memory 195376 kb
Host smart-125e69f1-c52f-4beb-8fa8-e482b4106710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416394497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3416394497
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2630755452
Short name T109
Test name
Test status
Simulation time 27547998 ps
CPU time 0.75 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:53 PM PDT 24
Peak memory 195944 kb
Host smart-5e96d2fd-0382-47a2-8e06-8f2a8c2a7c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630755452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2630755452
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.873227648
Short name T576
Test name
Test status
Simulation time 1613166428 ps
CPU time 21.6 seconds
Started Jul 07 05:45:52 PM PDT 24
Finished Jul 07 05:46:14 PM PDT 24
Peak memory 198940 kb
Host smart-c28cb53b-fcbd-409f-8293-211ade24e652
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873227648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.873227648
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.344153578
Short name T51
Test name
Test status
Simulation time 94901251 ps
CPU time 0.92 seconds
Started Jul 07 05:45:55 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 198528 kb
Host smart-599ce7c0-abff-41b2-828f-9ae5d879ddf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344153578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.344153578
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1801948221
Short name T245
Test name
Test status
Simulation time 450597306 ps
CPU time 1.5 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:54 PM PDT 24
Peak memory 197244 kb
Host smart-8c019262-8373-4c25-99b1-0291ba1a1ee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801948221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1801948221
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1100312349
Short name T678
Test name
Test status
Simulation time 38422637 ps
CPU time 1.59 seconds
Started Jul 07 05:45:54 PM PDT 24
Finished Jul 07 05:45:56 PM PDT 24
Peak memory 197252 kb
Host smart-0f7f6ff4-89e4-4930-9bc2-b08fab7783bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100312349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1100312349
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4098541658
Short name T559
Test name
Test status
Simulation time 214110635 ps
CPU time 3.41 seconds
Started Jul 07 05:45:52 PM PDT 24
Finished Jul 07 05:45:56 PM PDT 24
Peak memory 197688 kb
Host smart-8053e7ec-2878-4bc1-996b-8235f428991d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098541658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4098541658
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1508875836
Short name T160
Test name
Test status
Simulation time 141978004 ps
CPU time 1.35 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 05:45:53 PM PDT 24
Peak memory 196508 kb
Host smart-ecf26271-db5e-4ef9-adca-f495fdc950b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508875836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1508875836
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2209888634
Short name T247
Test name
Test status
Simulation time 305781756 ps
CPU time 1.42 seconds
Started Jul 07 05:45:54 PM PDT 24
Finished Jul 07 05:45:56 PM PDT 24
Peak memory 197712 kb
Host smart-b4bd755c-8726-4fea-b8b9-698733e02a92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209888634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2209888634
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1657638720
Short name T49
Test name
Test status
Simulation time 110499435 ps
CPU time 2.05 seconds
Started Jul 07 05:45:54 PM PDT 24
Finished Jul 07 05:45:56 PM PDT 24
Peak memory 198616 kb
Host smart-d32e00b7-0cbb-4aea-b0d3-f4b2a492e18f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657638720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1657638720
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3863555528
Short name T354
Test name
Test status
Simulation time 65063228 ps
CPU time 1.13 seconds
Started Jul 07 05:45:49 PM PDT 24
Finished Jul 07 05:45:50 PM PDT 24
Peak memory 196440 kb
Host smart-bdafea47-12b9-4975-b259-4bc552b8a9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863555528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3863555528
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1813225293
Short name T436
Test name
Test status
Simulation time 44206735 ps
CPU time 1.33 seconds
Started Jul 07 05:45:48 PM PDT 24
Finished Jul 07 05:45:49 PM PDT 24
Peak memory 196360 kb
Host smart-41411965-2683-4b95-ba44-0808816aae8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813225293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1813225293
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2508247229
Short name T15
Test name
Test status
Simulation time 9049989903 ps
CPU time 33.49 seconds
Started Jul 07 05:45:55 PM PDT 24
Finished Jul 07 05:46:29 PM PDT 24
Peak memory 198796 kb
Host smart-71a9d4b8-b11e-4a9e-9bd1-a122b95509fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508247229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2508247229
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2681872359
Short name T61
Test name
Test status
Simulation time 62346657404 ps
CPU time 1113.16 seconds
Started Jul 07 05:45:51 PM PDT 24
Finished Jul 07 06:04:25 PM PDT 24
Peak memory 198992 kb
Host smart-02abdd7d-ca51-484a-a883-0839191027f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2681872359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2681872359
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2384355416
Short name T364
Test name
Test status
Simulation time 37463875 ps
CPU time 0.59 seconds
Started Jul 07 05:46:02 PM PDT 24
Finished Jul 07 05:46:03 PM PDT 24
Peak memory 195384 kb
Host smart-47227a02-c180-49fc-923e-f896f7efb819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384355416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2384355416
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.497074236
Short name T654
Test name
Test status
Simulation time 53976230 ps
CPU time 0.92 seconds
Started Jul 07 05:45:56 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 196400 kb
Host smart-6c875bbf-ad5c-4076-a914-792e0c91f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497074236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.497074236
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3931948765
Short name T337
Test name
Test status
Simulation time 2468032852 ps
CPU time 12.33 seconds
Started Jul 07 05:45:57 PM PDT 24
Finished Jul 07 05:46:10 PM PDT 24
Peak memory 198788 kb
Host smart-135590c7-5e45-4a73-aae7-853372d7d9d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931948765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3931948765
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2126623243
Short name T498
Test name
Test status
Simulation time 88222582 ps
CPU time 0.8 seconds
Started Jul 07 05:45:56 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 197156 kb
Host smart-942a75bd-0940-46ad-8e99-2b573bffb515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126623243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2126623243
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1920442095
Short name T94
Test name
Test status
Simulation time 56490764 ps
CPU time 0.7 seconds
Started Jul 07 05:45:56 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 194924 kb
Host smart-5b26a7b9-229c-4bd3-a03f-2fbde97acdaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920442095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1920442095
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1700759593
Short name T664
Test name
Test status
Simulation time 27651176 ps
CPU time 1.14 seconds
Started Jul 07 05:45:56 PM PDT 24
Finished Jul 07 05:45:58 PM PDT 24
Peak memory 198152 kb
Host smart-7c493ca2-1d00-4b40-b892-bdd83ec7ec1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700759593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1700759593
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1398891589
Short name T165
Test name
Test status
Simulation time 618355095 ps
CPU time 3.26 seconds
Started Jul 07 05:45:58 PM PDT 24
Finished Jul 07 05:46:02 PM PDT 24
Peak memory 198760 kb
Host smart-769555fe-0b74-49a7-aea0-da49575d2800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398891589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1398891589
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2302340669
Short name T699
Test name
Test status
Simulation time 220033693 ps
CPU time 1.29 seconds
Started Jul 07 05:45:58 PM PDT 24
Finished Jul 07 05:45:59 PM PDT 24
Peak memory 197244 kb
Host smart-d05cbd62-9cc3-44e3-bf46-b323bb2278e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302340669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2302340669
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3273003006
Short name T127
Test name
Test status
Simulation time 21716587 ps
CPU time 0.92 seconds
Started Jul 07 05:45:57 PM PDT 24
Finished Jul 07 05:45:58 PM PDT 24
Peak memory 196676 kb
Host smart-665a22c7-45a9-4115-bb05-1adec1a3fc3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273003006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3273003006
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.122063385
Short name T474
Test name
Test status
Simulation time 516134727 ps
CPU time 6.28 seconds
Started Jul 07 05:45:55 PM PDT 24
Finished Jul 07 05:46:02 PM PDT 24
Peak memory 198664 kb
Host smart-4dca426b-ab59-4e8c-bac3-0090098858bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122063385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.122063385
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.972322305
Short name T328
Test name
Test status
Simulation time 37855326 ps
CPU time 0.77 seconds
Started Jul 07 05:45:56 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 195864 kb
Host smart-334a5e47-e19b-4d94-a7f7-c6d42c54c9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972322305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.972322305
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1692675933
Short name T54
Test name
Test status
Simulation time 98753729 ps
CPU time 1.15 seconds
Started Jul 07 05:45:56 PM PDT 24
Finished Jul 07 05:45:57 PM PDT 24
Peak memory 197132 kb
Host smart-3b298b34-a3d5-4146-bb64-c5dc41a5d149
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692675933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1692675933
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1014717567
Short name T570
Test name
Test status
Simulation time 2730167102 ps
CPU time 28.63 seconds
Started Jul 07 05:45:58 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 198820 kb
Host smart-6bcde6a3-8cfe-42c6-b877-e0042480d25a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014717567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1014717567
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.743411066
Short name T512
Test name
Test status
Simulation time 72629419 ps
CPU time 1.01 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 197420 kb
Host smart-c624a291-57de-495e-91d4-f5dd1ba1ac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743411066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.743411066
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.315919143
Short name T404
Test name
Test status
Simulation time 245607370 ps
CPU time 13.18 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:16 PM PDT 24
Peak memory 197420 kb
Host smart-ae45c616-4899-499f-825c-496ed9fa17d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315919143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.315919143
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3536165029
Short name T377
Test name
Test status
Simulation time 256360262 ps
CPU time 0.74 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:07 PM PDT 24
Peak memory 195436 kb
Host smart-67b8bb04-037a-4804-8c8e-1fc9f89eb971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536165029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3536165029
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.582277113
Short name T139
Test name
Test status
Simulation time 246566848 ps
CPU time 1.26 seconds
Started Jul 07 05:45:59 PM PDT 24
Finished Jul 07 05:46:01 PM PDT 24
Peak memory 196836 kb
Host smart-554847bb-0f3c-458b-86bc-fac97fcd0dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582277113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.582277113
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1520403188
Short name T194
Test name
Test status
Simulation time 208287490 ps
CPU time 2.56 seconds
Started Jul 07 05:46:02 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 198688 kb
Host smart-677320f8-6f84-4350-8214-3e5809544e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520403188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1520403188
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.221523983
Short name T169
Test name
Test status
Simulation time 59491554 ps
CPU time 0.7 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:03 PM PDT 24
Peak memory 194788 kb
Host smart-3a2f1ff5-c520-4f86-8f1e-c2edc4372de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221523983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.221523983
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1479972523
Short name T523
Test name
Test status
Simulation time 78133954 ps
CPU time 1.31 seconds
Started Jul 07 05:46:04 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 197580 kb
Host smart-89af03b3-6774-48fa-b5ae-14e77dccf747
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479972523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1479972523
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.594585583
Short name T537
Test name
Test status
Simulation time 813327765 ps
CPU time 4.79 seconds
Started Jul 07 05:46:00 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 198664 kb
Host smart-beaed017-684e-4cbf-b86f-92c9204935e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594585583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.594585583
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2887651550
Short name T586
Test name
Test status
Simulation time 206488594 ps
CPU time 1.06 seconds
Started Jul 07 05:45:59 PM PDT 24
Finished Jul 07 05:46:00 PM PDT 24
Peak memory 196340 kb
Host smart-f71b6b57-03d3-42f0-9ddb-21f457149ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887651550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2887651550
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2095784116
Short name T157
Test name
Test status
Simulation time 736805737 ps
CPU time 1.49 seconds
Started Jul 07 05:45:58 PM PDT 24
Finished Jul 07 05:46:00 PM PDT 24
Peak memory 197536 kb
Host smart-5af0c9cb-00be-4da5-8b79-95defc058e6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095784116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2095784116
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3099457444
Short name T333
Test name
Test status
Simulation time 163865802542 ps
CPU time 152.75 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:48:36 PM PDT 24
Peak memory 198748 kb
Host smart-e5e02fb0-7c87-4ba7-9dd4-a3afad3c6b9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099457444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3099457444
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3359196105
Short name T268
Test name
Test status
Simulation time 29059462 ps
CPU time 0.54 seconds
Started Jul 07 05:46:07 PM PDT 24
Finished Jul 07 05:46:08 PM PDT 24
Peak memory 194672 kb
Host smart-f1363326-44b0-4b05-8962-d52f591b326b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359196105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3359196105
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1692856856
Short name T282
Test name
Test status
Simulation time 31207405 ps
CPU time 0.72 seconds
Started Jul 07 05:46:05 PM PDT 24
Finished Jul 07 05:46:06 PM PDT 24
Peak memory 196652 kb
Host smart-e7872043-f5dd-4956-90e7-deaf76b6c700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692856856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1692856856
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2667029449
Short name T620
Test name
Test status
Simulation time 261628582 ps
CPU time 13.69 seconds
Started Jul 07 05:46:02 PM PDT 24
Finished Jul 07 05:46:16 PM PDT 24
Peak memory 196952 kb
Host smart-6c9777ec-b320-4c22-87c6-4770d7980259
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667029449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2667029449
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.518422343
Short name T357
Test name
Test status
Simulation time 64193210 ps
CPU time 0.93 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 196596 kb
Host smart-d0841050-6a20-497c-b347-81067257e17e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518422343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.518422343
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3009733081
Short name T134
Test name
Test status
Simulation time 105170119 ps
CPU time 0.97 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 196500 kb
Host smart-c4a07dbe-e88c-4997-b97d-b0a62aa5bd9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009733081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3009733081
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1586045566
Short name T266
Test name
Test status
Simulation time 376849156 ps
CPU time 3.4 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:10 PM PDT 24
Peak memory 198688 kb
Host smart-059b1c2f-5b7c-49d3-a9f0-d5777e35cc36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586045566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1586045566
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2194449018
Short name T183
Test name
Test status
Simulation time 175732044 ps
CPU time 2.1 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 197204 kb
Host smart-ab819c92-e40b-4140-85f0-692465817e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194449018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2194449018
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1195379015
Short name T552
Test name
Test status
Simulation time 268977218 ps
CPU time 1.4 seconds
Started Jul 07 05:45:59 PM PDT 24
Finished Jul 07 05:46:01 PM PDT 24
Peak memory 197244 kb
Host smart-f0bfc45a-801e-41b1-b659-37fadff59d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195379015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1195379015
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3622722678
Short name T242
Test name
Test status
Simulation time 27984550 ps
CPU time 1.05 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:08 PM PDT 24
Peak memory 196720 kb
Host smart-5e6025fa-5d4f-4fe9-8d6e-2dde8e3e7858
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622722678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3622722678
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1088094572
Short name T350
Test name
Test status
Simulation time 332826274 ps
CPU time 5.66 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:09 PM PDT 24
Peak memory 198936 kb
Host smart-3f383f22-f24c-42a5-9e9f-3c4f135202b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088094572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1088094572
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1983289737
Short name T532
Test name
Test status
Simulation time 81302145 ps
CPU time 1.15 seconds
Started Jul 07 05:46:03 PM PDT 24
Finished Jul 07 05:46:05 PM PDT 24
Peak memory 197168 kb
Host smart-14a9fc32-c556-4680-ab9a-5ff3efaac047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983289737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1983289737
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2699004825
Short name T455
Test name
Test status
Simulation time 167817946 ps
CPU time 1.16 seconds
Started Jul 07 05:45:57 PM PDT 24
Finished Jul 07 05:45:59 PM PDT 24
Peak memory 196228 kb
Host smart-2d49fc55-bbe2-40fd-86cc-4f0ac9608435
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699004825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2699004825
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.688675105
Short name T9
Test name
Test status
Simulation time 8097958716 ps
CPU time 87.71 seconds
Started Jul 07 05:46:01 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 198812 kb
Host smart-145a9823-3df2-4e09-8f3b-53fb246c6842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688675105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.688675105
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3627932042
Short name T162
Test name
Test status
Simulation time 18795879 ps
CPU time 0.61 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:07 PM PDT 24
Peak memory 194668 kb
Host smart-6ab66ab2-01ce-449f-ba70-31e0465a5263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627932042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3627932042
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2919642121
Short name T211
Test name
Test status
Simulation time 38268864 ps
CPU time 0.82 seconds
Started Jul 07 05:46:12 PM PDT 24
Finished Jul 07 05:46:14 PM PDT 24
Peak memory 196564 kb
Host smart-9b487a4c-c070-48d8-8379-7d26fa56f469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919642121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2919642121
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.889358788
Short name T635
Test name
Test status
Simulation time 2267518615 ps
CPU time 20.79 seconds
Started Jul 07 05:46:10 PM PDT 24
Finished Jul 07 05:46:32 PM PDT 24
Peak memory 198740 kb
Host smart-eff843cc-fd26-405a-8883-fec40004a838
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889358788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.889358788
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2009341162
Short name T543
Test name
Test status
Simulation time 46427103 ps
CPU time 0.8 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:07 PM PDT 24
Peak memory 196580 kb
Host smart-91ef8349-f30c-450e-80bf-9dba58a1e4ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009341162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2009341162
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1048028140
Short name T401
Test name
Test status
Simulation time 62438493 ps
CPU time 1.19 seconds
Started Jul 07 05:46:07 PM PDT 24
Finished Jul 07 05:46:09 PM PDT 24
Peak memory 196856 kb
Host smart-64756dd4-123a-4959-a039-eaa69a5d34ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048028140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1048028140
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1083233660
Short name T138
Test name
Test status
Simulation time 115967291 ps
CPU time 3.12 seconds
Started Jul 07 05:46:09 PM PDT 24
Finished Jul 07 05:46:12 PM PDT 24
Peak memory 196956 kb
Host smart-a0dcd243-804f-4e91-b7ec-070247c8e651
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083233660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1083233660
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3391977913
Short name T463
Test name
Test status
Simulation time 44716365 ps
CPU time 0.98 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:07 PM PDT 24
Peak memory 197172 kb
Host smart-00fdd825-1fd6-4865-8610-a7f841344ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391977913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3391977913
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3519199902
Short name T419
Test name
Test status
Simulation time 323966984 ps
CPU time 0.81 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:07 PM PDT 24
Peak memory 196072 kb
Host smart-99629cb2-c1c8-4cd1-8c37-7f36ab502706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519199902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3519199902
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1427202599
Short name T605
Test name
Test status
Simulation time 57811093 ps
CPU time 0.86 seconds
Started Jul 07 05:46:09 PM PDT 24
Finished Jul 07 05:46:11 PM PDT 24
Peak memory 198088 kb
Host smart-755462a8-563a-44e3-bdc0-4cda32ea7f5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427202599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1427202599
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.545125638
Short name T490
Test name
Test status
Simulation time 658810223 ps
CPU time 3.14 seconds
Started Jul 07 05:46:13 PM PDT 24
Finished Jul 07 05:46:16 PM PDT 24
Peak memory 198640 kb
Host smart-84a3b204-a9f5-48c2-84a6-3d60c103a335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545125638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.545125638
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2548464292
Short name T172
Test name
Test status
Simulation time 204477765 ps
CPU time 1.16 seconds
Started Jul 07 05:46:02 PM PDT 24
Finished Jul 07 05:46:03 PM PDT 24
Peak memory 196236 kb
Host smart-1ecf8803-0d46-4b45-9395-453db572c3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548464292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2548464292
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2118905978
Short name T220
Test name
Test status
Simulation time 186112205 ps
CPU time 1.02 seconds
Started Jul 07 05:46:11 PM PDT 24
Finished Jul 07 05:46:13 PM PDT 24
Peak memory 196336 kb
Host smart-ac7508db-c04d-4c7d-b558-3a0e024c76d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118905978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2118905978
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3494221000
Short name T4
Test name
Test status
Simulation time 13397467759 ps
CPU time 164.16 seconds
Started Jul 07 05:46:08 PM PDT 24
Finished Jul 07 05:48:52 PM PDT 24
Peak memory 198688 kb
Host smart-86a61aa3-b21c-4835-a8a0-9a84b763d3cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494221000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3494221000
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.78780739
Short name T14
Test name
Test status
Simulation time 323044055330 ps
CPU time 2603.57 seconds
Started Jul 07 05:46:08 PM PDT 24
Finished Jul 07 06:29:32 PM PDT 24
Peak memory 198904 kb
Host smart-78ae7b51-3a77-4411-bda7-9a27d76ffc4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=78780739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.78780739
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1046335450
Short name T39
Test name
Test status
Simulation time 56666626 ps
CPU time 0.57 seconds
Started Jul 07 05:46:11 PM PDT 24
Finished Jul 07 05:46:12 PM PDT 24
Peak memory 195420 kb
Host smart-942c745e-a1a7-465d-9cd0-30dab3d2383f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046335450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1046335450
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.943405032
Short name T200
Test name
Test status
Simulation time 46178161 ps
CPU time 0.88 seconds
Started Jul 07 05:46:08 PM PDT 24
Finished Jul 07 05:46:09 PM PDT 24
Peak memory 197288 kb
Host smart-a9872967-aab9-4b09-8f42-2dce9d146ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943405032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.943405032
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2635401711
Short name T651
Test name
Test status
Simulation time 217663622 ps
CPU time 5.08 seconds
Started Jul 07 05:46:15 PM PDT 24
Finished Jul 07 05:46:21 PM PDT 24
Peak memory 198704 kb
Host smart-fb7fed0e-d00c-40d2-9edd-acc32192d578
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635401711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2635401711
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.472532487
Short name T115
Test name
Test status
Simulation time 23047270 ps
CPU time 0.68 seconds
Started Jul 07 05:46:14 PM PDT 24
Finished Jul 07 05:46:15 PM PDT 24
Peak memory 195256 kb
Host smart-882a6c24-7709-4668-babe-7eaaaf167d7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472532487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.472532487
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1616962756
Short name T316
Test name
Test status
Simulation time 229021748 ps
CPU time 0.76 seconds
Started Jul 07 05:46:05 PM PDT 24
Finished Jul 07 05:46:06 PM PDT 24
Peak memory 195984 kb
Host smart-5327a816-4af2-496d-88a7-af6454a7b99c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616962756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1616962756
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3600861853
Short name T608
Test name
Test status
Simulation time 122033470 ps
CPU time 1.69 seconds
Started Jul 07 05:46:08 PM PDT 24
Finished Jul 07 05:46:10 PM PDT 24
Peak memory 197536 kb
Host smart-341fb94d-3f69-4a3b-8f5f-9123fa7bcfb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600861853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3600861853
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1826751747
Short name T696
Test name
Test status
Simulation time 265264678 ps
CPU time 2.12 seconds
Started Jul 07 05:46:07 PM PDT 24
Finished Jul 07 05:46:09 PM PDT 24
Peak memory 197704 kb
Host smart-916fe0ec-ec6b-4913-8e1f-c906161a8c5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826751747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1826751747
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3647703410
Short name T457
Test name
Test status
Simulation time 26422727 ps
CPU time 0.99 seconds
Started Jul 07 05:46:08 PM PDT 24
Finished Jul 07 05:46:10 PM PDT 24
Peak memory 197384 kb
Host smart-baa0a7a9-f081-49bb-b5a0-1de1afdb9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647703410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3647703410
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2982924326
Short name T331
Test name
Test status
Simulation time 91518852 ps
CPU time 1.09 seconds
Started Jul 07 05:46:07 PM PDT 24
Finished Jul 07 05:46:08 PM PDT 24
Peak memory 197476 kb
Host smart-d0fc73f5-6949-4919-bc26-f92b1384edcc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982924326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2982924326
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4068039342
Short name T702
Test name
Test status
Simulation time 110680800 ps
CPU time 2.51 seconds
Started Jul 07 05:46:11 PM PDT 24
Finished Jul 07 05:46:14 PM PDT 24
Peak memory 198548 kb
Host smart-c032a62f-1212-4b17-941c-02334a009691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068039342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4068039342
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2426343030
Short name T25
Test name
Test status
Simulation time 134388406 ps
CPU time 1.17 seconds
Started Jul 07 05:46:06 PM PDT 24
Finished Jul 07 05:46:08 PM PDT 24
Peak memory 197072 kb
Host smart-a97ad2fd-b5e4-4ed8-a3b9-151158d66bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426343030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2426343030
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1248989155
Short name T581
Test name
Test status
Simulation time 59950281 ps
CPU time 1.08 seconds
Started Jul 07 05:46:07 PM PDT 24
Finished Jul 07 05:46:09 PM PDT 24
Peak memory 196416 kb
Host smart-1902210d-8f01-458c-bb66-957ee30ae0e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248989155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1248989155
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.830760640
Short name T251
Test name
Test status
Simulation time 22287398191 ps
CPU time 76.89 seconds
Started Jul 07 05:46:12 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 198788 kb
Host smart-7d8d661b-92c9-40ec-bbae-8633ceb5f8fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830760640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.830760640
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1110643561
Short name T59
Test name
Test status
Simulation time 87295885807 ps
CPU time 1718.51 seconds
Started Jul 07 05:46:11 PM PDT 24
Finished Jul 07 06:14:50 PM PDT 24
Peak memory 198924 kb
Host smart-7a889313-4fab-4641-a0f0-0859a8db6065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1110643561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1110643561
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3544905004
Short name T674
Test name
Test status
Simulation time 19519039 ps
CPU time 0.58 seconds
Started Jul 07 05:46:14 PM PDT 24
Finished Jul 07 05:46:15 PM PDT 24
Peak memory 194680 kb
Host smart-064ff10a-16de-4443-aca7-6cf07a71b501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544905004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3544905004
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3888239938
Short name T411
Test name
Test status
Simulation time 37492876 ps
CPU time 0.78 seconds
Started Jul 07 05:46:12 PM PDT 24
Finished Jul 07 05:46:13 PM PDT 24
Peak memory 196036 kb
Host smart-ce0ecb5d-fb9b-4ad3-929b-843cfab68060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888239938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3888239938
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4150145275
Short name T444
Test name
Test status
Simulation time 1328437478 ps
CPU time 13.74 seconds
Started Jul 07 05:46:10 PM PDT 24
Finished Jul 07 05:46:24 PM PDT 24
Peak memory 197652 kb
Host smart-3d55259e-9af6-45b1-b73c-5ca45c07d3f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150145275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4150145275
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3147009462
Short name T100
Test name
Test status
Simulation time 170185254 ps
CPU time 0.79 seconds
Started Jul 07 05:46:10 PM PDT 24
Finished Jul 07 05:46:11 PM PDT 24
Peak memory 196580 kb
Host smart-ae4912b2-8bd4-42f6-ae9b-dca519ffc579
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147009462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3147009462
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.513469062
Short name T360
Test name
Test status
Simulation time 281301773 ps
CPU time 1.07 seconds
Started Jul 07 05:46:12 PM PDT 24
Finished Jul 07 05:46:13 PM PDT 24
Peak memory 196540 kb
Host smart-bfd2fc26-7b10-426c-868f-5326be1dd38f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513469062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.513469062
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1384229877
Short name T492
Test name
Test status
Simulation time 200632755 ps
CPU time 2.22 seconds
Started Jul 07 05:46:09 PM PDT 24
Finished Jul 07 05:46:12 PM PDT 24
Peak memory 198740 kb
Host smart-7a566cb6-906f-4908-893c-96856a8d08bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384229877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1384229877
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.785639060
Short name T280
Test name
Test status
Simulation time 83686451 ps
CPU time 0.93 seconds
Started Jul 07 05:46:13 PM PDT 24
Finished Jul 07 05:46:14 PM PDT 24
Peak memory 196240 kb
Host smart-98e7b1df-e965-48f9-bff5-393216f9a2e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785639060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
785639060
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.960903725
Short name T283
Test name
Test status
Simulation time 16141196 ps
CPU time 0.72 seconds
Started Jul 07 05:46:15 PM PDT 24
Finished Jul 07 05:46:16 PM PDT 24
Peak memory 195992 kb
Host smart-14734059-fffa-4b5b-92ae-d9af95162109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960903725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.960903725
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.489676715
Short name T48
Test name
Test status
Simulation time 31970147 ps
CPU time 0.73 seconds
Started Jul 07 05:46:14 PM PDT 24
Finished Jul 07 05:46:15 PM PDT 24
Peak memory 195988 kb
Host smart-65ee07d6-e4f5-4c94-9ff7-e23c890f2667
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489676715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.489676715
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4082898823
Short name T270
Test name
Test status
Simulation time 910792262 ps
CPU time 5.55 seconds
Started Jul 07 05:46:11 PM PDT 24
Finished Jul 07 05:46:17 PM PDT 24
Peak memory 198624 kb
Host smart-9d17aa85-0a2a-46cf-baf5-c8e390cec40e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082898823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4082898823
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.489967894
Short name T465
Test name
Test status
Simulation time 130391925 ps
CPU time 0.92 seconds
Started Jul 07 05:46:09 PM PDT 24
Finished Jul 07 05:46:11 PM PDT 24
Peak memory 196484 kb
Host smart-062bc243-23c1-4ca6-950f-5f0acdc11b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489967894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.489967894
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.520023378
Short name T300
Test name
Test status
Simulation time 81288834 ps
CPU time 1.28 seconds
Started Jul 07 05:46:09 PM PDT 24
Finished Jul 07 05:46:11 PM PDT 24
Peak memory 198692 kb
Host smart-df72b57b-08ab-4c4f-b3e7-be9046d383e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520023378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.520023378
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2638668145
Short name T554
Test name
Test status
Simulation time 14526371862 ps
CPU time 202.62 seconds
Started Jul 07 05:46:19 PM PDT 24
Finished Jul 07 05:49:42 PM PDT 24
Peak memory 198800 kb
Host smart-0d089467-ea44-4517-aca7-ea1898bd5356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638668145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2638668145
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.324422199
Short name T28
Test name
Test status
Simulation time 19528008 ps
CPU time 0.6 seconds
Started Jul 07 05:44:31 PM PDT 24
Finished Jul 07 05:44:32 PM PDT 24
Peak memory 194628 kb
Host smart-74fb8192-d275-4592-99fc-a9088aff973d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324422199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.324422199
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3330724381
Short name T584
Test name
Test status
Simulation time 144035648 ps
CPU time 0.7 seconds
Started Jul 07 05:44:25 PM PDT 24
Finished Jul 07 05:44:26 PM PDT 24
Peak memory 195448 kb
Host smart-eb14f23f-fc3a-4b42-b97a-2588b02b6821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330724381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3330724381
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.281733629
Short name T501
Test name
Test status
Simulation time 2020252192 ps
CPU time 25.55 seconds
Started Jul 07 05:44:30 PM PDT 24
Finished Jul 07 05:44:56 PM PDT 24
Peak memory 196220 kb
Host smart-4812de81-a943-40f4-b142-efcae6ab0ec0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281733629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.281733629
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2729762245
Short name T418
Test name
Test status
Simulation time 267175780 ps
CPU time 0.96 seconds
Started Jul 07 05:44:25 PM PDT 24
Finished Jul 07 05:44:27 PM PDT 24
Peak memory 197240 kb
Host smart-52e3f20a-429d-41b9-a622-46d1e8d71005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729762245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2729762245
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2382602432
Short name T407
Test name
Test status
Simulation time 48306884 ps
CPU time 1.32 seconds
Started Jul 07 05:44:26 PM PDT 24
Finished Jul 07 05:44:28 PM PDT 24
Peak memory 197488 kb
Host smart-3d41cfd8-8fcb-4810-b43d-c9fb831dfdc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382602432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2382602432
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3366608385
Short name T517
Test name
Test status
Simulation time 61969312 ps
CPU time 2.39 seconds
Started Jul 07 05:44:23 PM PDT 24
Finished Jul 07 05:44:26 PM PDT 24
Peak memory 198796 kb
Host smart-b6691884-5930-40f2-ad29-9f99662d2a20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366608385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3366608385
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.597789270
Short name T546
Test name
Test status
Simulation time 93930016 ps
CPU time 2.76 seconds
Started Jul 07 05:44:24 PM PDT 24
Finished Jul 07 05:44:27 PM PDT 24
Peak memory 198736 kb
Host smart-8103d94e-78f5-4623-aec8-e4193143c50f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597789270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.597789270
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.997107538
Short name T544
Test name
Test status
Simulation time 48127901 ps
CPU time 0.79 seconds
Started Jul 07 05:44:19 PM PDT 24
Finished Jul 07 05:44:20 PM PDT 24
Peak memory 196136 kb
Host smart-939765b4-c371-4575-adca-e1f6efafb7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997107538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.997107538
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4130088799
Short name T703
Test name
Test status
Simulation time 71211322 ps
CPU time 1.36 seconds
Started Jul 07 05:44:26 PM PDT 24
Finished Jul 07 05:44:28 PM PDT 24
Peak memory 197744 kb
Host smart-40088666-ce72-430e-98bd-cececf110c88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130088799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4130088799
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3488565519
Short name T424
Test name
Test status
Simulation time 189843828 ps
CPU time 4.9 seconds
Started Jul 07 05:44:23 PM PDT 24
Finished Jul 07 05:44:28 PM PDT 24
Peak memory 198588 kb
Host smart-0cbb5cb0-4df7-419b-a397-3e0064888900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488565519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3488565519
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3515608375
Short name T36
Test name
Test status
Simulation time 328889269 ps
CPU time 0.8 seconds
Started Jul 07 05:44:30 PM PDT 24
Finished Jul 07 05:44:31 PM PDT 24
Peak memory 214188 kb
Host smart-afcd6c73-e055-4db6-821d-eabbbf4154c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515608375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3515608375
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1952165928
Short name T452
Test name
Test status
Simulation time 146493124 ps
CPU time 1.4 seconds
Started Jul 07 05:44:18 PM PDT 24
Finished Jul 07 05:44:20 PM PDT 24
Peak memory 197196 kb
Host smart-04eb1502-a10a-4d92-849d-b836742b9924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952165928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1952165928
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.4030146731
Short name T27
Test name
Test status
Simulation time 54006563 ps
CPU time 1.39 seconds
Started Jul 07 05:44:20 PM PDT 24
Finished Jul 07 05:44:22 PM PDT 24
Peak memory 196296 kb
Host smart-289d85e0-bc45-40be-a943-d9a76c7bd4af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030146731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.4030146731
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4266240937
Short name T312
Test name
Test status
Simulation time 7408907766 ps
CPU time 207.1 seconds
Started Jul 07 05:44:28 PM PDT 24
Finished Jul 07 05:47:55 PM PDT 24
Peak memory 198784 kb
Host smart-f3adabe2-4a62-47ff-90dd-dff39b988231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266240937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4266240937
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.322496514
Short name T195
Test name
Test status
Simulation time 108523201 ps
CPU time 0.59 seconds
Started Jul 07 05:46:20 PM PDT 24
Finished Jul 07 05:46:21 PM PDT 24
Peak memory 194848 kb
Host smart-c448e057-9d43-4322-8175-b13760374293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322496514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.322496514
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1826483699
Short name T439
Test name
Test status
Simulation time 90794814 ps
CPU time 0.78 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 195852 kb
Host smart-509fa281-f92b-4a8e-a128-85987d76485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826483699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1826483699
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.805085367
Short name T114
Test name
Test status
Simulation time 764645260 ps
CPU time 20.66 seconds
Started Jul 07 05:46:15 PM PDT 24
Finished Jul 07 05:46:36 PM PDT 24
Peak memory 197628 kb
Host smart-bc670472-b1e6-42bc-8f23-72dbdc9825c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805085367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.805085367
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2662777656
Short name T562
Test name
Test status
Simulation time 191076171 ps
CPU time 0.9 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 197340 kb
Host smart-c544139f-a7ef-4565-a962-66b2a0131056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662777656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2662777656
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4166891068
Short name T472
Test name
Test status
Simulation time 36077406 ps
CPU time 0.9 seconds
Started Jul 07 05:46:15 PM PDT 24
Finished Jul 07 05:46:17 PM PDT 24
Peak memory 196988 kb
Host smart-95c436ef-2a98-4755-9ddf-ea190cae345d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166891068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4166891068
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3536387452
Short name T594
Test name
Test status
Simulation time 55637150 ps
CPU time 2.39 seconds
Started Jul 07 05:46:17 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 198744 kb
Host smart-2af61317-307e-40c8-a986-678452e78e1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536387452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3536387452
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2830879197
Short name T292
Test name
Test status
Simulation time 216210468 ps
CPU time 1.34 seconds
Started Jul 07 05:46:15 PM PDT 24
Finished Jul 07 05:46:16 PM PDT 24
Peak memory 197360 kb
Host smart-e4ffb4e8-9c5e-43e6-ba54-73a3e96d11e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830879197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2830879197
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2804131130
Short name T481
Test name
Test status
Simulation time 292055904 ps
CPU time 1.37 seconds
Started Jul 07 05:46:17 PM PDT 24
Finished Jul 07 05:46:19 PM PDT 24
Peak memory 196464 kb
Host smart-6787ae4a-05db-4c62-8442-8486d76601a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804131130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2804131130
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2195063565
Short name T106
Test name
Test status
Simulation time 55080864 ps
CPU time 1.11 seconds
Started Jul 07 05:46:16 PM PDT 24
Finished Jul 07 05:46:18 PM PDT 24
Peak memory 197488 kb
Host smart-f71a1b6c-d416-4835-8985-567d65880459
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195063565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2195063565
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1856444313
Short name T650
Test name
Test status
Simulation time 208871388 ps
CPU time 5.25 seconds
Started Jul 07 05:46:18 PM PDT 24
Finished Jul 07 05:46:23 PM PDT 24
Peak memory 198708 kb
Host smart-9a53d533-c6e4-422c-8a0a-c39ddce0b0a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856444313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1856444313
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2335335355
Short name T435
Test name
Test status
Simulation time 33474546 ps
CPU time 1.08 seconds
Started Jul 07 05:46:19 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 196408 kb
Host smart-e20d1a1e-141d-45d6-8232-a6a3b7ea717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335335355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2335335355
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2950457678
Short name T582
Test name
Test status
Simulation time 142265340 ps
CPU time 1.26 seconds
Started Jul 07 05:46:14 PM PDT 24
Finished Jul 07 05:46:16 PM PDT 24
Peak memory 198604 kb
Host smart-dcad70f8-be59-4935-9169-d78925c8fc21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950457678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2950457678
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.646342153
Short name T386
Test name
Test status
Simulation time 8951392371 ps
CPU time 65.55 seconds
Started Jul 07 05:46:17 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 198784 kb
Host smart-c67913f8-2574-4d43-80e7-d2dc86adfa3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646342153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.646342153
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3138222094
Short name T693
Test name
Test status
Simulation time 26559400 ps
CPU time 0.6 seconds
Started Jul 07 05:46:19 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 194888 kb
Host smart-49634605-cdda-4570-883e-5a3fc4a5eb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138222094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3138222094
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.645306919
Short name T530
Test name
Test status
Simulation time 70072093 ps
CPU time 0.64 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:26 PM PDT 24
Peak memory 195416 kb
Host smart-28d2ad57-6e35-49bf-b59a-71334beeaa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645306919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.645306919
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3698671214
Short name T604
Test name
Test status
Simulation time 1494929036 ps
CPU time 21.86 seconds
Started Jul 07 05:46:15 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 198704 kb
Host smart-bb1182ec-e2cc-4fc8-951b-2ccdf20e15b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698671214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3698671214
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3000050013
Short name T489
Test name
Test status
Simulation time 110301638 ps
CPU time 0.66 seconds
Started Jul 07 05:46:16 PM PDT 24
Finished Jul 07 05:46:17 PM PDT 24
Peak memory 195076 kb
Host smart-e6e8a93c-a319-447f-b549-20c6cc9a6c41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000050013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3000050013
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2001977192
Short name T413
Test name
Test status
Simulation time 89464100 ps
CPU time 1.5 seconds
Started Jul 07 05:46:17 PM PDT 24
Finished Jul 07 05:46:19 PM PDT 24
Peak memory 197604 kb
Host smart-e82ddf77-fe17-44e1-a54f-28d028d32bc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001977192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2001977192
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1478306745
Short name T564
Test name
Test status
Simulation time 83605145 ps
CPU time 1.9 seconds
Started Jul 07 05:46:21 PM PDT 24
Finished Jul 07 05:46:24 PM PDT 24
Peak memory 198644 kb
Host smart-a3597299-adb6-4f18-acd8-c98a5d728523
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478306745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1478306745
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3205237858
Short name T649
Test name
Test status
Simulation time 400118438 ps
CPU time 2.06 seconds
Started Jul 07 05:46:18 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 196692 kb
Host smart-8897c8bf-9a75-4248-9044-a875e29950a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205237858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3205237858
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.945432165
Short name T196
Test name
Test status
Simulation time 19007220 ps
CPU time 0.67 seconds
Started Jul 07 05:46:17 PM PDT 24
Finished Jul 07 05:46:18 PM PDT 24
Peak memory 195032 kb
Host smart-d858462c-e3b1-4e4c-bc78-51f79bb49f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945432165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.945432165
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1137378179
Short name T482
Test name
Test status
Simulation time 108441522 ps
CPU time 0.73 seconds
Started Jul 07 05:46:19 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 196076 kb
Host smart-914109ee-0b3d-4d74-b9fe-a2bcb633850b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137378179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1137378179
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2286934272
Short name T313
Test name
Test status
Simulation time 160640127 ps
CPU time 2.58 seconds
Started Jul 07 05:46:17 PM PDT 24
Finished Jul 07 05:46:20 PM PDT 24
Peak memory 198588 kb
Host smart-5efc3650-5faa-480c-93e1-940e5605a1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286934272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2286934272
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2727312095
Short name T420
Test name
Test status
Simulation time 834100149 ps
CPU time 1.17 seconds
Started Jul 07 05:46:20 PM PDT 24
Finished Jul 07 05:46:22 PM PDT 24
Peak memory 196376 kb
Host smart-36d3ad58-c6b0-4664-aa4a-3577982d48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727312095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2727312095
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.49260543
Short name T634
Test name
Test status
Simulation time 50055945 ps
CPU time 1.16 seconds
Started Jul 07 05:46:26 PM PDT 24
Finished Jul 07 05:46:28 PM PDT 24
Peak memory 196492 kb
Host smart-e531eaf2-704d-4b46-b657-98c1dd3dca1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49260543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.49260543
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2761325302
Short name T454
Test name
Test status
Simulation time 16059001516 ps
CPU time 205.53 seconds
Started Jul 07 05:46:19 PM PDT 24
Finished Jul 07 05:49:45 PM PDT 24
Peak memory 198792 kb
Host smart-164a8adc-021d-46a4-8b4b-88e0f6edbf32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761325302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2761325302
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3518722064
Short name T684
Test name
Test status
Simulation time 33658636 ps
CPU time 0.56 seconds
Started Jul 07 05:46:26 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 194836 kb
Host smart-b0dcf547-b063-4825-89a0-1edca6d4b102
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518722064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3518722064
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2953860009
Short name T432
Test name
Test status
Simulation time 126014671 ps
CPU time 0.89 seconds
Started Jul 07 05:46:23 PM PDT 24
Finished Jul 07 05:46:24 PM PDT 24
Peak memory 196084 kb
Host smart-5ed4469c-e79f-4307-80b8-a81358d80582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953860009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2953860009
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2259146088
Short name T406
Test name
Test status
Simulation time 440423802 ps
CPU time 3.73 seconds
Started Jul 07 05:46:23 PM PDT 24
Finished Jul 07 05:46:26 PM PDT 24
Peak memory 196644 kb
Host smart-3b04b2a8-7e2a-413d-906d-84a6f08942df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259146088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2259146088
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.965259085
Short name T21
Test name
Test status
Simulation time 100907070 ps
CPU time 0.85 seconds
Started Jul 07 05:46:23 PM PDT 24
Finished Jul 07 05:46:24 PM PDT 24
Peak memory 196676 kb
Host smart-48e0902b-4c3b-451c-ae91-9f33a6d17d24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965259085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.965259085
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3688954302
Short name T289
Test name
Test status
Simulation time 29362048 ps
CPU time 0.9 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 197316 kb
Host smart-0b2e9709-067f-4bd6-8d2c-9d253d697a62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688954302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3688954302
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.272426843
Short name T633
Test name
Test status
Simulation time 52392167 ps
CPU time 1.27 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:26 PM PDT 24
Peak memory 197572 kb
Host smart-ddfb2e0b-a687-4685-93cc-030123018927
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272426843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.272426843
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.998467825
Short name T227
Test name
Test status
Simulation time 152794381 ps
CPU time 1.33 seconds
Started Jul 07 05:46:23 PM PDT 24
Finished Jul 07 05:46:24 PM PDT 24
Peak memory 197400 kb
Host smart-93527cb5-fc30-4431-bff7-403bba9ba284
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998467825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
998467825
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3468354813
Short name T695
Test name
Test status
Simulation time 40269274 ps
CPU time 1.02 seconds
Started Jul 07 05:46:27 PM PDT 24
Finished Jul 07 05:46:28 PM PDT 24
Peak memory 196692 kb
Host smart-9448a651-a3e5-4514-a968-7c48e3698ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468354813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3468354813
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3275877750
Short name T147
Test name
Test status
Simulation time 68228866 ps
CPU time 0.85 seconds
Started Jul 07 05:46:21 PM PDT 24
Finished Jul 07 05:46:22 PM PDT 24
Peak memory 197340 kb
Host smart-19e86197-9df4-4810-b2f2-38532dbf8a72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275877750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3275877750
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.960410985
Short name T20
Test name
Test status
Simulation time 4299366899 ps
CPU time 6.25 seconds
Started Jul 07 05:46:21 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 198664 kb
Host smart-5e3111d9-8e80-43eb-8e08-a450dd97075e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960410985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.960410985
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2061992120
Short name T580
Test name
Test status
Simulation time 265883273 ps
CPU time 1.19 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 196424 kb
Host smart-fde20a02-81aa-411e-ac7e-4bad8b028881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061992120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2061992120
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3907134775
Short name T484
Test name
Test status
Simulation time 32253962 ps
CPU time 0.99 seconds
Started Jul 07 05:46:22 PM PDT 24
Finished Jul 07 05:46:23 PM PDT 24
Peak memory 196248 kb
Host smart-2bf40dfe-e75c-4963-b647-5ff2dfe1d90f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907134775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3907134775
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.398053457
Short name T50
Test name
Test status
Simulation time 39124833094 ps
CPU time 147.8 seconds
Started Jul 07 05:46:22 PM PDT 24
Finished Jul 07 05:48:50 PM PDT 24
Peak memory 198788 kb
Host smart-37940e47-fc34-4b3d-a422-2e54176e6164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398053457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.398053457
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1354489806
Short name T672
Test name
Test status
Simulation time 17937088149 ps
CPU time 560.18 seconds
Started Jul 07 05:46:20 PM PDT 24
Finished Jul 07 05:55:40 PM PDT 24
Peak memory 198912 kb
Host smart-ae3a6c6e-6553-4c7d-bfca-df999c815be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1354489806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1354489806
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.178290172
Short name T480
Test name
Test status
Simulation time 15361341 ps
CPU time 0.56 seconds
Started Jul 07 05:46:31 PM PDT 24
Finished Jul 07 05:46:31 PM PDT 24
Peak memory 194688 kb
Host smart-7b830c7a-a349-498d-8e0d-a6ed98261dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178290172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.178290172
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3646386605
Short name T509
Test name
Test status
Simulation time 45056100 ps
CPU time 0.7 seconds
Started Jul 07 05:46:24 PM PDT 24
Finished Jul 07 05:46:25 PM PDT 24
Peak memory 195492 kb
Host smart-9871ac80-2643-4b38-b2a1-9a26409dc872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646386605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3646386605
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2606289168
Short name T170
Test name
Test status
Simulation time 836518709 ps
CPU time 25.86 seconds
Started Jul 07 05:46:29 PM PDT 24
Finished Jul 07 05:46:55 PM PDT 24
Peak memory 197700 kb
Host smart-96575aa6-2cbc-41f1-8b22-998421790ce6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606289168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2606289168
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.254569351
Short name T638
Test name
Test status
Simulation time 63969305 ps
CPU time 0.96 seconds
Started Jul 07 05:46:31 PM PDT 24
Finished Jul 07 05:46:32 PM PDT 24
Peak memory 198564 kb
Host smart-7e370c7a-bb03-45cc-9f6a-f8db2a582177
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254569351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.254569351
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1319579757
Short name T18
Test name
Test status
Simulation time 110824850 ps
CPU time 0.92 seconds
Started Jul 07 05:46:22 PM PDT 24
Finished Jul 07 05:46:24 PM PDT 24
Peak memory 196468 kb
Host smart-a7255fb8-2ee6-4da9-95c8-88d83138379e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319579757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1319579757
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3686410801
Short name T500
Test name
Test status
Simulation time 57155364 ps
CPU time 2.35 seconds
Started Jul 07 05:46:24 PM PDT 24
Finished Jul 07 05:46:26 PM PDT 24
Peak memory 198704 kb
Host smart-cb70cdfa-12d5-41c2-b3f8-936b7b7eb714
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686410801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3686410801
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3894181939
Short name T269
Test name
Test status
Simulation time 67836186 ps
CPU time 1.48 seconds
Started Jul 07 05:46:29 PM PDT 24
Finished Jul 07 05:46:31 PM PDT 24
Peak memory 196516 kb
Host smart-b5f34db4-d93b-42cf-b612-6b466033633c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894181939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3894181939
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1079431611
Short name T257
Test name
Test status
Simulation time 351413999 ps
CPU time 1.28 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 198044 kb
Host smart-75e465a3-6253-403a-961e-b511e65b24b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079431611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1079431611
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1951557100
Short name T375
Test name
Test status
Simulation time 27514445 ps
CPU time 0.78 seconds
Started Jul 07 05:46:28 PM PDT 24
Finished Jul 07 05:46:29 PM PDT 24
Peak memory 196820 kb
Host smart-33718d32-48cd-4cc6-b1ff-4ce5e8b3a92b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951557100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1951557100
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1898508902
Short name T118
Test name
Test status
Simulation time 293425890 ps
CPU time 4.98 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:31 PM PDT 24
Peak memory 198596 kb
Host smart-8547e385-c6a5-46e0-8a02-0340b98fabb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898508902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1898508902
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1579114484
Short name T706
Test name
Test status
Simulation time 1433787163 ps
CPU time 1.43 seconds
Started Jul 07 05:46:26 PM PDT 24
Finished Jul 07 05:46:28 PM PDT 24
Peak memory 197500 kb
Host smart-249a7324-05a0-4919-8330-b094ceea9ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579114484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1579114484
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3798664232
Short name T614
Test name
Test status
Simulation time 40029505 ps
CPU time 1.13 seconds
Started Jul 07 05:46:24 PM PDT 24
Finished Jul 07 05:46:26 PM PDT 24
Peak memory 196368 kb
Host smart-5f820417-b35b-4f1b-80a6-3257597047d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798664232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3798664232
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1317644306
Short name T99
Test name
Test status
Simulation time 6149918987 ps
CPU time 186.09 seconds
Started Jul 07 05:46:27 PM PDT 24
Finished Jul 07 05:49:33 PM PDT 24
Peak memory 198824 kb
Host smart-34e96cc0-330b-4607-a963-ca92177eda1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317644306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1317644306
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.454617747
Short name T704
Test name
Test status
Simulation time 13857075612 ps
CPU time 504.97 seconds
Started Jul 07 05:46:30 PM PDT 24
Finished Jul 07 05:54:55 PM PDT 24
Peak memory 198884 kb
Host smart-0ca769f1-590c-495c-85d9-db3e74f65d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=454617747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.454617747
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.707498132
Short name T175
Test name
Test status
Simulation time 18842492 ps
CPU time 0.59 seconds
Started Jul 07 05:46:32 PM PDT 24
Finished Jul 07 05:46:33 PM PDT 24
Peak memory 196412 kb
Host smart-67fd69f3-ace0-4ead-96b9-0018071baf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707498132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.707498132
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2096220323
Short name T219
Test name
Test status
Simulation time 29906575 ps
CPU time 0.88 seconds
Started Jul 07 05:46:32 PM PDT 24
Finished Jul 07 05:46:34 PM PDT 24
Peak memory 197260 kb
Host smart-5cdd5a85-f579-4a8c-8f3b-1a4cad041532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096220323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2096220323
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2652048136
Short name T636
Test name
Test status
Simulation time 803634694 ps
CPU time 27.16 seconds
Started Jul 07 05:46:29 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 196236 kb
Host smart-63d7d2e8-bf9c-4428-8577-a56366abde41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652048136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2652048136
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2160729506
Short name T258
Test name
Test status
Simulation time 164303013 ps
CPU time 0.99 seconds
Started Jul 07 05:46:29 PM PDT 24
Finished Jul 07 05:46:31 PM PDT 24
Peak memory 197080 kb
Host smart-d4ab495a-0704-4512-a522-3c6e6d8c7d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160729506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2160729506
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.604359109
Short name T241
Test name
Test status
Simulation time 213080704 ps
CPU time 1.16 seconds
Started Jul 07 05:46:27 PM PDT 24
Finished Jul 07 05:46:29 PM PDT 24
Peak memory 196520 kb
Host smart-45489871-87d4-4fc7-84fc-f15a66edc2ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604359109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.604359109
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.872050419
Short name T629
Test name
Test status
Simulation time 451863313 ps
CPU time 3.58 seconds
Started Jul 07 05:46:32 PM PDT 24
Finished Jul 07 05:46:36 PM PDT 24
Peak memory 198692 kb
Host smart-9d05842e-5330-43b5-a8a1-d5fc05323141
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872050419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.872050419
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1636345281
Short name T171
Test name
Test status
Simulation time 145387545 ps
CPU time 1.4 seconds
Started Jul 07 05:46:26 PM PDT 24
Finished Jul 07 05:46:28 PM PDT 24
Peak memory 196476 kb
Host smart-cc39e771-9a00-4d72-8880-2eb6a78da422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636345281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1636345281
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2539243433
Short name T648
Test name
Test status
Simulation time 86593929 ps
CPU time 0.97 seconds
Started Jul 07 05:46:28 PM PDT 24
Finished Jul 07 05:46:29 PM PDT 24
Peak memory 196572 kb
Host smart-3857fed8-9403-4560-a452-c3091919e78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539243433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2539243433
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3127123711
Short name T229
Test name
Test status
Simulation time 38298493 ps
CPU time 0.72 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 195652 kb
Host smart-a075c9ec-1694-4bfe-8679-304c704dc1d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127123711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3127123711
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3004254783
Short name T403
Test name
Test status
Simulation time 1221995606 ps
CPU time 5.29 seconds
Started Jul 07 05:46:31 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 198708 kb
Host smart-12473a54-3614-49cc-9973-808960953e1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004254783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3004254783
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2005625105
Short name T427
Test name
Test status
Simulation time 78376689 ps
CPU time 1.14 seconds
Started Jul 07 05:46:29 PM PDT 24
Finished Jul 07 05:46:30 PM PDT 24
Peak memory 196540 kb
Host smart-dd99a8b4-2df5-4d51-a19d-3ca5f8fba6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005625105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2005625105
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2941496816
Short name T653
Test name
Test status
Simulation time 112177260 ps
CPU time 0.99 seconds
Started Jul 07 05:46:25 PM PDT 24
Finished Jul 07 05:46:27 PM PDT 24
Peak memory 196476 kb
Host smart-89491408-4e86-4e35-9883-91d4aa508e7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941496816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2941496816
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1629517763
Short name T381
Test name
Test status
Simulation time 34945817619 ps
CPU time 172.56 seconds
Started Jul 07 05:46:33 PM PDT 24
Finished Jul 07 05:49:25 PM PDT 24
Peak memory 198852 kb
Host smart-468eae78-f65d-4399-949b-ce536eb42cd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629517763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1629517763
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2330873964
Short name T460
Test name
Test status
Simulation time 251921255245 ps
CPU time 1217.14 seconds
Started Jul 07 05:46:33 PM PDT 24
Finished Jul 07 06:06:50 PM PDT 24
Peak memory 198964 kb
Host smart-f5ce9dae-025b-4613-a6d5-d937c90dfc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2330873964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2330873964
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3666880227
Short name T395
Test name
Test status
Simulation time 67999267 ps
CPU time 0.58 seconds
Started Jul 07 05:46:35 PM PDT 24
Finished Jul 07 05:46:35 PM PDT 24
Peak memory 194676 kb
Host smart-e1d7472c-b4b3-4f06-a79c-271a52a43448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666880227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3666880227
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1007116938
Short name T592
Test name
Test status
Simulation time 82438694 ps
CPU time 0.76 seconds
Started Jul 07 05:46:34 PM PDT 24
Finished Jul 07 05:46:35 PM PDT 24
Peak memory 195444 kb
Host smart-f34644d2-f65c-441c-9308-0f15b296b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007116938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1007116938
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3559762602
Short name T110
Test name
Test status
Simulation time 413346196 ps
CPU time 13.95 seconds
Started Jul 07 05:46:35 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 197548 kb
Host smart-619cfca9-0353-4d19-aa03-0b80b8ff1e1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559762602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3559762602
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3027328469
Short name T712
Test name
Test status
Simulation time 645767502 ps
CPU time 0.85 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:40 PM PDT 24
Peak memory 195472 kb
Host smart-4414065d-0019-4f0c-8e10-d81f077d85b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027328469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3027328469
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2111605488
Short name T263
Test name
Test status
Simulation time 78199261 ps
CPU time 0.75 seconds
Started Jul 07 05:46:32 PM PDT 24
Finished Jul 07 05:46:33 PM PDT 24
Peak memory 196084 kb
Host smart-9b986407-f314-4e82-b79d-5191c97344a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111605488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2111605488
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4138762856
Short name T662
Test name
Test status
Simulation time 187586575 ps
CPU time 2.37 seconds
Started Jul 07 05:46:34 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 198612 kb
Host smart-5d6ef964-27a4-49ac-a180-47a4154fe695
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138762856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4138762856
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.882941252
Short name T587
Test name
Test status
Simulation time 208162109 ps
CPU time 1.51 seconds
Started Jul 07 05:46:35 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 196476 kb
Host smart-015dddf6-79cc-44b4-a8ce-2d545abec7da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882941252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
882941252
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2531662685
Short name T199
Test name
Test status
Simulation time 366842409 ps
CPU time 1.2 seconds
Started Jul 07 05:46:32 PM PDT 24
Finished Jul 07 05:46:34 PM PDT 24
Peak memory 196768 kb
Host smart-5e4be91d-d004-400f-844c-56f25b4f2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531662685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2531662685
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3989179914
Short name T393
Test name
Test status
Simulation time 103966773 ps
CPU time 0.9 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:40 PM PDT 24
Peak memory 197956 kb
Host smart-a6eb1d74-0ae7-4532-9e77-e3478411e499
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989179914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3989179914
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3928640961
Short name T273
Test name
Test status
Simulation time 772597093 ps
CPU time 2.8 seconds
Started Jul 07 05:46:34 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 198684 kb
Host smart-424493d4-ef89-4bef-bae5-ebc9918722b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928640961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3928640961
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2162291650
Short name T557
Test name
Test status
Simulation time 129686767 ps
CPU time 1.26 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:58 PM PDT 24
Peak memory 195380 kb
Host smart-1ddd8f44-4050-409c-91f0-23f32ee9fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162291650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2162291650
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.4255506829
Short name T166
Test name
Test status
Simulation time 186866456 ps
CPU time 0.85 seconds
Started Jul 07 05:46:32 PM PDT 24
Finished Jul 07 05:46:33 PM PDT 24
Peak memory 196580 kb
Host smart-4d92dfc2-21df-4162-8e86-d79fd0bfdf1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255506829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.4255506829
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2383954859
Short name T276
Test name
Test status
Simulation time 4466518704 ps
CPU time 31.99 seconds
Started Jul 07 05:46:34 PM PDT 24
Finished Jul 07 05:47:06 PM PDT 24
Peak memory 198720 kb
Host smart-2265420a-40b5-48e7-bb77-4077a2fbb5e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383954859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2383954859
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3577742551
Short name T663
Test name
Test status
Simulation time 69632276 ps
CPU time 0.62 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:39 PM PDT 24
Peak memory 195616 kb
Host smart-15abbcf3-6c46-4ef4-9348-7bb19566a703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577742551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3577742551
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.200913680
Short name T503
Test name
Test status
Simulation time 44935990 ps
CPU time 0.65 seconds
Started Jul 07 05:46:36 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 195432 kb
Host smart-f9377fff-a4cb-400c-88a9-188824c7c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200913680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.200913680
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1039335528
Short name T371
Test name
Test status
Simulation time 392522210 ps
CPU time 16.71 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:56 PM PDT 24
Peak memory 197888 kb
Host smart-b64d66d6-a381-4fdd-9673-003d69d661f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039335528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1039335528
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.710363905
Short name T209
Test name
Test status
Simulation time 22551238 ps
CPU time 0.67 seconds
Started Jul 07 05:46:34 PM PDT 24
Finished Jul 07 05:46:35 PM PDT 24
Peak memory 195540 kb
Host smart-f46aba9b-add3-4e30-bdb2-fde064b60221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710363905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.710363905
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.4196690529
Short name T178
Test name
Test status
Simulation time 86944983 ps
CPU time 1.43 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 197248 kb
Host smart-00ab4e7e-f08b-4e26-a3f0-80bb92c3eca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196690529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.4196690529
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4018094493
Short name T496
Test name
Test status
Simulation time 263470478 ps
CPU time 2.76 seconds
Started Jul 07 05:46:37 PM PDT 24
Finished Jul 07 05:46:40 PM PDT 24
Peak memory 198652 kb
Host smart-bdebb57f-e823-444b-b44c-e25673c32469
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018094493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4018094493
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3662154526
Short name T569
Test name
Test status
Simulation time 121248076 ps
CPU time 3.58 seconds
Started Jul 07 05:46:35 PM PDT 24
Finished Jul 07 05:46:39 PM PDT 24
Peak memory 197840 kb
Host smart-24644754-745c-44c3-9c8d-f11c41d72122
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662154526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3662154526
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4210035138
Short name T261
Test name
Test status
Simulation time 248136098 ps
CPU time 1.08 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:39 PM PDT 24
Peak memory 196728 kb
Host smart-5850871a-0e88-40c7-aa18-abeadaa59ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210035138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4210035138
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1055565033
Short name T697
Test name
Test status
Simulation time 26860371 ps
CPU time 0.81 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 195920 kb
Host smart-960ff41b-8e04-4ded-8cbc-a390fe8ad982
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055565033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1055565033
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2938769985
Short name T627
Test name
Test status
Simulation time 827767040 ps
CPU time 3.6 seconds
Started Jul 07 05:46:36 PM PDT 24
Finished Jul 07 05:46:40 PM PDT 24
Peak memory 198692 kb
Host smart-5ef4115e-c238-4bd0-b62d-70c43a86c9ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938769985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2938769985
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2052464794
Short name T400
Test name
Test status
Simulation time 42486331 ps
CPU time 1.19 seconds
Started Jul 07 05:46:36 PM PDT 24
Finished Jul 07 05:46:37 PM PDT 24
Peak memory 196500 kb
Host smart-2f4d7ac2-8e81-4106-8c0a-08ecdfdc6567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052464794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2052464794
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1551668106
Short name T13
Test name
Test status
Simulation time 68338216 ps
CPU time 1.2 seconds
Started Jul 07 05:46:34 PM PDT 24
Finished Jul 07 05:46:36 PM PDT 24
Peak memory 196412 kb
Host smart-2841e7a7-3f90-4855-8174-a69b1547c073
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551668106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1551668106
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1677699744
Short name T536
Test name
Test status
Simulation time 3540338202 ps
CPU time 47.69 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:47:27 PM PDT 24
Peak memory 198856 kb
Host smart-0d1cb802-709e-4e99-85e4-dc9081828044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677699744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1677699744
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3090857035
Short name T494
Test name
Test status
Simulation time 124125201655 ps
CPU time 516.57 seconds
Started Jul 07 05:46:36 PM PDT 24
Finished Jul 07 05:55:13 PM PDT 24
Peak memory 198948 kb
Host smart-f24fda30-32df-4112-a972-a9989dd3eacd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3090857035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3090857035
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3141574928
Short name T669
Test name
Test status
Simulation time 14777665 ps
CPU time 0.59 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:39 PM PDT 24
Peak memory 194600 kb
Host smart-0b11dc1b-2861-4d45-b2aa-52bb0703eb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141574928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3141574928
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3802613375
Short name T505
Test name
Test status
Simulation time 61387030 ps
CPU time 0.8 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:46:40 PM PDT 24
Peak memory 196744 kb
Host smart-8f0e7622-e076-403f-813b-b347bf7a658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802613375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3802613375
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1336408849
Short name T529
Test name
Test status
Simulation time 269949709 ps
CPU time 10.07 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:48 PM PDT 24
Peak memory 197452 kb
Host smart-51fa5f88-7afc-48fd-a954-ac7695af7fe6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336408849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1336408849
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4003771255
Short name T3
Test name
Test status
Simulation time 644131051 ps
CPU time 0.84 seconds
Started Jul 07 05:46:44 PM PDT 24
Finished Jul 07 05:46:45 PM PDT 24
Peak memory 196584 kb
Host smart-cc734163-e41e-43e3-ab6b-803a23e3e651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003771255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4003771255
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3766521022
Short name T372
Test name
Test status
Simulation time 1811629909 ps
CPU time 1.42 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 198724 kb
Host smart-1872d4db-f36f-4533-8999-e77c15e7cce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766521022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3766521022
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3902567509
Short name T23
Test name
Test status
Simulation time 326022939 ps
CPU time 2.92 seconds
Started Jul 07 05:46:40 PM PDT 24
Finished Jul 07 05:46:43 PM PDT 24
Peak memory 198724 kb
Host smart-1ec23db1-8d6b-44e7-9fdc-0dca5f9432c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902567509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3902567509
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4272734152
Short name T574
Test name
Test status
Simulation time 53953985 ps
CPU time 1.46 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 196892 kb
Host smart-a92af5bd-0fb4-47b6-9d04-de6d1b38f3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272734152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4272734152
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.566832689
Short name T285
Test name
Test status
Simulation time 232225638 ps
CPU time 1.22 seconds
Started Jul 07 05:46:41 PM PDT 24
Finished Jul 07 05:46:43 PM PDT 24
Peak memory 197308 kb
Host smart-9a6153e8-f47b-46b3-816a-c8fde8c0aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566832689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.566832689
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1913859800
Short name T152
Test name
Test status
Simulation time 58277436 ps
CPU time 1.34 seconds
Started Jul 07 05:46:40 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 198796 kb
Host smart-a0a2fc9a-c983-4dc8-8ae9-068992fa040a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913859800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1913859800
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1118733219
Short name T535
Test name
Test status
Simulation time 1170068541 ps
CPU time 3.25 seconds
Started Jul 07 05:46:41 PM PDT 24
Finished Jul 07 05:46:45 PM PDT 24
Peak memory 198500 kb
Host smart-a3646ad9-0398-4ae8-b0d9-7957568ffdaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118733219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1118733219
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3871719376
Short name T668
Test name
Test status
Simulation time 59643276 ps
CPU time 1.18 seconds
Started Jul 07 05:46:42 PM PDT 24
Finished Jul 07 05:46:43 PM PDT 24
Peak memory 196556 kb
Host smart-c39e6b51-fdc9-41b9-8d26-cdbf59e1647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871719376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3871719376
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2371933110
Short name T380
Test name
Test status
Simulation time 136628882 ps
CPU time 1.14 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:40 PM PDT 24
Peak memory 196236 kb
Host smart-aac0055b-0568-45b5-8203-c6ef184bbe61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371933110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2371933110
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1209187868
Short name T468
Test name
Test status
Simulation time 18894225867 ps
CPU time 141.46 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:49:01 PM PDT 24
Peak memory 198796 kb
Host smart-a52c6388-bc0e-4ca8-bba3-c3ae11e0a3b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209187868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1209187868
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2859965936
Short name T622
Test name
Test status
Simulation time 13325045 ps
CPU time 0.6 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:46:47 PM PDT 24
Peak memory 194684 kb
Host smart-99fae093-a1e7-4b78-bb28-7db31e4e28dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859965936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2859965936
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.793178389
Short name T187
Test name
Test status
Simulation time 32560562 ps
CPU time 0.71 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:46:41 PM PDT 24
Peak memory 194792 kb
Host smart-c3dca97c-b73d-4978-9925-b688ae988d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793178389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.793178389
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1655798990
Short name T376
Test name
Test status
Simulation time 1882540115 ps
CPU time 9.68 seconds
Started Jul 07 05:46:39 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 196960 kb
Host smart-c720322e-5682-4fda-addc-f9f2c663b985
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655798990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1655798990
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3526040979
Short name T93
Test name
Test status
Simulation time 68979076 ps
CPU time 0.99 seconds
Started Jul 07 05:46:44 PM PDT 24
Finished Jul 07 05:46:45 PM PDT 24
Peak memory 197016 kb
Host smart-cbbbabb7-0a7b-44d5-b1fe-553d7eafd2e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526040979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3526040979
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3229851886
Short name T343
Test name
Test status
Simulation time 60094443 ps
CPU time 0.73 seconds
Started Jul 07 05:46:41 PM PDT 24
Finished Jul 07 05:46:42 PM PDT 24
Peak memory 195824 kb
Host smart-1f0351ef-edd0-4b08-890d-ef11726b6c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229851886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3229851886
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3304801987
Short name T238
Test name
Test status
Simulation time 69640546 ps
CPU time 2.85 seconds
Started Jul 07 05:46:44 PM PDT 24
Finished Jul 07 05:46:47 PM PDT 24
Peak memory 198764 kb
Host smart-f643009f-52b3-4d9e-83fe-757b5a63e824
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304801987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3304801987
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2179526742
Short name T208
Test name
Test status
Simulation time 114771848 ps
CPU time 2.67 seconds
Started Jul 07 05:46:40 PM PDT 24
Finished Jul 07 05:46:43 PM PDT 24
Peak memory 198776 kb
Host smart-eae59335-7a60-43bd-8486-fe7c9f522ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179526742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2179526742
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4022938119
Short name T609
Test name
Test status
Simulation time 121115748 ps
CPU time 1.42 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:39 PM PDT 24
Peak memory 197252 kb
Host smart-f4b909a4-d8df-44c7-b6d8-a8175ef3fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022938119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4022938119
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1525930623
Short name T218
Test name
Test status
Simulation time 105410981 ps
CPU time 1.08 seconds
Started Jul 07 05:46:45 PM PDT 24
Finished Jul 07 05:46:46 PM PDT 24
Peak memory 196740 kb
Host smart-35de4f65-2c94-4eca-a662-e2f118dc0a96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525930623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1525930623
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.248909811
Short name T619
Test name
Test status
Simulation time 117733801 ps
CPU time 5.36 seconds
Started Jul 07 05:46:41 PM PDT 24
Finished Jul 07 05:46:47 PM PDT 24
Peak memory 198696 kb
Host smart-ba1f5b67-7b22-41e2-844d-96b435ad65b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248909811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.248909811
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2040661335
Short name T398
Test name
Test status
Simulation time 176734919 ps
CPU time 1.29 seconds
Started Jul 07 05:46:43 PM PDT 24
Finished Jul 07 05:46:45 PM PDT 24
Peak memory 197548 kb
Host smart-2409a427-4d85-4e91-a53e-a3c498fee5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040661335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2040661335
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2668714142
Short name T632
Test name
Test status
Simulation time 102546665 ps
CPU time 0.74 seconds
Started Jul 07 05:46:38 PM PDT 24
Finished Jul 07 05:46:39 PM PDT 24
Peak memory 194796 kb
Host smart-49890b87-5c4c-4cf0-a3ee-e8e8ecb2ae30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668714142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2668714142
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.331276472
Short name T639
Test name
Test status
Simulation time 34285730648 ps
CPU time 203.57 seconds
Started Jul 07 05:46:45 PM PDT 24
Finished Jul 07 05:50:09 PM PDT 24
Peak memory 198796 kb
Host smart-38cc530f-50d3-4b2d-bc52-11c27ceda36b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331276472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.331276472
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.862385038
Short name T658
Test name
Test status
Simulation time 16923643 ps
CPU time 0.62 seconds
Started Jul 07 05:46:47 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 194876 kb
Host smart-bb50ee4b-8505-4e92-8a2e-b90e9a487b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862385038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.862385038
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1656643069
Short name T565
Test name
Test status
Simulation time 76553583 ps
CPU time 0.81 seconds
Started Jul 07 05:46:42 PM PDT 24
Finished Jul 07 05:46:44 PM PDT 24
Peak memory 196044 kb
Host smart-ed0db0f8-e488-477f-a6ed-aa94609b7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656643069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1656643069
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3734977133
Short name T657
Test name
Test status
Simulation time 813425261 ps
CPU time 15.92 seconds
Started Jul 07 05:46:43 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 197884 kb
Host smart-466e89c4-3df4-41bc-9565-50807ea91f7e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734977133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3734977133
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1240324010
Short name T250
Test name
Test status
Simulation time 58702889 ps
CPU time 0.87 seconds
Started Jul 07 05:46:51 PM PDT 24
Finished Jul 07 05:46:52 PM PDT 24
Peak memory 197200 kb
Host smart-16f8b8ce-6076-4ebb-a1d7-980a1fe0c0b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240324010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1240324010
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1397639395
Short name T485
Test name
Test status
Simulation time 460003464 ps
CPU time 1.39 seconds
Started Jul 07 05:46:45 PM PDT 24
Finished Jul 07 05:46:47 PM PDT 24
Peak memory 197224 kb
Host smart-760c69ed-9bc5-4c8b-9355-1a03cac4c993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397639395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1397639395
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3692841542
Short name T44
Test name
Test status
Simulation time 86724354 ps
CPU time 2 seconds
Started Jul 07 05:46:47 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 198756 kb
Host smart-16c091b4-f9ef-4882-97d2-4625a9428acd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692841542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3692841542
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3638056504
Short name T442
Test name
Test status
Simulation time 125262936 ps
CPU time 2.92 seconds
Started Jul 07 05:46:44 PM PDT 24
Finished Jul 07 05:46:47 PM PDT 24
Peak memory 197944 kb
Host smart-1699b97e-8168-4314-8fae-c320787580aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638056504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3638056504
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2983308308
Short name T320
Test name
Test status
Simulation time 43322069 ps
CPU time 1.11 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:46:48 PM PDT 24
Peak memory 196756 kb
Host smart-7ecfc128-85af-492d-b443-2a89b7a98bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983308308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2983308308
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2619314742
Short name T437
Test name
Test status
Simulation time 32680535 ps
CPU time 0.87 seconds
Started Jul 07 05:46:43 PM PDT 24
Finished Jul 07 05:46:44 PM PDT 24
Peak memory 197964 kb
Host smart-11f8c76e-4e77-4fd5-93a0-3d0a004c5761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619314742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2619314742
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3325236734
Short name T667
Test name
Test status
Simulation time 209013657 ps
CPU time 3.41 seconds
Started Jul 07 05:46:42 PM PDT 24
Finished Jul 07 05:46:46 PM PDT 24
Peak memory 198628 kb
Host smart-dffe98f1-073f-4eb6-8211-3f05e188e61b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325236734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3325236734
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4200801157
Short name T388
Test name
Test status
Simulation time 36508960 ps
CPU time 1.02 seconds
Started Jul 07 05:46:43 PM PDT 24
Finished Jul 07 05:46:44 PM PDT 24
Peak memory 196184 kb
Host smart-2f5d2e49-a895-4a93-9acf-f1fd4d6480e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200801157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4200801157
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.368171207
Short name T689
Test name
Test status
Simulation time 60277718 ps
CPU time 1.13 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:46:47 PM PDT 24
Peak memory 196476 kb
Host smart-fb2d7fe4-5f59-45cd-98a6-f8f5a273f0a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368171207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.368171207
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2054233158
Short name T256
Test name
Test status
Simulation time 199689691585 ps
CPU time 201.18 seconds
Started Jul 07 05:46:49 PM PDT 24
Finished Jul 07 05:50:10 PM PDT 24
Peak memory 198832 kb
Host smart-2544643b-0cc5-4cd9-a3e2-276d13164a67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054233158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2054233158
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3025514556
Short name T508
Test name
Test status
Simulation time 61316124 ps
CPU time 0.56 seconds
Started Jul 07 05:44:33 PM PDT 24
Finished Jul 07 05:44:34 PM PDT 24
Peak memory 194592 kb
Host smart-fad261ec-0ad5-4f9a-b849-534bb0044890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025514556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3025514556
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2528332821
Short name T414
Test name
Test status
Simulation time 20189193 ps
CPU time 0.74 seconds
Started Jul 07 05:44:33 PM PDT 24
Finished Jul 07 05:44:34 PM PDT 24
Peak memory 195952 kb
Host smart-84312952-1115-44ee-9f80-caefeb188d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528332821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2528332821
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2435469331
Short name T210
Test name
Test status
Simulation time 2795236097 ps
CPU time 26.5 seconds
Started Jul 07 05:44:30 PM PDT 24
Finished Jul 07 05:44:57 PM PDT 24
Peak memory 198792 kb
Host smart-7bee0017-fc5b-4e8b-9962-93f9def4ae14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435469331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2435469331
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4235370001
Short name T448
Test name
Test status
Simulation time 54804683 ps
CPU time 0.74 seconds
Started Jul 07 05:44:30 PM PDT 24
Finished Jul 07 05:44:31 PM PDT 24
Peak memory 195444 kb
Host smart-f86f9dd2-9d28-4b7d-ac24-fb3236e03a7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235370001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4235370001
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3534399977
Short name T295
Test name
Test status
Simulation time 53001047 ps
CPU time 0.68 seconds
Started Jul 07 05:44:32 PM PDT 24
Finished Jul 07 05:44:33 PM PDT 24
Peak memory 194908 kb
Host smart-b97bf7ac-4d79-4440-9634-71c59ff17fc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534399977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3534399977
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3861114666
Short name T382
Test name
Test status
Simulation time 98278128 ps
CPU time 3.75 seconds
Started Jul 07 05:44:30 PM PDT 24
Finished Jul 07 05:44:34 PM PDT 24
Peak memory 198700 kb
Host smart-73567e84-cfb5-4237-88ce-daf40864a23f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861114666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3861114666
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.29483037
Short name T293
Test name
Test status
Simulation time 217858972 ps
CPU time 3.31 seconds
Started Jul 07 05:44:34 PM PDT 24
Finished Jul 07 05:44:38 PM PDT 24
Peak memory 197592 kb
Host smart-6d571f17-8840-448d-90b4-8c58920d683d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29483037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.29483037
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3171596751
Short name T179
Test name
Test status
Simulation time 179480543 ps
CPU time 1.11 seconds
Started Jul 07 05:44:30 PM PDT 24
Finished Jul 07 05:44:32 PM PDT 24
Peak memory 196688 kb
Host smart-8aecbdf1-a389-4e17-a8ef-7f20a6a124ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171596751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3171596751
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3691113063
Short name T329
Test name
Test status
Simulation time 63504669 ps
CPU time 1.24 seconds
Started Jul 07 05:44:33 PM PDT 24
Finished Jul 07 05:44:35 PM PDT 24
Peak memory 196716 kb
Host smart-c8d231a6-c75a-4442-9d6b-f9f9a9507069
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691113063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3691113063
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1392441482
Short name T163
Test name
Test status
Simulation time 756548437 ps
CPU time 3.28 seconds
Started Jul 07 05:44:34 PM PDT 24
Finished Jul 07 05:44:37 PM PDT 24
Peak memory 198620 kb
Host smart-ef96c6d5-ce77-42b0-b25e-cb01c209c293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392441482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1392441482
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1889165184
Short name T47
Test name
Test status
Simulation time 110421733 ps
CPU time 0.76 seconds
Started Jul 07 05:44:38 PM PDT 24
Finished Jul 07 05:44:39 PM PDT 24
Peak memory 214308 kb
Host smart-1c5d0214-04af-4b90-81b5-750895cac414
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889165184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1889165184
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.440514604
Short name T351
Test name
Test status
Simulation time 85167664 ps
CPU time 1.1 seconds
Started Jul 07 05:44:27 PM PDT 24
Finished Jul 07 05:44:28 PM PDT 24
Peak memory 197104 kb
Host smart-f9c97bc5-2746-483d-8e9f-d93e13bc5a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440514604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.440514604
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3031241722
Short name T206
Test name
Test status
Simulation time 161738586 ps
CPU time 1.03 seconds
Started Jul 07 05:44:33 PM PDT 24
Finished Jul 07 05:44:35 PM PDT 24
Peak memory 197088 kb
Host smart-772ac65a-9b4b-4489-a7ac-06eac93077c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031241722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3031241722
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1932418368
Short name T628
Test name
Test status
Simulation time 29427690291 ps
CPU time 100.99 seconds
Started Jul 07 05:44:38 PM PDT 24
Finished Jul 07 05:46:19 PM PDT 24
Peak memory 198824 kb
Host smart-3605eb2e-052c-4b99-9189-c6df769294fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932418368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1932418368
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3247821217
Short name T31
Test name
Test status
Simulation time 62890105700 ps
CPU time 1173.95 seconds
Started Jul 07 05:44:36 PM PDT 24
Finished Jul 07 06:04:11 PM PDT 24
Peak memory 198880 kb
Host smart-85c80f63-024c-4379-8873-a4a616e06350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3247821217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3247821217
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.597669315
Short name T223
Test name
Test status
Simulation time 25158276 ps
CPU time 0.58 seconds
Started Jul 07 05:46:50 PM PDT 24
Finished Jul 07 05:46:51 PM PDT 24
Peak memory 195620 kb
Host smart-55db3dfb-9786-47a4-85f1-feea0728ecd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597669315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.597669315
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1868341441
Short name T126
Test name
Test status
Simulation time 48191629 ps
CPU time 0.97 seconds
Started Jul 07 05:46:50 PM PDT 24
Finished Jul 07 05:46:51 PM PDT 24
Peak memory 197456 kb
Host smart-acc11783-8d42-4757-805d-a8658967641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868341441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1868341441
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.822912807
Short name T687
Test name
Test status
Simulation time 1757481710 ps
CPU time 26.84 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:47:13 PM PDT 24
Peak memory 197456 kb
Host smart-a79900db-752c-44cf-8bb0-8e4e5b0d9931
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822912807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.822912807
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3790337498
Short name T618
Test name
Test status
Simulation time 49618654 ps
CPU time 0.87 seconds
Started Jul 07 05:46:49 PM PDT 24
Finished Jul 07 05:46:50 PM PDT 24
Peak memory 196720 kb
Host smart-fc243ffd-80e8-49f7-b389-6261f0382d07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790337498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3790337498
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3097283414
Short name T640
Test name
Test status
Simulation time 41311913 ps
CPU time 1.16 seconds
Started Jul 07 05:46:52 PM PDT 24
Finished Jul 07 05:46:53 PM PDT 24
Peak memory 196780 kb
Host smart-0cc6042a-4c86-45fe-9814-aa3c848b48e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097283414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3097283414
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4094859573
Short name T486
Test name
Test status
Simulation time 81012213 ps
CPU time 0.98 seconds
Started Jul 07 05:46:48 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 196768 kb
Host smart-5ab72f53-fcb5-400b-9b38-dce3c38da09c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094859573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4094859573
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.120810384
Short name T467
Test name
Test status
Simulation time 242252164 ps
CPU time 3.88 seconds
Started Jul 07 05:46:53 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 197872 kb
Host smart-22bf19e7-aa3a-4193-8d6d-880bc9fd9795
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120810384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
120810384
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.611570244
Short name T560
Test name
Test status
Simulation time 32262450 ps
CPU time 1.19 seconds
Started Jul 07 05:46:48 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 197532 kb
Host smart-8200c9be-e557-49f6-81f4-6bf85720c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611570244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.611570244
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3402328830
Short name T583
Test name
Test status
Simulation time 71473009 ps
CPU time 1.36 seconds
Started Jul 07 05:46:47 PM PDT 24
Finished Jul 07 05:46:48 PM PDT 24
Peak memory 197748 kb
Host smart-e1fea4b2-65ef-4b74-9ca3-82c8119be231
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402328830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3402328830
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1014459053
Short name T144
Test name
Test status
Simulation time 63856615 ps
CPU time 3.13 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:46:49 PM PDT 24
Peak memory 198660 kb
Host smart-b7c59d20-69c6-461d-93eb-80f7b48be1a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014459053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1014459053
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.4040699453
Short name T510
Test name
Test status
Simulation time 116026989 ps
CPU time 1.13 seconds
Started Jul 07 05:46:53 PM PDT 24
Finished Jul 07 05:46:55 PM PDT 24
Peak memory 196356 kb
Host smart-32e206b6-7bb4-498a-b968-b45137512a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040699453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.4040699453
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1622504180
Short name T105
Test name
Test status
Simulation time 262545869 ps
CPU time 1.16 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:46:48 PM PDT 24
Peak memory 196688 kb
Host smart-dc3ab75f-68bf-4903-b086-a1068792b15d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622504180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1622504180
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.301267848
Short name T394
Test name
Test status
Simulation time 267458692087 ps
CPU time 208.98 seconds
Started Jul 07 05:46:46 PM PDT 24
Finished Jul 07 05:50:16 PM PDT 24
Peak memory 198732 kb
Host smart-ac774ee9-73d7-4b33-88da-a9f6cd1527d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301267848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.301267848
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1986191018
Short name T461
Test name
Test status
Simulation time 27242875372 ps
CPU time 409.99 seconds
Started Jul 07 05:46:53 PM PDT 24
Finished Jul 07 05:53:43 PM PDT 24
Peak memory 198952 kb
Host smart-cba2e36b-5e67-4bd0-bc43-f420951defed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1986191018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1986191018
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.12325144
Short name T683
Test name
Test status
Simulation time 13862239 ps
CPU time 0.57 seconds
Started Jul 07 05:46:49 PM PDT 24
Finished Jul 07 05:46:50 PM PDT 24
Peak memory 195352 kb
Host smart-246e4180-3072-4b98-84b9-965d2963d0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12325144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.12325144
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2356197744
Short name T129
Test name
Test status
Simulation time 26623414 ps
CPU time 0.72 seconds
Started Jul 07 05:46:56 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 194736 kb
Host smart-2390ffea-57c0-4443-9654-c8e3d321f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356197744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2356197744
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3272826351
Short name T681
Test name
Test status
Simulation time 411458940 ps
CPU time 10.89 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:47:08 PM PDT 24
Peak memory 196224 kb
Host smart-4a0f5cdd-4f3f-498a-b719-132a786b866c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272826351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3272826351
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.702175349
Short name T304
Test name
Test status
Simulation time 89635684 ps
CPU time 0.97 seconds
Started Jul 07 05:46:50 PM PDT 24
Finished Jul 07 05:46:51 PM PDT 24
Peak memory 197808 kb
Host smart-3efc80c5-5c68-4482-a16c-346406c2fe98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702175349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.702175349
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.12240981
Short name T685
Test name
Test status
Simulation time 92245672 ps
CPU time 1.35 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 197872 kb
Host smart-1b0a9d61-bcda-41ea-9af1-eaf70dc3af19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12240981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.12240981
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1626160350
Short name T499
Test name
Test status
Simulation time 223990786 ps
CPU time 2.74 seconds
Started Jul 07 05:46:51 PM PDT 24
Finished Jul 07 05:46:54 PM PDT 24
Peak memory 198816 kb
Host smart-de9164cf-bea2-4c16-b5d5-707658ad43a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626160350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1626160350
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.707371398
Short name T234
Test name
Test status
Simulation time 54175790 ps
CPU time 0.91 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:58 PM PDT 24
Peak memory 196760 kb
Host smart-c58c08cb-4e07-42b0-a705-2a1ba2faa4f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707371398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
707371398
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3647517610
Short name T449
Test name
Test status
Simulation time 95352875 ps
CPU time 1.4 seconds
Started Jul 07 05:46:49 PM PDT 24
Finished Jul 07 05:46:51 PM PDT 24
Peak memory 196688 kb
Host smart-ceaf1f13-f13d-4550-b3e6-68c26041a237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647517610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3647517610
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.194476562
Short name T631
Test name
Test status
Simulation time 157074593 ps
CPU time 1.06 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 196740 kb
Host smart-ec321927-fe87-4994-90d9-9fc3e2f272ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194476562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.194476562
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.775873298
Short name T578
Test name
Test status
Simulation time 115854568 ps
CPU time 5.26 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:47:03 PM PDT 24
Peak memory 198664 kb
Host smart-e9dc8d28-0644-47f0-8b7d-62f69b8adcb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775873298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.775873298
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3419241227
Short name T309
Test name
Test status
Simulation time 94810318 ps
CPU time 1.51 seconds
Started Jul 07 05:46:54 PM PDT 24
Finished Jul 07 05:46:55 PM PDT 24
Peak memory 196328 kb
Host smart-60b031c0-6a68-433a-89d9-02a8b6f41181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419241227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3419241227
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1720460155
Short name T327
Test name
Test status
Simulation time 150780983 ps
CPU time 1.28 seconds
Started Jul 07 05:46:55 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 197040 kb
Host smart-3e462933-55c8-49cc-be36-c0c292896d2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720460155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1720460155
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2627323683
Short name T525
Test name
Test status
Simulation time 10981171025 ps
CPU time 153.87 seconds
Started Jul 07 05:46:52 PM PDT 24
Finished Jul 07 05:49:26 PM PDT 24
Peak memory 198860 kb
Host smart-da820a3d-405b-4bc1-b120-126eab8952eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627323683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2627323683
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2912472473
Short name T249
Test name
Test status
Simulation time 14451030 ps
CPU time 0.58 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:58 PM PDT 24
Peak memory 194680 kb
Host smart-03bd9bb4-c63e-434a-b66c-2fcf45f14699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912472473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2912472473
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1909465783
Short name T524
Test name
Test status
Simulation time 26728763 ps
CPU time 0.64 seconds
Started Jul 07 05:46:56 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 195320 kb
Host smart-b93828f4-0ed2-4c02-affb-5f087fb61097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909465783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1909465783
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.454815859
Short name T519
Test name
Test status
Simulation time 477940334 ps
CPU time 4.46 seconds
Started Jul 07 05:46:56 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 196604 kb
Host smart-02b0b4fd-d7a6-4046-a9e1-f45c96e0f24b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454815859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.454815859
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2575956267
Short name T387
Test name
Test status
Simulation time 296844026 ps
CPU time 0.83 seconds
Started Jul 07 05:46:52 PM PDT 24
Finished Jul 07 05:46:53 PM PDT 24
Peak memory 196672 kb
Host smart-542159d6-a9a6-46b8-8154-5de26e40fc42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575956267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2575956267
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2092740100
Short name T215
Test name
Test status
Simulation time 88145480 ps
CPU time 1.29 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:58 PM PDT 24
Peak memory 195832 kb
Host smart-6c980177-9158-4999-8bdf-95dd681ced37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092740100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2092740100
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.406066905
Short name T623
Test name
Test status
Simulation time 39016244 ps
CPU time 1.83 seconds
Started Jul 07 05:46:53 PM PDT 24
Finished Jul 07 05:46:55 PM PDT 24
Peak memory 197340 kb
Host smart-00ce6df2-5cde-492c-91ad-c491aac8f629
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406066905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.406066905
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1537474094
Short name T626
Test name
Test status
Simulation time 116345326 ps
CPU time 0.98 seconds
Started Jul 07 05:46:52 PM PDT 24
Finished Jul 07 05:46:53 PM PDT 24
Peak memory 196964 kb
Host smart-e27d8baf-1108-4d4f-9547-8b22e6173fe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537474094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1537474094
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1985602460
Short name T11
Test name
Test status
Simulation time 29022664 ps
CPU time 1.08 seconds
Started Jul 07 05:46:54 PM PDT 24
Finished Jul 07 05:46:55 PM PDT 24
Peak memory 196524 kb
Host smart-e947037c-9942-4980-9a89-1bd85f987d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985602460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1985602460
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2346579686
Short name T248
Test name
Test status
Simulation time 124455510 ps
CPU time 0.92 seconds
Started Jul 07 05:46:55 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 197364 kb
Host smart-d4dff9df-dc4a-4a7e-ae8e-c55d0e720e3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346579686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2346579686
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1334532580
Short name T591
Test name
Test status
Simulation time 222805244 ps
CPU time 1.55 seconds
Started Jul 07 05:46:53 PM PDT 24
Finished Jul 07 05:46:55 PM PDT 24
Peak memory 198624 kb
Host smart-86657597-4328-4bac-96e1-b52c397f6e88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334532580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1334532580
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3892058683
Short name T417
Test name
Test status
Simulation time 128968094 ps
CPU time 1.3 seconds
Started Jul 07 05:46:56 PM PDT 24
Finished Jul 07 05:46:58 PM PDT 24
Peak memory 197548 kb
Host smart-244c55cd-100c-4a40-92ba-ef7c409ea5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892058683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3892058683
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3224943124
Short name T155
Test name
Test status
Simulation time 89503558 ps
CPU time 1.02 seconds
Started Jul 07 05:46:55 PM PDT 24
Finished Jul 07 05:46:57 PM PDT 24
Peak memory 196216 kb
Host smart-41ce4d7d-c08b-42aa-8202-6b600e88aaac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224943124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3224943124
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1176028964
Short name T190
Test name
Test status
Simulation time 5392866668 ps
CPU time 38.45 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 198776 kb
Host smart-d78a7cf4-9b08-48a1-a62e-94a26bc646e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176028964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1176028964
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1708149302
Short name T90
Test name
Test status
Simulation time 34479155856 ps
CPU time 289.29 seconds
Started Jul 07 05:47:00 PM PDT 24
Finished Jul 07 05:51:49 PM PDT 24
Peak memory 198940 kb
Host smart-300a920e-563d-4152-b86b-890b51814eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1708149302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1708149302
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3718581365
Short name T443
Test name
Test status
Simulation time 66405331 ps
CPU time 0.6 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:02 PM PDT 24
Peak memory 194660 kb
Host smart-bc3db401-656d-4584-8f93-cea606650fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718581365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3718581365
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3001501014
Short name T488
Test name
Test status
Simulation time 113773520 ps
CPU time 0.79 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 196036 kb
Host smart-840a222c-9bcb-454c-a5ad-f229b09e7c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001501014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3001501014
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3304932316
Short name T527
Test name
Test status
Simulation time 1163455441 ps
CPU time 17.07 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:18 PM PDT 24
Peak memory 197580 kb
Host smart-21ab76fd-218e-46d5-87a5-18c77f4dd2c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304932316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3304932316
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.692514798
Short name T212
Test name
Test status
Simulation time 238245658 ps
CPU time 0.75 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 197244 kb
Host smart-59190ee8-d247-4386-a170-b4afa2e81bbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692514798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.692514798
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3059543872
Short name T675
Test name
Test status
Simulation time 89288372 ps
CPU time 1.26 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 197372 kb
Host smart-7df33f3c-f963-4218-b3c9-629c9dec03fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059543872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3059543872
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1269041801
Short name T643
Test name
Test status
Simulation time 112399388 ps
CPU time 2.09 seconds
Started Jul 07 05:47:00 PM PDT 24
Finished Jul 07 05:47:03 PM PDT 24
Peak memory 197200 kb
Host smart-e73dfc73-fb13-4596-bb2b-f64756a7cfc3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269041801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1269041801
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3287927215
Short name T385
Test name
Test status
Simulation time 277638656 ps
CPU time 2.5 seconds
Started Jul 07 05:47:00 PM PDT 24
Finished Jul 07 05:47:03 PM PDT 24
Peak memory 198740 kb
Host smart-932e8010-4227-4a6d-baed-55a8d6712e64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287927215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3287927215
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4290593419
Short name T317
Test name
Test status
Simulation time 262285536 ps
CPU time 1.12 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 196812 kb
Host smart-e72e502c-3ff8-43a4-9f14-be6ef805339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290593419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4290593419
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2971378716
Short name T240
Test name
Test status
Simulation time 23764213 ps
CPU time 0.71 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 195600 kb
Host smart-116bc888-4c68-4a0a-871b-8d7a20627faf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971378716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2971378716
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.4223137785
Short name T389
Test name
Test status
Simulation time 956038717 ps
CPU time 4.59 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 05:47:03 PM PDT 24
Peak memory 198464 kb
Host smart-c45b9a85-95f3-4ea1-ad4b-0078d95302ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223137785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.4223137785
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.703959213
Short name T700
Test name
Test status
Simulation time 222005124 ps
CPU time 0.86 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 197068 kb
Host smart-b54f106a-5140-441a-a705-1a7d3eec4a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703959213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.703959213
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1214740216
Short name T19
Test name
Test status
Simulation time 71038254 ps
CPU time 1.38 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 197092 kb
Host smart-bcb5cb8d-215e-412b-926c-d9ce3201cc39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214740216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1214740216
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3201652761
Short name T526
Test name
Test status
Simulation time 2327269553 ps
CPU time 59.75 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:47:57 PM PDT 24
Peak memory 198696 kb
Host smart-51ad8d13-019d-48f3-9c69-26152eb2a24b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201652761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3201652761
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3420259228
Short name T652
Test name
Test status
Simulation time 63082206322 ps
CPU time 1241.22 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 06:07:40 PM PDT 24
Peak memory 198964 kb
Host smart-dc72c18b-d0eb-40ad-9c0f-429fc3f75948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3420259228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3420259228
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1845216537
Short name T469
Test name
Test status
Simulation time 13590491 ps
CPU time 0.57 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:02 PM PDT 24
Peak memory 194696 kb
Host smart-02a18cd1-89f2-4e93-960a-dee36ad0776f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845216537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1845216537
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3848009268
Short name T378
Test name
Test status
Simulation time 20465386 ps
CPU time 0.74 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:02 PM PDT 24
Peak memory 194752 kb
Host smart-52d234c7-b233-49df-98b9-932cfeb2f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848009268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3848009268
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3576362178
Short name T547
Test name
Test status
Simulation time 146540180 ps
CPU time 6.87 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:08 PM PDT 24
Peak memory 197628 kb
Host smart-ebe085af-f0d0-441f-91ec-718993a3088f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576362178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3576362178
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2252080618
Short name T415
Test name
Test status
Simulation time 28495548 ps
CPU time 0.75 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:02 PM PDT 24
Peak memory 195296 kb
Host smart-31a267ae-4991-47a3-b64c-11422abb47d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252080618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2252080618
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3950004905
Short name T222
Test name
Test status
Simulation time 382089725 ps
CPU time 1.32 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:58 PM PDT 24
Peak memory 196448 kb
Host smart-8dc6d885-0548-434c-ae39-fbe89d72d4d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950004905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3950004905
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2645182834
Short name T235
Test name
Test status
Simulation time 52794960 ps
CPU time 2.21 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 196996 kb
Host smart-f8f685e5-5cdb-4af6-a7f1-ed4c9b5f6913
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645182834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2645182834
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1495535385
Short name T616
Test name
Test status
Simulation time 87860472 ps
CPU time 1.8 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 196548 kb
Host smart-146dd379-b138-4de5-b37b-b1a3aeba49f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495535385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1495535385
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.61062204
Short name T458
Test name
Test status
Simulation time 53677413 ps
CPU time 0.7 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 195948 kb
Host smart-5dad4fce-c1b1-4680-9b39-4cf65bf7d8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61062204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.61062204
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.982140171
Short name T278
Test name
Test status
Simulation time 25546692 ps
CPU time 0.77 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 195836 kb
Host smart-c46d4c23-b82d-46b8-8e42-f9dae18a9e66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982140171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.982140171
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2348974477
Short name T315
Test name
Test status
Simulation time 128543979 ps
CPU time 1.65 seconds
Started Jul 07 05:47:05 PM PDT 24
Finished Jul 07 05:47:07 PM PDT 24
Peak memory 198636 kb
Host smart-ba02a181-731b-42ec-8bed-a6f2cdd45f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348974477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2348974477
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1502327686
Short name T216
Test name
Test status
Simulation time 323254901 ps
CPU time 1.37 seconds
Started Jul 07 05:46:58 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 197404 kb
Host smart-8e405592-9a05-466e-9148-213a5a45c67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502327686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1502327686
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.165165275
Short name T478
Test name
Test status
Simulation time 122114845 ps
CPU time 0.77 seconds
Started Jul 07 05:46:57 PM PDT 24
Finished Jul 07 05:46:59 PM PDT 24
Peak memory 195844 kb
Host smart-7d7558c0-10ed-430d-8064-4b16d9da573e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165165275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.165165275
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.209144844
Short name T551
Test name
Test status
Simulation time 4875329418 ps
CPU time 64.44 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:48:04 PM PDT 24
Peak memory 198760 kb
Host smart-fd1816a2-877a-4e79-9c6e-885c0dbf6268
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209144844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.209144844
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2805533110
Short name T598
Test name
Test status
Simulation time 46595239641 ps
CPU time 468.09 seconds
Started Jul 07 05:47:02 PM PDT 24
Finished Jul 07 05:54:51 PM PDT 24
Peak memory 198804 kb
Host smart-8d14cf03-0aef-42ea-b8b1-ebf08226b41c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2805533110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2805533110
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2208829534
Short name T228
Test name
Test status
Simulation time 11467067 ps
CPU time 0.59 seconds
Started Jul 07 05:47:03 PM PDT 24
Finished Jul 07 05:47:04 PM PDT 24
Peak memory 194600 kb
Host smart-c357156b-c305-4f9a-8ce0-72beee9584e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208829534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2208829534
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.486894688
Short name T102
Test name
Test status
Simulation time 16046888 ps
CPU time 0.66 seconds
Started Jul 07 05:46:59 PM PDT 24
Finished Jul 07 05:47:00 PM PDT 24
Peak memory 194748 kb
Host smart-38084393-9ef8-43f8-ab70-d48c0bb80e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486894688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.486894688
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2013632822
Short name T345
Test name
Test status
Simulation time 1472861366 ps
CPU time 25.47 seconds
Started Jul 07 05:47:06 PM PDT 24
Finished Jul 07 05:47:32 PM PDT 24
Peak memory 197484 kb
Host smart-448d19f3-e5b2-4860-b1ec-b2651d504cbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013632822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2013632822
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.17191745
Short name T22
Test name
Test status
Simulation time 78771113 ps
CPU time 0.77 seconds
Started Jul 07 05:47:03 PM PDT 24
Finished Jul 07 05:47:04 PM PDT 24
Peak memory 195360 kb
Host smart-d95628d4-e8a0-4596-90d1-843370902021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17191745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.17191745
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1410175096
Short name T534
Test name
Test status
Simulation time 25991819 ps
CPU time 0.78 seconds
Started Jul 07 05:47:04 PM PDT 24
Finished Jul 07 05:47:05 PM PDT 24
Peak memory 196176 kb
Host smart-b11d6179-4f4a-472f-96b6-5c26b935a387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410175096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1410175096
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2382827840
Short name T339
Test name
Test status
Simulation time 127328014 ps
CPU time 1.48 seconds
Started Jul 07 05:47:05 PM PDT 24
Finished Jul 07 05:47:07 PM PDT 24
Peak memory 197600 kb
Host smart-8e4e78fe-9a94-424f-a6aa-ebc80d713cf4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382827840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2382827840
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1056308625
Short name T323
Test name
Test status
Simulation time 116619617 ps
CPU time 3.41 seconds
Started Jul 07 05:47:08 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 197816 kb
Host smart-d7ae3b9e-416b-419c-862c-31ae37befe79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056308625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1056308625
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1726488822
Short name T185
Test name
Test status
Simulation time 45192034 ps
CPU time 1.02 seconds
Started Jul 07 05:47:04 PM PDT 24
Finished Jul 07 05:47:05 PM PDT 24
Peak memory 197424 kb
Host smart-86bb3c79-704d-42fc-9f48-61c25c18d4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726488822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1726488822
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3732482237
Short name T319
Test name
Test status
Simulation time 27496014 ps
CPU time 1.11 seconds
Started Jul 07 05:47:01 PM PDT 24
Finished Jul 07 05:47:03 PM PDT 24
Peak memory 197484 kb
Host smart-4f39c0be-5a9b-4eb4-8177-3b167ee8849e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732482237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3732482237
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1128191911
Short name T122
Test name
Test status
Simulation time 452245672 ps
CPU time 4.85 seconds
Started Jul 07 05:47:04 PM PDT 24
Finished Jul 07 05:47:09 PM PDT 24
Peak memory 198624 kb
Host smart-351cab8d-78cf-4902-ad0a-1e3546a17823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128191911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1128191911
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.890910909
Short name T338
Test name
Test status
Simulation time 33985568 ps
CPU time 0.83 seconds
Started Jul 07 05:47:04 PM PDT 24
Finished Jul 07 05:47:05 PM PDT 24
Peak memory 196004 kb
Host smart-870b61b3-89bb-431c-b9cb-fafa9cd12a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890910909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.890910909
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1354732464
Short name T433
Test name
Test status
Simulation time 122907163 ps
CPU time 0.98 seconds
Started Jul 07 05:47:03 PM PDT 24
Finished Jul 07 05:47:04 PM PDT 24
Peak memory 196148 kb
Host smart-e4519153-5bef-49ab-b771-0bea1503df4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354732464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1354732464
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1412909102
Short name T462
Test name
Test status
Simulation time 13078582548 ps
CPU time 47.94 seconds
Started Jul 07 05:47:10 PM PDT 24
Finished Jul 07 05:47:58 PM PDT 24
Peak memory 198788 kb
Host smart-6014dc41-cde3-445d-b0e1-4a92357696b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412909102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1412909102
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2396236939
Short name T366
Test name
Test status
Simulation time 85482574 ps
CPU time 0.54 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:11 PM PDT 24
Peak memory 193432 kb
Host smart-4938695f-2c46-49bb-96ee-edae6ad9e5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396236939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2396236939
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4144701417
Short name T52
Test name
Test status
Simulation time 135974363 ps
CPU time 0.8 seconds
Started Jul 07 05:47:09 PM PDT 24
Finished Jul 07 05:47:10 PM PDT 24
Peak memory 196000 kb
Host smart-8f1491bd-e0b3-4ffb-998f-8044fd4e0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144701417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4144701417
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.527516216
Short name T233
Test name
Test status
Simulation time 1382557395 ps
CPU time 17.93 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 197792 kb
Host smart-721d8bfd-17a7-45fc-8b1e-3c2640c48c8b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527516216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.527516216
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3604173099
Short name T405
Test name
Test status
Simulation time 56928492 ps
CPU time 0.9 seconds
Started Jul 07 05:47:10 PM PDT 24
Finished Jul 07 05:47:11 PM PDT 24
Peak memory 197480 kb
Host smart-1725b774-2d27-44ba-a905-a29d354b0607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604173099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3604173099
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2327854131
Short name T408
Test name
Test status
Simulation time 161093561 ps
CPU time 1.26 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:14 PM PDT 24
Peak memory 196820 kb
Host smart-f525b59f-20d4-4290-8b31-4eef0643e479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327854131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2327854131
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.585552881
Short name T164
Test name
Test status
Simulation time 508921461 ps
CPU time 3.42 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:17 PM PDT 24
Peak memory 198688 kb
Host smart-898be8f5-8a1b-4735-ad6e-928f7600037f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585552881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.585552881
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2393894863
Short name T359
Test name
Test status
Simulation time 68438633 ps
CPU time 2.37 seconds
Started Jul 07 05:47:05 PM PDT 24
Finished Jul 07 05:47:08 PM PDT 24
Peak memory 197708 kb
Host smart-8e6bfcb5-b1f2-463f-9f75-6a44a9e18854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393894863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2393894863
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2857054047
Short name T624
Test name
Test status
Simulation time 80877456 ps
CPU time 1.2 seconds
Started Jul 07 05:47:07 PM PDT 24
Finished Jul 07 05:47:09 PM PDT 24
Peak memory 196780 kb
Host smart-84525b6e-c13c-4395-9663-44146370c6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857054047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2857054047
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2174092896
Short name T625
Test name
Test status
Simulation time 190702664 ps
CPU time 0.86 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 196608 kb
Host smart-e97b897d-8a20-4122-a0ff-b708d87e7c1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174092896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2174092896
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2471216713
Short name T307
Test name
Test status
Simulation time 93927474 ps
CPU time 4.24 seconds
Started Jul 07 05:47:09 PM PDT 24
Finished Jul 07 05:47:14 PM PDT 24
Peak memory 198588 kb
Host smart-cddfff53-aaa8-4590-b61a-20b25e39f3de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471216713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2471216713
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.642486209
Short name T707
Test name
Test status
Simulation time 43689537 ps
CPU time 1.24 seconds
Started Jul 07 05:47:04 PM PDT 24
Finished Jul 07 05:47:05 PM PDT 24
Peak memory 196536 kb
Host smart-b4e206ce-b9ca-4da8-963f-31942715cb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642486209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.642486209
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1814375696
Short name T392
Test name
Test status
Simulation time 108673904 ps
CPU time 1.13 seconds
Started Jul 07 05:47:04 PM PDT 24
Finished Jul 07 05:47:06 PM PDT 24
Peak memory 196188 kb
Host smart-e3b4c826-0f02-44bc-b5ac-3844046e9a4b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814375696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1814375696
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3294235079
Short name T302
Test name
Test status
Simulation time 58200665224 ps
CPU time 227.25 seconds
Started Jul 07 05:47:09 PM PDT 24
Finished Jul 07 05:50:57 PM PDT 24
Peak memory 198804 kb
Host smart-88e17c98-59b1-4f6c-bef2-3070e0410455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294235079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3294235079
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1124259340
Short name T555
Test name
Test status
Simulation time 37078999215 ps
CPU time 1179.59 seconds
Started Jul 07 05:47:09 PM PDT 24
Finished Jul 07 06:06:49 PM PDT 24
Peak memory 198920 kb
Host smart-8a0eef04-e839-483f-9cb5-d5c9a684f9fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1124259340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1124259340
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2749420015
Short name T224
Test name
Test status
Simulation time 13326435 ps
CPU time 0.58 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 195360 kb
Host smart-aa08f2a5-b8d6-4f25-a123-25c1fc1ca954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749420015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2749420015
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2386711772
Short name T237
Test name
Test status
Simulation time 84237337 ps
CPU time 0.69 seconds
Started Jul 07 05:47:12 PM PDT 24
Finished Jul 07 05:47:13 PM PDT 24
Peak memory 194768 kb
Host smart-333aee1f-6a39-4ce8-96ef-c870062fd7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386711772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2386711772
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3887652530
Short name T522
Test name
Test status
Simulation time 747411933 ps
CPU time 12.66 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:24 PM PDT 24
Peak memory 197216 kb
Host smart-f79a8b7e-9a36-44b8-9f3a-bf980a879200
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887652530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3887652530
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.511642993
Short name T26
Test name
Test status
Simulation time 122753714 ps
CPU time 0.78 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 196200 kb
Host smart-a801614c-e3c6-4c7d-a74e-6154d58c69b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511642993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.511642993
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3403390390
Short name T373
Test name
Test status
Simulation time 56742122 ps
CPU time 1.03 seconds
Started Jul 07 05:47:10 PM PDT 24
Finished Jul 07 05:47:11 PM PDT 24
Peak memory 196568 kb
Host smart-4e7acfee-9b64-4833-a154-0e46c5c17a88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403390390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3403390390
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.548497599
Short name T141
Test name
Test status
Simulation time 152595301 ps
CPU time 3.36 seconds
Started Jul 07 05:47:14 PM PDT 24
Finished Jul 07 05:47:18 PM PDT 24
Peak memory 198728 kb
Host smart-89d93448-495a-43b6-b40c-995a3a778b66
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548497599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.548497599
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.590321860
Short name T133
Test name
Test status
Simulation time 68321569 ps
CPU time 2.18 seconds
Started Jul 07 05:47:12 PM PDT 24
Finished Jul 07 05:47:14 PM PDT 24
Peak memory 198772 kb
Host smart-2ab2bb55-ea6e-47d9-aeef-4acbde260ed4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590321860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
590321860
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.213155325
Short name T332
Test name
Test status
Simulation time 43601756 ps
CPU time 1.09 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 196664 kb
Host smart-adc44b3c-7960-4af4-b445-131bddf001f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213155325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.213155325
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1216813834
Short name T521
Test name
Test status
Simulation time 61114005 ps
CPU time 1.19 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:14 PM PDT 24
Peak memory 196744 kb
Host smart-013c2e0e-f8fa-4017-89e6-bc3eda82e227
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216813834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1216813834
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2015719130
Short name T429
Test name
Test status
Simulation time 791543908 ps
CPU time 3.62 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:17 PM PDT 24
Peak memory 198692 kb
Host smart-f4ab3eb8-886f-470a-93ed-f542e7e22914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015719130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2015719130
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1427258988
Short name T121
Test name
Test status
Simulation time 212063912 ps
CPU time 1.12 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:15 PM PDT 24
Peak memory 196496 kb
Host smart-19991a40-8d89-4c7a-9da7-6b62894b243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427258988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1427258988
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4023281978
Short name T596
Test name
Test status
Simulation time 316030371 ps
CPU time 1.29 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:14 PM PDT 24
Peak memory 198696 kb
Host smart-f358c838-11db-4fb5-91bd-0dbbe7b42a22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023281978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4023281978
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3680983120
Short name T646
Test name
Test status
Simulation time 80997632663 ps
CPU time 218.58 seconds
Started Jul 07 05:47:16 PM PDT 24
Finished Jul 07 05:50:54 PM PDT 24
Peak memory 198832 kb
Host smart-0aefd7b4-b6a6-4e79-9095-eab1ab01c522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680983120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3680983120
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2949589464
Short name T336
Test name
Test status
Simulation time 23785628 ps
CPU time 0.61 seconds
Started Jul 07 05:47:17 PM PDT 24
Finished Jul 07 05:47:18 PM PDT 24
Peak memory 194644 kb
Host smart-9be1884c-5699-4a5e-8685-a5bbac236ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949589464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2949589464
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.989415807
Short name T98
Test name
Test status
Simulation time 31192896 ps
CPU time 0.7 seconds
Started Jul 07 05:47:12 PM PDT 24
Finished Jul 07 05:47:13 PM PDT 24
Peak memory 196548 kb
Host smart-8d173f5e-5a6c-42d3-879e-ad447bbef2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989415807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.989415807
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.872807452
Short name T426
Test name
Test status
Simulation time 617219803 ps
CPU time 4.75 seconds
Started Jul 07 05:47:20 PM PDT 24
Finished Jul 07 05:47:25 PM PDT 24
Peak memory 197448 kb
Host smart-d48f0fcd-2cb0-4207-8d01-f1c08939aea0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872807452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.872807452
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3593847130
Short name T450
Test name
Test status
Simulation time 247392611 ps
CPU time 1.04 seconds
Started Jul 07 05:47:20 PM PDT 24
Finished Jul 07 05:47:22 PM PDT 24
Peak memory 197136 kb
Host smart-c765882b-e474-4d1a-be7d-7d9170c278bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593847130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3593847130
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1236891644
Short name T145
Test name
Test status
Simulation time 91123385 ps
CPU time 0.76 seconds
Started Jul 07 05:47:12 PM PDT 24
Finished Jul 07 05:47:13 PM PDT 24
Peak memory 196172 kb
Host smart-d5559e3d-dbc7-4f60-946c-ef4fe263c40f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236891644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1236891644
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.4116420479
Short name T708
Test name
Test status
Simulation time 72943699 ps
CPU time 2.81 seconds
Started Jul 07 05:47:18 PM PDT 24
Finished Jul 07 05:47:21 PM PDT 24
Peak memory 198772 kb
Host smart-3baf7680-0646-49a8-96e0-c8a6551d43e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116420479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.4116420479
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1185161118
Short name T225
Test name
Test status
Simulation time 241719211 ps
CPU time 2.87 seconds
Started Jul 07 05:47:09 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 198004 kb
Host smart-38a97660-1ad6-4a43-b058-8a7747145b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185161118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1185161118
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3684023330
Short name T568
Test name
Test status
Simulation time 146986647 ps
CPU time 1.43 seconds
Started Jul 07 05:47:14 PM PDT 24
Finished Jul 07 05:47:15 PM PDT 24
Peak memory 197672 kb
Host smart-1b1efd49-0d20-4818-96f5-bd5acd315411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684023330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3684023330
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3562744740
Short name T140
Test name
Test status
Simulation time 69310521 ps
CPU time 1.33 seconds
Started Jul 07 05:47:14 PM PDT 24
Finished Jul 07 05:47:15 PM PDT 24
Peak memory 197716 kb
Host smart-9b09c365-6903-4708-b4a2-c94295715c75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562744740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3562744740
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3284937672
Short name T601
Test name
Test status
Simulation time 2412256960 ps
CPU time 3.56 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:17 PM PDT 24
Peak memory 198752 kb
Host smart-401dfd58-4547-4ce9-9bb8-83e275fda90d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284937672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3284937672
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1180504930
Short name T344
Test name
Test status
Simulation time 128655050 ps
CPU time 1.31 seconds
Started Jul 07 05:47:11 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 196344 kb
Host smart-6276258a-edca-4e0f-a6e9-a8b6143d51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180504930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1180504930
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3817512982
Short name T612
Test name
Test status
Simulation time 79704158 ps
CPU time 1.49 seconds
Started Jul 07 05:47:10 PM PDT 24
Finished Jul 07 05:47:11 PM PDT 24
Peak memory 198696 kb
Host smart-fbcb6098-c1f2-49d5-b22d-1e0e14786268
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817512982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3817512982
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2355100506
Short name T243
Test name
Test status
Simulation time 9441872942 ps
CPU time 126.69 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:49:28 PM PDT 24
Peak memory 198836 kb
Host smart-b732aabf-16cb-40a5-b534-4fe857fc0ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355100506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2355100506
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3563899167
Short name T63
Test name
Test status
Simulation time 514068509910 ps
CPU time 1427.55 seconds
Started Jul 07 05:47:14 PM PDT 24
Finished Jul 07 06:11:02 PM PDT 24
Peak memory 207128 kb
Host smart-31a5182a-60ce-4756-987c-c2c5bc67f4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3563899167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3563899167
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.890188607
Short name T279
Test name
Test status
Simulation time 46125368 ps
CPU time 0.58 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:22 PM PDT 24
Peak memory 195556 kb
Host smart-f925ab06-7b59-4d38-896e-7bf8dec9ae92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890188607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.890188607
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1243958896
Short name T123
Test name
Test status
Simulation time 21873002 ps
CPU time 0.81 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 195968 kb
Host smart-d41700a0-dc53-4963-b62d-2b12799d9a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243958896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1243958896
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4090639642
Short name T286
Test name
Test status
Simulation time 2850875484 ps
CPU time 20.45 seconds
Started Jul 07 05:47:17 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 197684 kb
Host smart-0f4ec5c5-1310-4cce-b6ea-0a1ab5141ed0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090639642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4090639642
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.859421103
Short name T542
Test name
Test status
Simulation time 194327694 ps
CPU time 0.93 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 197740 kb
Host smart-edb22745-4e34-49ce-9814-12068bf1922f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859421103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.859421103
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3186422229
Short name T518
Test name
Test status
Simulation time 429277346 ps
CPU time 1.4 seconds
Started Jul 07 05:47:15 PM PDT 24
Finished Jul 07 05:47:16 PM PDT 24
Peak memory 197700 kb
Host smart-dd3cbe36-5541-4ccd-acfb-a6c5b5d5606e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186422229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3186422229
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3428592927
Short name T441
Test name
Test status
Simulation time 189177703 ps
CPU time 1.4 seconds
Started Jul 07 05:47:14 PM PDT 24
Finished Jul 07 05:47:16 PM PDT 24
Peak memory 197472 kb
Host smart-4b46357d-8e6b-4a18-a56e-ead6487019d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428592927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3428592927
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1124546604
Short name T355
Test name
Test status
Simulation time 340172212 ps
CPU time 1.87 seconds
Started Jul 07 05:47:14 PM PDT 24
Finished Jul 07 05:47:16 PM PDT 24
Peak memory 196728 kb
Host smart-28205d68-7932-408d-8f39-17fa0d7cad8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124546604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1124546604
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1034057514
Short name T531
Test name
Test status
Simulation time 65159557 ps
CPU time 1.26 seconds
Started Jul 07 05:47:19 PM PDT 24
Finished Jul 07 05:47:20 PM PDT 24
Peak memory 197272 kb
Host smart-6907d1b2-83de-4638-b7be-119ad8507415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034057514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1034057514
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3204933799
Short name T53
Test name
Test status
Simulation time 29472241 ps
CPU time 0.83 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 196096 kb
Host smart-cd4d453d-fe01-4adf-9e67-fae3835efbea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204933799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3204933799
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.296906107
Short name T539
Test name
Test status
Simulation time 116416982 ps
CPU time 2.69 seconds
Started Jul 07 05:47:17 PM PDT 24
Finished Jul 07 05:47:20 PM PDT 24
Peak memory 198660 kb
Host smart-22932a5e-2c53-4c65-a922-c047c32b62b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296906107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.296906107
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1649063792
Short name T713
Test name
Test status
Simulation time 44622641 ps
CPU time 0.88 seconds
Started Jul 07 05:47:20 PM PDT 24
Finished Jul 07 05:47:21 PM PDT 24
Peak memory 197112 kb
Host smart-2875d009-db77-4391-b0d3-3b49ee68ba72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649063792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1649063792
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.263869397
Short name T318
Test name
Test status
Simulation time 257884717 ps
CPU time 1.52 seconds
Started Jul 07 05:47:13 PM PDT 24
Finished Jul 07 05:47:15 PM PDT 24
Peak memory 197432 kb
Host smart-7830732a-b9cc-4017-833f-131e0527d936
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263869397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.263869397
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3667552085
Short name T487
Test name
Test status
Simulation time 7897245754 ps
CPU time 91.93 seconds
Started Jul 07 05:47:17 PM PDT 24
Finished Jul 07 05:48:49 PM PDT 24
Peak memory 198792 kb
Host smart-d302a7d5-02ce-4639-a931-3f7cc32e4581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667552085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3667552085
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.346524712
Short name T409
Test name
Test status
Simulation time 36731931 ps
CPU time 0.58 seconds
Started Jul 07 05:44:40 PM PDT 24
Finished Jul 07 05:44:41 PM PDT 24
Peak memory 194656 kb
Host smart-671d6794-7c62-4358-850a-11108fa8d293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346524712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.346524712
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2087297953
Short name T434
Test name
Test status
Simulation time 177486038 ps
CPU time 0.86 seconds
Started Jul 07 05:44:39 PM PDT 24
Finished Jul 07 05:44:40 PM PDT 24
Peak memory 196108 kb
Host smart-284731dc-48d0-4289-b038-562290577dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087297953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2087297953
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1042814533
Short name T671
Test name
Test status
Simulation time 290265949 ps
CPU time 14.74 seconds
Started Jul 07 05:44:37 PM PDT 24
Finished Jul 07 05:44:52 PM PDT 24
Peak memory 196220 kb
Host smart-047b562d-9f89-427a-bd6c-ba22251a9650
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042814533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1042814533
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1088752861
Short name T7
Test name
Test status
Simulation time 62055633 ps
CPU time 0.8 seconds
Started Jul 07 05:44:44 PM PDT 24
Finished Jul 07 05:44:45 PM PDT 24
Peak memory 196728 kb
Host smart-6175fce2-a6d0-4bde-a56a-dc43a47e5112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088752861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1088752861
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1932172605
Short name T217
Test name
Test status
Simulation time 384098973 ps
CPU time 1.33 seconds
Started Jul 07 05:44:36 PM PDT 24
Finished Jul 07 05:44:38 PM PDT 24
Peak memory 197500 kb
Host smart-068a407a-4a61-421c-a620-ff2b329c1e44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932172605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1932172605
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1540186802
Short name T120
Test name
Test status
Simulation time 72650460 ps
CPU time 1.52 seconds
Started Jul 07 05:44:41 PM PDT 24
Finished Jul 07 05:44:43 PM PDT 24
Peak memory 197256 kb
Host smart-3c432d6c-92fd-4cb6-ad0e-da5c2c9445ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540186802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1540186802
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1017628581
Short name T637
Test name
Test status
Simulation time 184591519 ps
CPU time 1.7 seconds
Started Jul 07 05:44:41 PM PDT 24
Finished Jul 07 05:44:43 PM PDT 24
Peak memory 196684 kb
Host smart-f1f253f4-3819-4e40-8e19-160257b36a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017628581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1017628581
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3128476407
Short name T362
Test name
Test status
Simulation time 25724429 ps
CPU time 0.72 seconds
Started Jul 07 05:44:43 PM PDT 24
Finished Jul 07 05:44:44 PM PDT 24
Peak memory 196044 kb
Host smart-c8435153-27f7-48ed-903a-3997b7953fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128476407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3128476407
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2118095191
Short name T104
Test name
Test status
Simulation time 47560621 ps
CPU time 1.18 seconds
Started Jul 07 05:44:40 PM PDT 24
Finished Jul 07 05:44:42 PM PDT 24
Peak memory 196832 kb
Host smart-24d90c1d-f7a4-4350-84bb-2002c57608ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118095191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2118095191
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2332250010
Short name T55
Test name
Test status
Simulation time 333652698 ps
CPU time 4.32 seconds
Started Jul 07 05:44:41 PM PDT 24
Finished Jul 07 05:44:46 PM PDT 24
Peak memory 198664 kb
Host smart-c5062369-4ee0-4abb-8f13-17299a8900a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332250010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2332250010
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.411361175
Short name T291
Test name
Test status
Simulation time 65400229 ps
CPU time 1.24 seconds
Started Jul 07 05:44:48 PM PDT 24
Finished Jul 07 05:44:50 PM PDT 24
Peak memory 197160 kb
Host smart-8ecc0011-1812-4ee9-b5ad-1699b88ef0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411361175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.411361175
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3208972327
Short name T630
Test name
Test status
Simulation time 45746617 ps
CPU time 1.23 seconds
Started Jul 07 05:44:37 PM PDT 24
Finished Jul 07 05:44:38 PM PDT 24
Peak memory 197688 kb
Host smart-ca179427-d8c7-400e-b3c4-476dd31b5fc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208972327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3208972327
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1785169816
Short name T259
Test name
Test status
Simulation time 18790640891 ps
CPU time 173.14 seconds
Started Jul 07 05:44:40 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 198812 kb
Host smart-702aed12-ab71-4af6-9557-b80babd61755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785169816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1785169816
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3201235438
Short name T533
Test name
Test status
Simulation time 11442227 ps
CPU time 0.54 seconds
Started Jul 07 05:44:48 PM PDT 24
Finished Jul 07 05:44:49 PM PDT 24
Peak memory 193416 kb
Host smart-3b6aab9e-cced-46c3-bfc3-64fad0d9f531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201235438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3201235438
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3377497335
Short name T585
Test name
Test status
Simulation time 91137325 ps
CPU time 0.65 seconds
Started Jul 07 05:44:50 PM PDT 24
Finished Jul 07 05:44:51 PM PDT 24
Peak memory 195412 kb
Host smart-336e7fb8-37f0-473e-9bb1-212fbf83a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377497335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3377497335
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1999327718
Short name T642
Test name
Test status
Simulation time 335496610 ps
CPU time 15.39 seconds
Started Jul 07 05:44:48 PM PDT 24
Finished Jul 07 05:45:04 PM PDT 24
Peak memory 198544 kb
Host smart-5570cb05-79f5-498c-bc77-f2504812f241
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999327718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1999327718
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2251520469
Short name T491
Test name
Test status
Simulation time 119900780 ps
CPU time 0.95 seconds
Started Jul 07 05:44:50 PM PDT 24
Finished Jul 07 05:44:51 PM PDT 24
Peak memory 197800 kb
Host smart-527e222a-0a85-4944-9b67-4ad4b27a2d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251520469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2251520469
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.349457443
Short name T692
Test name
Test status
Simulation time 174256362 ps
CPU time 0.88 seconds
Started Jul 07 05:44:45 PM PDT 24
Finished Jul 07 05:44:46 PM PDT 24
Peak memory 196112 kb
Host smart-9aeaa017-64fc-462f-9ea0-82232a585725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349457443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.349457443
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.206429768
Short name T96
Test name
Test status
Simulation time 228125942 ps
CPU time 2.3 seconds
Started Jul 07 05:44:50 PM PDT 24
Finished Jul 07 05:44:53 PM PDT 24
Peak memory 198748 kb
Host smart-fddc384f-433b-40c3-87bc-1ca21d1f90bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206429768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.206429768
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.101441773
Short name T701
Test name
Test status
Simulation time 433347086 ps
CPU time 1.43 seconds
Started Jul 07 05:44:44 PM PDT 24
Finished Jul 07 05:44:46 PM PDT 24
Peak memory 196744 kb
Host smart-a2021a39-8284-4bcb-9ac3-55815250259a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101441773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.101441773
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.129553194
Short name T353
Test name
Test status
Simulation time 111966683 ps
CPU time 1.11 seconds
Started Jul 07 05:44:42 PM PDT 24
Finished Jul 07 05:44:44 PM PDT 24
Peak memory 196676 kb
Host smart-1d965b28-c475-4ef9-a931-9b5ad30b9b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129553194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.129553194
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.260483020
Short name T182
Test name
Test status
Simulation time 27883498 ps
CPU time 0.75 seconds
Started Jul 07 05:44:43 PM PDT 24
Finished Jul 07 05:44:44 PM PDT 24
Peak memory 196084 kb
Host smart-62d2ea96-c514-4f09-87d1-7b6d8dfdc36b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260483020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.260483020
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3338147661
Short name T303
Test name
Test status
Simulation time 152469769 ps
CPU time 2.09 seconds
Started Jul 07 05:44:57 PM PDT 24
Finished Jul 07 05:44:59 PM PDT 24
Peak memory 198604 kb
Host smart-250f82eb-ba35-464f-8654-c7f135ee1995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338147661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3338147661
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1414139560
Short name T477
Test name
Test status
Simulation time 64724292 ps
CPU time 1.13 seconds
Started Jul 07 05:44:45 PM PDT 24
Finished Jul 07 05:44:46 PM PDT 24
Peak memory 196464 kb
Host smart-12e8cda2-46b5-4a64-9b83-870824e784eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414139560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1414139560
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3299112080
Short name T137
Test name
Test status
Simulation time 597135325 ps
CPU time 1.29 seconds
Started Jul 07 05:44:41 PM PDT 24
Finished Jul 07 05:44:43 PM PDT 24
Peak memory 197572 kb
Host smart-4bc443f6-0352-40a8-8958-ed50eaa040de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299112080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3299112080
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2944160678
Short name T6
Test name
Test status
Simulation time 2065370405 ps
CPU time 21.98 seconds
Started Jul 07 05:44:42 PM PDT 24
Finished Jul 07 05:45:04 PM PDT 24
Peak memory 198748 kb
Host smart-a92df4ec-6696-42b1-af89-00d846ff918b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944160678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2944160678
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.635784078
Short name T45
Test name
Test status
Simulation time 43349056 ps
CPU time 0.6 seconds
Started Jul 07 05:44:52 PM PDT 24
Finished Jul 07 05:44:53 PM PDT 24
Peak memory 195548 kb
Host smart-ad1dd622-a767-48f4-86f3-9dc397c317f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635784078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.635784078
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3672860718
Short name T267
Test name
Test status
Simulation time 26062474 ps
CPU time 0.9 seconds
Started Jul 07 05:44:59 PM PDT 24
Finished Jul 07 05:45:00 PM PDT 24
Peak memory 197896 kb
Host smart-051363a9-a169-407f-b63d-2ea1df02cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672860718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3672860718
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.644035091
Short name T103
Test name
Test status
Simulation time 2190708204 ps
CPU time 17.84 seconds
Started Jul 07 05:44:46 PM PDT 24
Finished Jul 07 05:45:04 PM PDT 24
Peak memory 196952 kb
Host smart-83e28fec-cfc3-435e-bb81-5daab5c45631
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644035091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.644035091
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.181573306
Short name T597
Test name
Test status
Simulation time 179290183 ps
CPU time 0.84 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:50 PM PDT 24
Peak memory 196536 kb
Host smart-8f2949c2-cf43-42d7-a5aa-6165c5d6ba33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181573306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.181573306
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3181207720
Short name T573
Test name
Test status
Simulation time 1135639702 ps
CPU time 1.21 seconds
Started Jul 07 05:44:45 PM PDT 24
Finished Jul 07 05:44:47 PM PDT 24
Peak memory 197484 kb
Host smart-ebe79dca-3aaa-41f5-8c7f-44f4c9b01f86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181207720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3181207720
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3844856794
Short name T125
Test name
Test status
Simulation time 52089783 ps
CPU time 1.32 seconds
Started Jul 07 05:44:43 PM PDT 24
Finished Jul 07 05:44:44 PM PDT 24
Peak memory 197160 kb
Host smart-07ed0942-f243-44e3-8081-4f481139c716
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844856794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3844856794
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1349419436
Short name T397
Test name
Test status
Simulation time 251632953 ps
CPU time 3.3 seconds
Started Jul 07 05:44:46 PM PDT 24
Finished Jul 07 05:44:49 PM PDT 24
Peak memory 198668 kb
Host smart-3e845a1b-8aec-4f16-9b1d-24fd75b26872
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349419436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1349419436
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.327983775
Short name T158
Test name
Test status
Simulation time 66788365 ps
CPU time 0.96 seconds
Started Jul 07 05:44:44 PM PDT 24
Finished Jul 07 05:44:45 PM PDT 24
Peak memory 196688 kb
Host smart-fa2b4ad9-46c2-4a2c-a240-b78d8a8143e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327983775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.327983775
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2556452392
Short name T613
Test name
Test status
Simulation time 27414420 ps
CPU time 1.03 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:50 PM PDT 24
Peak memory 196724 kb
Host smart-e9474b23-6f87-47f0-93b8-4dd8d51584dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556452392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2556452392
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.169097654
Short name T483
Test name
Test status
Simulation time 30341799 ps
CPU time 1.55 seconds
Started Jul 07 05:44:42 PM PDT 24
Finished Jul 07 05:44:44 PM PDT 24
Peak memory 198640 kb
Host smart-85573479-f68f-437f-93ef-4409649e679c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169097654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.169097654
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.717804628
Short name T301
Test name
Test status
Simulation time 871482876 ps
CPU time 1.19 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:50 PM PDT 24
Peak memory 196440 kb
Host smart-32d237e1-39fb-4d27-8989-c472c1c39910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717804628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.717804628
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1469397413
Short name T255
Test name
Test status
Simulation time 286414060 ps
CPU time 1.24 seconds
Started Jul 07 05:44:45 PM PDT 24
Finished Jul 07 05:44:46 PM PDT 24
Peak memory 197164 kb
Host smart-3c382c4a-1767-41aa-a6a0-6e3a27696229
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469397413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1469397413
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.903287652
Short name T111
Test name
Test status
Simulation time 29996848576 ps
CPU time 55.49 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:45:45 PM PDT 24
Peak memory 198716 kb
Host smart-f476f815-91af-44d8-ab60-aaef8943c3c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903287652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.903287652
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3726668277
Short name T446
Test name
Test status
Simulation time 60859288 ps
CPU time 0.58 seconds
Started Jul 07 05:44:51 PM PDT 24
Finished Jul 07 05:44:52 PM PDT 24
Peak memory 195624 kb
Host smart-847350ea-35c8-461e-be58-a8c8d35a9620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726668277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3726668277
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2324879792
Short name T119
Test name
Test status
Simulation time 39752026 ps
CPU time 0.91 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:51 PM PDT 24
Peak memory 197268 kb
Host smart-7bb57886-7cdf-41c1-a996-e6e8b9863807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324879792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2324879792
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2200096514
Short name T186
Test name
Test status
Simulation time 177579678 ps
CPU time 6.77 seconds
Started Jul 07 05:44:52 PM PDT 24
Finished Jul 07 05:44:59 PM PDT 24
Peak memory 197500 kb
Host smart-91fb593a-4bb5-458c-9830-4c53e4e8587d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200096514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2200096514
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2294429645
Short name T471
Test name
Test status
Simulation time 165390007 ps
CPU time 1.1 seconds
Started Jul 07 05:44:54 PM PDT 24
Finished Jul 07 05:44:55 PM PDT 24
Peak memory 198520 kb
Host smart-72b385c4-b3ca-4e39-8a40-4cf1aa64a6ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294429645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2294429645
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2070189043
Short name T188
Test name
Test status
Simulation time 199007209 ps
CPU time 0.85 seconds
Started Jul 07 05:44:46 PM PDT 24
Finished Jul 07 05:44:48 PM PDT 24
Peak memory 196320 kb
Host smart-b784c5f2-3d81-44ed-b82f-6f1e3fcc1706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070189043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2070189043
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1314282775
Short name T402
Test name
Test status
Simulation time 166691651 ps
CPU time 1.84 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:51 PM PDT 24
Peak memory 198748 kb
Host smart-085cdb1a-9e0d-42f8-9364-cf7974493ad2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314282775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1314282775
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1481073408
Short name T538
Test name
Test status
Simulation time 291702933 ps
CPU time 3.55 seconds
Started Jul 07 05:44:48 PM PDT 24
Finished Jul 07 05:44:51 PM PDT 24
Peak memory 196528 kb
Host smart-2d4579ec-303d-46c8-a199-8831d1a49d88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481073408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1481073408
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2725759118
Short name T107
Test name
Test status
Simulation time 23285575 ps
CPU time 0.93 seconds
Started Jul 07 05:44:50 PM PDT 24
Finished Jul 07 05:44:52 PM PDT 24
Peak memory 196704 kb
Host smart-488731d6-997c-482a-8975-684ef2ed67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725759118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2725759118
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3907547156
Short name T428
Test name
Test status
Simulation time 47066854 ps
CPU time 0.84 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:50 PM PDT 24
Peak memory 197372 kb
Host smart-2137b1fd-2ceb-44cc-a2ed-d3376cf84594
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907547156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3907547156
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3344783094
Short name T5
Test name
Test status
Simulation time 483160754 ps
CPU time 5.79 seconds
Started Jul 07 05:44:52 PM PDT 24
Finished Jul 07 05:44:58 PM PDT 24
Peak memory 198660 kb
Host smart-255d76ee-49f7-4371-b299-6dbc018c602a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344783094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3344783094
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3218117637
Short name T558
Test name
Test status
Simulation time 122898017 ps
CPU time 1.25 seconds
Started Jul 07 05:44:49 PM PDT 24
Finished Jul 07 05:44:50 PM PDT 24
Peak memory 197372 kb
Host smart-d4b7e4de-a747-4f1b-9644-dacf6ebf07ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218117637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3218117637
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.412322944
Short name T600
Test name
Test status
Simulation time 21390235 ps
CPU time 0.69 seconds
Started Jul 07 05:44:47 PM PDT 24
Finished Jul 07 05:44:48 PM PDT 24
Peak memory 194812 kb
Host smart-d7620624-7501-4e9c-bf3e-ea74786cc7ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412322944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.412322944
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2839324459
Short name T430
Test name
Test status
Simulation time 94227569778 ps
CPU time 138.61 seconds
Started Jul 07 05:44:53 PM PDT 24
Finished Jul 07 05:47:12 PM PDT 24
Peak memory 198828 kb
Host smart-12147434-f12b-4c1a-9d17-e862d5986631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839324459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2839324459
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1066911225
Short name T57
Test name
Test status
Simulation time 60290489329 ps
CPU time 1557.19 seconds
Started Jul 07 05:44:51 PM PDT 24
Finished Jul 07 06:10:48 PM PDT 24
Peak memory 198960 kb
Host smart-4fffeb17-c33a-4bfc-b68d-7004da5ffce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1066911225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1066911225
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3985055339
Short name T682
Test name
Test status
Simulation time 16890890 ps
CPU time 0.59 seconds
Started Jul 07 05:44:59 PM PDT 24
Finished Jul 07 05:45:00 PM PDT 24
Peak memory 194652 kb
Host smart-ec6e1033-fd15-4b6c-a14a-8df7fc03b4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985055339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3985055339
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1778656784
Short name T236
Test name
Test status
Simulation time 131934018 ps
CPU time 0.72 seconds
Started Jul 07 05:44:57 PM PDT 24
Finished Jul 07 05:44:58 PM PDT 24
Peak memory 195804 kb
Host smart-4170625a-0e3f-4686-ba4a-07ebe50e0c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778656784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1778656784
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.41031442
Short name T431
Test name
Test status
Simulation time 930974298 ps
CPU time 20.29 seconds
Started Jul 07 05:44:59 PM PDT 24
Finished Jul 07 05:45:20 PM PDT 24
Peak memory 196216 kb
Host smart-182ab7ff-6b17-491c-a60b-3774e0921b6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress.41031442
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3609579768
Short name T143
Test name
Test status
Simulation time 47664881 ps
CPU time 0.65 seconds
Started Jul 07 05:44:57 PM PDT 24
Finished Jul 07 05:44:58 PM PDT 24
Peak memory 195112 kb
Host smart-5d3303a8-1b74-4e9a-a742-af61427c6bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609579768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3609579768
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3734689522
Short name T473
Test name
Test status
Simulation time 346929202 ps
CPU time 1.32 seconds
Started Jul 07 05:44:56 PM PDT 24
Finished Jul 07 05:44:58 PM PDT 24
Peak memory 196792 kb
Host smart-1ce59c66-57ce-420b-b00d-5d31950f6851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734689522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3734689522
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1364883226
Short name T595
Test name
Test status
Simulation time 77026365 ps
CPU time 2.89 seconds
Started Jul 07 05:44:54 PM PDT 24
Finished Jul 07 05:44:57 PM PDT 24
Peak memory 198692 kb
Host smart-e84d7f15-8dc4-41ec-9e02-de0002dc452e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364883226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1364883226
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3419138263
Short name T342
Test name
Test status
Simulation time 378493280 ps
CPU time 2.3 seconds
Started Jul 07 05:44:52 PM PDT 24
Finished Jul 07 05:44:54 PM PDT 24
Peak memory 196496 kb
Host smart-b6f6dffd-e2d9-4c35-9660-76f6c25e1d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419138263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3419138263
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.108298613
Short name T611
Test name
Test status
Simulation time 223486455 ps
CPU time 1.32 seconds
Started Jul 07 05:44:53 PM PDT 24
Finished Jul 07 05:44:54 PM PDT 24
Peak memory 197308 kb
Host smart-2dc522e4-aba8-43b2-a6a8-af8b8891413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108298613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.108298613
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3402392394
Short name T645
Test name
Test status
Simulation time 129530722 ps
CPU time 0.94 seconds
Started Jul 07 05:44:54 PM PDT 24
Finished Jul 07 05:44:56 PM PDT 24
Peak memory 197296 kb
Host smart-f7bddadb-7177-42da-8897-a4ec28eb70bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402392394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3402392394
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.296737236
Short name T213
Test name
Test status
Simulation time 704455328 ps
CPU time 3.18 seconds
Started Jul 07 05:44:59 PM PDT 24
Finished Jul 07 05:45:03 PM PDT 24
Peak memory 198604 kb
Host smart-70105448-9e32-432b-806a-54b266118ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296737236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.296737236
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3026356489
Short name T321
Test name
Test status
Simulation time 179853649 ps
CPU time 1.39 seconds
Started Jul 07 05:44:51 PM PDT 24
Finished Jul 07 05:44:52 PM PDT 24
Peak memory 197476 kb
Host smart-83a00518-6bfa-4cf6-95fc-3dff09fe86ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026356489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3026356489
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1909798289
Short name T606
Test name
Test status
Simulation time 109190832 ps
CPU time 1.07 seconds
Started Jul 07 05:44:56 PM PDT 24
Finished Jul 07 05:44:57 PM PDT 24
Peak memory 196440 kb
Host smart-030a5f5e-ffa4-463b-ba3e-628550fafc24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909798289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1909798289
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2969598484
Short name T877
Test name
Test status
Simulation time 79909126 ps
CPU time 1.09 seconds
Started Jul 07 05:47:19 PM PDT 24
Finished Jul 07 05:47:21 PM PDT 24
Peak memory 197108 kb
Host smart-da4e2016-3588-4e40-824a-ca0a0e7a82f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2969598484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2969598484
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.693652376
Short name T921
Test name
Test status
Simulation time 48517272 ps
CPU time 1.14 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 196968 kb
Host smart-579ffb0c-8969-4bbd-89a9-14c7cd401424
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693652376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.693652376
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.390048682
Short name T904
Test name
Test status
Simulation time 99064684 ps
CPU time 0.95 seconds
Started Jul 07 05:47:18 PM PDT 24
Finished Jul 07 05:47:20 PM PDT 24
Peak memory 196252 kb
Host smart-48f25161-62c1-42b0-93f9-2681d864d0a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=390048682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.390048682
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.201156749
Short name T927
Test name
Test status
Simulation time 54651679 ps
CPU time 1.44 seconds
Started Jul 07 05:47:20 PM PDT 24
Finished Jul 07 05:47:22 PM PDT 24
Peak memory 198428 kb
Host smart-87a19a4c-a786-4e1a-b06d-7a9a08b05bec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201156749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.201156749
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3457190224
Short name T916
Test name
Test status
Simulation time 281310778 ps
CPU time 1.19 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 196996 kb
Host smart-6658ed99-a406-43f1-bad7-521d348d0b4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3457190224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3457190224
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2873050285
Short name T887
Test name
Test status
Simulation time 39228250 ps
CPU time 0.87 seconds
Started Jul 07 05:47:22 PM PDT 24
Finished Jul 07 05:47:24 PM PDT 24
Peak memory 197760 kb
Host smart-70fb2b6f-0a0b-4981-94da-bb963ae4c1a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873050285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2873050285
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1487108640
Short name T872
Test name
Test status
Simulation time 319700600 ps
CPU time 1.35 seconds
Started Jul 07 05:47:24 PM PDT 24
Finished Jul 07 05:47:25 PM PDT 24
Peak memory 197388 kb
Host smart-f68f1afc-1e57-43ba-a6ea-96a112a05fd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1487108640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1487108640
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3483995655
Short name T919
Test name
Test status
Simulation time 161180486 ps
CPU time 0.99 seconds
Started Jul 07 05:47:26 PM PDT 24
Finished Jul 07 05:47:27 PM PDT 24
Peak memory 196988 kb
Host smart-098105c6-5996-4b69-899d-731b3032c125
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483995655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3483995655
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3431908070
Short name T888
Test name
Test status
Simulation time 52075899 ps
CPU time 0.97 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 197172 kb
Host smart-f3c3f095-7c30-4090-8665-2bd3b58139af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3431908070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3431908070
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.979877801
Short name T941
Test name
Test status
Simulation time 72698320 ps
CPU time 1.34 seconds
Started Jul 07 05:47:26 PM PDT 24
Finished Jul 07 05:47:28 PM PDT 24
Peak memory 197292 kb
Host smart-4002571c-34af-4cd9-b7bd-5a556315f637
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979877801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.979877801
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2929732682
Short name T853
Test name
Test status
Simulation time 72732677 ps
CPU time 1.33 seconds
Started Jul 07 05:47:25 PM PDT 24
Finished Jul 07 05:47:26 PM PDT 24
Peak memory 196964 kb
Host smart-730eba23-b140-4842-8372-d31465ea3705
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2929732682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2929732682
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3007917008
Short name T851
Test name
Test status
Simulation time 29123634 ps
CPU time 1.04 seconds
Started Jul 07 05:47:24 PM PDT 24
Finished Jul 07 05:47:26 PM PDT 24
Peak memory 197224 kb
Host smart-764a7ee9-7fdf-48a6-9989-2e4bf2ef7627
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007917008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3007917008
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1453822682
Short name T942
Test name
Test status
Simulation time 143861991 ps
CPU time 1.21 seconds
Started Jul 07 05:47:29 PM PDT 24
Finished Jul 07 05:47:31 PM PDT 24
Peak memory 197132 kb
Host smart-8c3d73a0-01a6-429d-a753-3bec4e4f17dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1453822682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1453822682
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2792730933
Short name T865
Test name
Test status
Simulation time 44173607 ps
CPU time 1.24 seconds
Started Jul 07 05:47:24 PM PDT 24
Finished Jul 07 05:47:25 PM PDT 24
Peak memory 197404 kb
Host smart-e969707e-c281-44c8-bfe5-7436d117cb44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792730933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2792730933
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1835382597
Short name T873
Test name
Test status
Simulation time 80741182 ps
CPU time 1.08 seconds
Started Jul 07 05:47:27 PM PDT 24
Finished Jul 07 05:47:28 PM PDT 24
Peak memory 196988 kb
Host smart-03d9d3d3-d18a-4c82-998b-3395dfca87f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1835382597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1835382597
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2481217023
Short name T861
Test name
Test status
Simulation time 393200577 ps
CPU time 1.29 seconds
Started Jul 07 05:47:27 PM PDT 24
Finished Jul 07 05:47:28 PM PDT 24
Peak memory 197064 kb
Host smart-c67d268d-8b75-4d7c-9677-f7ff7dcf106c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481217023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2481217023
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1149533655
Short name T943
Test name
Test status
Simulation time 25380455 ps
CPU time 0.87 seconds
Started Jul 07 05:47:27 PM PDT 24
Finished Jul 07 05:47:28 PM PDT 24
Peak memory 198304 kb
Host smart-b6187a6d-3d83-4c07-8186-29e2c41273d3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1149533655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1149533655
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2818770722
Short name T892
Test name
Test status
Simulation time 415584216 ps
CPU time 0.93 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 196948 kb
Host smart-c58adb44-5ab2-465b-84aa-d287c91b0347
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818770722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2818770722
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1422341121
Short name T931
Test name
Test status
Simulation time 104859953 ps
CPU time 0.79 seconds
Started Jul 07 05:47:29 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 195796 kb
Host smart-1859c497-50aa-4ca4-88eb-cf07e04205fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1422341121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1422341121
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2761178918
Short name T893
Test name
Test status
Simulation time 51421901 ps
CPU time 1.1 seconds
Started Jul 07 05:47:29 PM PDT 24
Finished Jul 07 05:47:31 PM PDT 24
Peak memory 197112 kb
Host smart-409b65a5-8a1e-40f2-a264-5e52774a0904
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761178918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2761178918
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.145304879
Short name T937
Test name
Test status
Simulation time 156147192 ps
CPU time 1.27 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 197264 kb
Host smart-fa883350-9a1c-4921-ab54-a4052592cd52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=145304879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.145304879
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3258618213
Short name T881
Test name
Test status
Simulation time 627541743 ps
CPU time 1.07 seconds
Started Jul 07 05:47:24 PM PDT 24
Finished Jul 07 05:47:26 PM PDT 24
Peak memory 198432 kb
Host smart-5cc78cc2-61bb-409f-8ce5-227fc78cb97a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258618213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3258618213
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2643748860
Short name T878
Test name
Test status
Simulation time 78529844 ps
CPU time 1.02 seconds
Started Jul 07 05:47:25 PM PDT 24
Finished Jul 07 05:47:26 PM PDT 24
Peak memory 192112 kb
Host smart-87672083-db7b-4396-83a4-3e1f476efd7a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2643748860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2643748860
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4035213019
Short name T894
Test name
Test status
Simulation time 55990073 ps
CPU time 1.02 seconds
Started Jul 07 05:47:25 PM PDT 24
Finished Jul 07 05:47:26 PM PDT 24
Peak memory 197180 kb
Host smart-aa265385-7ced-4f5e-a27b-538e0ab7d3db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035213019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4035213019
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1972730000
Short name T910
Test name
Test status
Simulation time 233778952 ps
CPU time 1.22 seconds
Started Jul 07 05:47:22 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 197300 kb
Host smart-85cf0b7a-d31b-4624-8f29-646d1c3b434d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1972730000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1972730000
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1028353898
Short name T895
Test name
Test status
Simulation time 82669329 ps
CPU time 1.39 seconds
Started Jul 07 05:47:19 PM PDT 24
Finished Jul 07 05:47:20 PM PDT 24
Peak memory 197384 kb
Host smart-f9551dfa-ad68-41f1-ac6a-6553cffb7da2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028353898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1028353898
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1289506909
Short name T859
Test name
Test status
Simulation time 47886969 ps
CPU time 0.98 seconds
Started Jul 07 05:47:30 PM PDT 24
Finished Jul 07 05:47:31 PM PDT 24
Peak memory 196100 kb
Host smart-4f5cd957-8d2a-4e73-8eff-45df4255a9a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1289506909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1289506909
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4100032214
Short name T899
Test name
Test status
Simulation time 115128683 ps
CPU time 0.97 seconds
Started Jul 07 05:47:27 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 197724 kb
Host smart-bef88046-48c8-48c8-bb7d-9e13ca15dfb5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100032214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4100032214
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2119006689
Short name T918
Test name
Test status
Simulation time 178585251 ps
CPU time 1.29 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 197120 kb
Host smart-f9f79a9d-1740-4e95-94cf-79e13ccd1915
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2119006689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2119006689
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.521517909
Short name T917
Test name
Test status
Simulation time 682747905 ps
CPU time 1.18 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 197140 kb
Host smart-7a653a93-af40-4246-918a-5769abdc7a9c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521517909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.521517909
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3126725789
Short name T848
Test name
Test status
Simulation time 84827409 ps
CPU time 0.83 seconds
Started Jul 07 05:47:29 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 195856 kb
Host smart-6ddffe61-23a7-41fa-809d-2b644aa00600
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3126725789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3126725789
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3644940283
Short name T913
Test name
Test status
Simulation time 373832792 ps
CPU time 1.51 seconds
Started Jul 07 05:47:32 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 197156 kb
Host smart-3de7a92d-f001-4dc1-b8d3-28a0abdbefee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644940283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3644940283
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.664627612
Short name T914
Test name
Test status
Simulation time 30231456 ps
CPU time 0.69 seconds
Started Jul 07 05:47:32 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 195404 kb
Host smart-41f0bc97-74a8-404b-b54b-80009afc680a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=664627612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.664627612
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4152472286
Short name T875
Test name
Test status
Simulation time 140798039 ps
CPU time 1.39 seconds
Started Jul 07 05:47:31 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 197008 kb
Host smart-56b9f4f1-8ca0-4182-97f0-d64b3264345e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152472286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4152472286
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2189008638
Short name T880
Test name
Test status
Simulation time 82172853 ps
CPU time 0.8 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:34 PM PDT 24
Peak memory 195840 kb
Host smart-ee2e6aac-acf9-4006-acea-f4682c739247
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2189008638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2189008638
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.154491954
Short name T911
Test name
Test status
Simulation time 70032917 ps
CPU time 1.08 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:36 PM PDT 24
Peak memory 196344 kb
Host smart-7c0bb50c-5d8e-4963-a39d-ecad94c1a8f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154491954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.154491954
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1468378884
Short name T885
Test name
Test status
Simulation time 291220193 ps
CPU time 0.98 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 197820 kb
Host smart-c33fc253-c300-4079-b387-d8f2706f8110
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1468378884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1468378884
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.770983933
Short name T912
Test name
Test status
Simulation time 188148539 ps
CPU time 1.21 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 197068 kb
Host smart-a66daf98-d0bb-45fc-abbb-0f77540443cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770983933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.770983933
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3800380551
Short name T922
Test name
Test status
Simulation time 152635919 ps
CPU time 1.08 seconds
Started Jul 07 05:47:27 PM PDT 24
Finished Jul 07 05:47:29 PM PDT 24
Peak memory 196984 kb
Host smart-947dabf5-e130-4393-b3a5-69a63b9e03b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3800380551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3800380551
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2118667481
Short name T854
Test name
Test status
Simulation time 58039544 ps
CPU time 0.89 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:36 PM PDT 24
Peak memory 196228 kb
Host smart-21d5a3d2-500c-4723-b99f-e1f304eccae6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118667481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2118667481
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1926830626
Short name T924
Test name
Test status
Simulation time 122922788 ps
CPU time 1.36 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 196948 kb
Host smart-315d514d-e71b-4e86-b8b9-54577a203852
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1926830626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1926830626
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.900502424
Short name T903
Test name
Test status
Simulation time 101427844 ps
CPU time 1.08 seconds
Started Jul 07 05:47:32 PM PDT 24
Finished Jul 07 05:47:34 PM PDT 24
Peak memory 197220 kb
Host smart-0fd2867d-74d6-4338-a7aa-8a79b348392b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900502424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.900502424
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1513866776
Short name T850
Test name
Test status
Simulation time 202158633 ps
CPU time 0.95 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 195644 kb
Host smart-2ffcfbf2-7b1f-4b53-b3a8-3f00da4db394
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1513866776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1513866776
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4075961502
Short name T867
Test name
Test status
Simulation time 38434064 ps
CPU time 0.87 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 195884 kb
Host smart-a74deab1-6235-46ca-90f7-28418a358d99
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075961502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4075961502
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1469493173
Short name T882
Test name
Test status
Simulation time 38008740 ps
CPU time 0.89 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 195928 kb
Host smart-3d171b74-fd41-4d92-8701-508aa20587db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1469493173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1469493173
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1680908211
Short name T936
Test name
Test status
Simulation time 47562059 ps
CPU time 1.23 seconds
Started Jul 07 05:47:31 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 196080 kb
Host smart-13b10c0a-df66-436b-81fe-68ec6536ad7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680908211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1680908211
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3054475972
Short name T906
Test name
Test status
Simulation time 35203776 ps
CPU time 1.05 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 196196 kb
Host smart-a1ffc527-f654-489b-b0fe-1a5daad8ac77
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3054475972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3054475972
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.668794421
Short name T909
Test name
Test status
Simulation time 38858089 ps
CPU time 1.07 seconds
Started Jul 07 05:47:20 PM PDT 24
Finished Jul 07 05:47:22 PM PDT 24
Peak memory 196336 kb
Host smart-88023395-9604-4e77-bc9d-a9433e722ab4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668794421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.668794421
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1715767599
Short name T925
Test name
Test status
Simulation time 370543045 ps
CPU time 1.53 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 197408 kb
Host smart-9913227e-a90d-4ddc-9c60-0995138be3ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1715767599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1715767599
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3124190613
Short name T870
Test name
Test status
Simulation time 67383624 ps
CPU time 1.04 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 196892 kb
Host smart-bc7e5a29-94e0-4436-a3ca-589c0f54e558
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124190613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3124190613
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3765066737
Short name T900
Test name
Test status
Simulation time 203374138 ps
CPU time 1.31 seconds
Started Jul 07 05:47:29 PM PDT 24
Finished Jul 07 05:47:31 PM PDT 24
Peak memory 197348 kb
Host smart-6172c6e1-698e-469d-bfc6-9cf047682dd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3765066737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3765066737
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2893587849
Short name T928
Test name
Test status
Simulation time 33908074 ps
CPU time 1.03 seconds
Started Jul 07 05:47:32 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 196916 kb
Host smart-cf75b6d4-f48c-470c-955d-7de081bd8a26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893587849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2893587849
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3277317393
Short name T866
Test name
Test status
Simulation time 54728553 ps
CPU time 1.07 seconds
Started Jul 07 05:47:34 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 197056 kb
Host smart-c8f10a73-44e9-4444-812e-3c0f03d1c1fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3277317393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3277317393
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2066957221
Short name T863
Test name
Test status
Simulation time 31520092 ps
CPU time 1.03 seconds
Started Jul 07 05:47:29 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 196088 kb
Host smart-697627c3-631d-4193-9170-11a00731ef05
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066957221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2066957221
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2969970717
Short name T890
Test name
Test status
Simulation time 88626637 ps
CPU time 1.53 seconds
Started Jul 07 05:47:28 PM PDT 24
Finished Jul 07 05:47:30 PM PDT 24
Peak memory 197020 kb
Host smart-f40d3c5d-cb07-4383-865a-d55a7b742ed5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2969970717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2969970717
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.36304135
Short name T886
Test name
Test status
Simulation time 111992802 ps
CPU time 0.97 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 197108 kb
Host smart-12447756-4550-4e39-9999-5444dcd699ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.36304135
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1934970318
Short name T905
Test name
Test status
Simulation time 81377503 ps
CPU time 1.53 seconds
Started Jul 07 05:47:34 PM PDT 24
Finished Jul 07 05:47:36 PM PDT 24
Peak memory 198436 kb
Host smart-6ad44a27-03ef-4e08-8f21-3e545a2b3d87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1934970318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1934970318
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.936418953
Short name T915
Test name
Test status
Simulation time 92289799 ps
CPU time 1.52 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 197804 kb
Host smart-47bacae5-1356-40a5-9530-e291784d7401
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936418953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.936418953
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.805974192
Short name T879
Test name
Test status
Simulation time 236816403 ps
CPU time 1.17 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 197104 kb
Host smart-672fbf57-74e5-442f-8ba3-b622c62842ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=805974192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.805974192
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1994324162
Short name T856
Test name
Test status
Simulation time 45238283 ps
CPU time 1.29 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 198440 kb
Host smart-f4fc014f-5f52-40e2-8c0d-88fc61385746
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994324162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1994324162
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.871970317
Short name T920
Test name
Test status
Simulation time 37733374 ps
CPU time 0.84 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:34 PM PDT 24
Peak memory 196616 kb
Host smart-ace9343f-b7fc-4619-a4f6-6815d1dd923d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=871970317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.871970317
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1180715754
Short name T884
Test name
Test status
Simulation time 81121587 ps
CPU time 0.84 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 195860 kb
Host smart-d9872e46-11c9-4ad7-8f20-6dde839428e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180715754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1180715754
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2426395591
Short name T868
Test name
Test status
Simulation time 210678693 ps
CPU time 1.12 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 196936 kb
Host smart-4f4f021e-795c-46ed-874c-0b613055cab2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2426395591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2426395591
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1726615561
Short name T945
Test name
Test status
Simulation time 39288245 ps
CPU time 0.93 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 196992 kb
Host smart-b77c6182-a5e1-47ef-a9e3-3fb9e80d013a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726615561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1726615561
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3249358481
Short name T860
Test name
Test status
Simulation time 115595266 ps
CPU time 1.09 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 196892 kb
Host smart-35725c56-4dfc-43ae-adc7-26a7b0b98912
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3249358481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3249358481
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.707335794
Short name T864
Test name
Test status
Simulation time 42753599 ps
CPU time 0.8 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:36 PM PDT 24
Peak memory 195792 kb
Host smart-87c0b9f4-c868-43cd-8260-5f2aad81c61a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707335794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.707335794
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.907345993
Short name T852
Test name
Test status
Simulation time 144019964 ps
CPU time 1.2 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 198452 kb
Host smart-92ac9956-49b2-4378-bc31-c4dc4e4a1d7e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=907345993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.907345993
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.919210962
Short name T871
Test name
Test status
Simulation time 66789812 ps
CPU time 0.84 seconds
Started Jul 07 05:47:32 PM PDT 24
Finished Jul 07 05:47:33 PM PDT 24
Peak memory 196568 kb
Host smart-97ce942f-8aa6-4d06-b3a0-a6b861fc5f87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919210962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.919210962
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.434149387
Short name T908
Test name
Test status
Simulation time 35131816 ps
CPU time 0.82 seconds
Started Jul 07 05:47:17 PM PDT 24
Finished Jul 07 05:47:18 PM PDT 24
Peak memory 195904 kb
Host smart-64051502-31d3-4117-bcd8-93c87207c410
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=434149387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.434149387
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3042216970
Short name T869
Test name
Test status
Simulation time 83863299 ps
CPU time 0.92 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:22 PM PDT 24
Peak memory 196956 kb
Host smart-cf4e9761-4493-40b6-987e-ba801533ce5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042216970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3042216970
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.341119514
Short name T855
Test name
Test status
Simulation time 875729908 ps
CPU time 1.45 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 197248 kb
Host smart-d4fc957c-803b-4e45-a693-9d956abbbfe9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=341119514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.341119514
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4220517120
Short name T862
Test name
Test status
Simulation time 46358970 ps
CPU time 1.21 seconds
Started Jul 07 05:47:37 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 196152 kb
Host smart-d60dd084-165a-49c8-996f-daf437d141ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220517120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4220517120
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2819824735
Short name T932
Test name
Test status
Simulation time 142698261 ps
CPU time 1.46 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 197196 kb
Host smart-861d854a-3084-4f56-86a1-1c5ff0f9c51a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2819824735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2819824735
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.546306657
Short name T944
Test name
Test status
Simulation time 379319166 ps
CPU time 1.66 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:39 PM PDT 24
Peak memory 197220 kb
Host smart-a5d30f61-689d-4f31-bfcd-62033dc6f3e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546306657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.546306657
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3964679749
Short name T847
Test name
Test status
Simulation time 510798613 ps
CPU time 1.27 seconds
Started Jul 07 05:47:37 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 197072 kb
Host smart-fa0a5049-6584-47aa-832a-bdd964f9b9c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3964679749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3964679749
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1047190078
Short name T934
Test name
Test status
Simulation time 109911793 ps
CPU time 1.5 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:37 PM PDT 24
Peak memory 198336 kb
Host smart-964a067e-baf8-479f-9659-51e55d9d51fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047190078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1047190078
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.825429002
Short name T891
Test name
Test status
Simulation time 153186938 ps
CPU time 0.94 seconds
Started Jul 07 05:47:38 PM PDT 24
Finished Jul 07 05:47:39 PM PDT 24
Peak memory 196996 kb
Host smart-1df7a637-2d58-4380-8514-a2f0906d875c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=825429002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.825429002
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2057798655
Short name T889
Test name
Test status
Simulation time 207516911 ps
CPU time 1.18 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:34 PM PDT 24
Peak memory 196988 kb
Host smart-e3274368-65b7-4837-8576-0ee3c994fd68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057798655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2057798655
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3328940027
Short name T939
Test name
Test status
Simulation time 378778117 ps
CPU time 1.25 seconds
Started Jul 07 05:47:38 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 196956 kb
Host smart-a6cb7183-90c9-464c-b5a1-54b1f4264515
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3328940027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3328940027
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2692303145
Short name T846
Test name
Test status
Simulation time 118596636 ps
CPU time 1.03 seconds
Started Jul 07 05:47:34 PM PDT 24
Finished Jul 07 05:47:35 PM PDT 24
Peak memory 196908 kb
Host smart-598420db-e304-4388-89e9-0fa712b6da03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692303145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2692303145
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2093491821
Short name T938
Test name
Test status
Simulation time 491753169 ps
CPU time 1.09 seconds
Started Jul 07 05:47:33 PM PDT 24
Finished Jul 07 05:47:34 PM PDT 24
Peak memory 197012 kb
Host smart-b09b0a1e-b80f-441c-8416-bc5b28ea29c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2093491821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2093491821
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1910776413
Short name T930
Test name
Test status
Simulation time 493416213 ps
CPU time 1.7 seconds
Started Jul 07 05:47:37 PM PDT 24
Finished Jul 07 05:47:39 PM PDT 24
Peak memory 198476 kb
Host smart-d35399f2-9c22-4865-8606-f0d19ef66062
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910776413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1910776413
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1773646926
Short name T940
Test name
Test status
Simulation time 128647914 ps
CPU time 1.19 seconds
Started Jul 07 05:47:36 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 198472 kb
Host smart-d32553a7-9bbd-4008-a622-d8a8a5046cb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1773646926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1773646926
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.179019070
Short name T858
Test name
Test status
Simulation time 258732039 ps
CPU time 1.1 seconds
Started Jul 07 05:47:37 PM PDT 24
Finished Jul 07 05:47:39 PM PDT 24
Peak memory 197024 kb
Host smart-2b7dadc3-7e17-4873-a50e-cbcb9e681360
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179019070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.179019070
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3206568950
Short name T849
Test name
Test status
Simulation time 54127062 ps
CPU time 0.88 seconds
Started Jul 07 05:47:34 PM PDT 24
Finished Jul 07 05:47:36 PM PDT 24
Peak memory 197088 kb
Host smart-07f40b0c-4fd4-419d-94f2-0969ef72f083
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3206568950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3206568950
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.496614209
Short name T874
Test name
Test status
Simulation time 44725371 ps
CPU time 1.06 seconds
Started Jul 07 05:47:39 PM PDT 24
Finished Jul 07 05:47:40 PM PDT 24
Peak memory 196796 kb
Host smart-246ac86e-e29f-4fab-ae32-374603765178
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496614209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.496614209
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.252715734
Short name T902
Test name
Test status
Simulation time 91472914 ps
CPU time 0.98 seconds
Started Jul 07 05:47:41 PM PDT 24
Finished Jul 07 05:47:43 PM PDT 24
Peak memory 196888 kb
Host smart-fc248d3c-ebc1-4043-93b1-d35993fa5fdb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=252715734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.252715734
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1063939643
Short name T923
Test name
Test status
Simulation time 147560221 ps
CPU time 1.46 seconds
Started Jul 07 05:47:35 PM PDT 24
Finished Jul 07 05:47:36 PM PDT 24
Peak memory 197024 kb
Host smart-8f48f2f4-d86e-4682-9368-e867562a6577
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063939643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1063939643
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.660884195
Short name T876
Test name
Test status
Simulation time 60393079 ps
CPU time 1.09 seconds
Started Jul 07 05:47:37 PM PDT 24
Finished Jul 07 05:47:38 PM PDT 24
Peak memory 196184 kb
Host smart-d63585a8-49a2-431e-9795-eab6eaeac421
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=660884195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.660884195
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371838938
Short name T897
Test name
Test status
Simulation time 35109751 ps
CPU time 0.9 seconds
Started Jul 07 05:47:38 PM PDT 24
Finished Jul 07 05:47:39 PM PDT 24
Peak memory 195780 kb
Host smart-4bb1f7b1-8fdc-40c8-92d6-380dd85ad76a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371838938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3371838938
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.4276890421
Short name T896
Test name
Test status
Simulation time 69155954 ps
CPU time 1.39 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 197224 kb
Host smart-b91efbb1-8246-497f-8a2f-c511e0808c2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4276890421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.4276890421
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3567122381
Short name T857
Test name
Test status
Simulation time 247127446 ps
CPU time 1.26 seconds
Started Jul 07 05:47:22 PM PDT 24
Finished Jul 07 05:47:24 PM PDT 24
Peak memory 197252 kb
Host smart-c3c55d42-f1ff-482b-965f-00b4da739e59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567122381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3567122381
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1831157266
Short name T929
Test name
Test status
Simulation time 97706794 ps
CPU time 0.94 seconds
Started Jul 07 05:47:23 PM PDT 24
Finished Jul 07 05:47:24 PM PDT 24
Peak memory 196032 kb
Host smart-b044cc59-205f-4643-b4a9-c9db4cf8a060
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1831157266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1831157266
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.818943611
Short name T926
Test name
Test status
Simulation time 202426490 ps
CPU time 1.03 seconds
Started Jul 07 05:47:23 PM PDT 24
Finished Jul 07 05:47:24 PM PDT 24
Peak memory 196364 kb
Host smart-7c659f13-3928-4b5c-ad26-f9a813ee89d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818943611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.818943611
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3110553263
Short name T935
Test name
Test status
Simulation time 361040095 ps
CPU time 1.56 seconds
Started Jul 07 05:47:23 PM PDT 24
Finished Jul 07 05:47:25 PM PDT 24
Peak memory 198408 kb
Host smart-8ec904be-37f9-445d-95bf-a1dc0cc0e924
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3110553263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3110553263
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2666064150
Short name T933
Test name
Test status
Simulation time 270225212 ps
CPU time 1.46 seconds
Started Jul 07 05:47:23 PM PDT 24
Finished Jul 07 05:47:25 PM PDT 24
Peak memory 198428 kb
Host smart-283cdb90-cac5-4b4c-ba6a-3a64e319a481
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666064150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2666064150
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.161636787
Short name T907
Test name
Test status
Simulation time 59269015 ps
CPU time 1.11 seconds
Started Jul 07 05:47:23 PM PDT 24
Finished Jul 07 05:47:24 PM PDT 24
Peak memory 197076 kb
Host smart-2cb11756-f5ef-4279-a643-f8cbdfc72446
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=161636787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.161636787
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1555381523
Short name T883
Test name
Test status
Simulation time 40513977 ps
CPU time 0.95 seconds
Started Jul 07 05:47:22 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 197504 kb
Host smart-a66edd7a-4a7b-42d3-b32d-9323736a6187
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555381523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1555381523
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2378750919
Short name T898
Test name
Test status
Simulation time 24356460 ps
CPU time 0.7 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:23 PM PDT 24
Peak memory 194756 kb
Host smart-27ba64fd-06fb-4fa7-8c9a-04c3ca8e169d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2378750919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2378750919
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1937243717
Short name T901
Test name
Test status
Simulation time 421569152 ps
CPU time 1.28 seconds
Started Jul 07 05:47:21 PM PDT 24
Finished Jul 07 05:47:22 PM PDT 24
Peak memory 198724 kb
Host smart-218a177c-b45f-4377-817f-43cdb808bc20
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937243717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1937243717
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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