Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5035117	1			T1	839		T11	1		T12	16578
all_pins[1]	5035117	1			T1	839		T11	1		T12	16578
all_pins[2]	5035117	1			T1	839		T11	1		T12	16578
all_pins[3]	5035117	1			T1	839		T11	1		T12	16578
all_pins[4]	5035117	1			T1	839		T11	1		T12	16578
all_pins[5]	5035117	1			T1	839		T11	1		T12	16578
all_pins[6]	5035117	1			T1	839		T11	1		T12	16578
all_pins[7]	5035117	1			T1	839		T11	1		T12	16578
all_pins[8]	5035117	1			T1	839		T11	1		T12	16578
all_pins[9]	5035117	1			T1	839		T11	1		T12	16578
all_pins[10]	5035117	1			T1	839		T11	1		T12	16578
all_pins[11]	5035117	1			T1	839		T11	1		T12	16578
all_pins[12]	5035117	1			T1	839		T11	1		T12	16578
all_pins[13]	5035117	1			T1	839		T11	1		T12	16578
all_pins[14]	5035117	1			T1	839		T11	1		T12	16578
all_pins[15]	5035117	1			T1	839		T11	1		T12	16578
all_pins[16]	5035117	1			T1	839		T11	1		T12	16578
all_pins[17]	5035117	1			T1	839		T11	1		T12	16578
all_pins[18]	5035117	1			T1	839		T11	1		T12	16578
all_pins[19]	5035117	1			T1	839		T11	1		T12	16578
all_pins[20]	5035117	1			T1	839		T11	1		T12	16578
all_pins[21]	5035117	1			T1	839		T11	1		T12	16578
all_pins[22]	5035117	1			T1	839		T11	1		T12	16578
all_pins[23]	5035117	1			T1	839		T11	1		T12	16578
all_pins[24]	5035117	1			T1	839		T11	1		T12	16578
all_pins[25]	5035117	1			T1	839		T11	1		T12	16578
all_pins[26]	5035117	1			T1	839		T11	1		T12	16578
all_pins[27]	5035117	1			T1	839		T11	1		T12	16578
all_pins[28]	5035117	1			T1	839		T11	1		T12	16578
all_pins[29]	5035117	1			T1	839		T11	1		T12	16578
all_pins[30]	5035117	1			T1	839		T11	1		T12	16578
all_pins[31]	5035117	1			T1	839		T11	1		T12	16578

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	100033668	1			T1	16496		T11	32		T12	328083
values[0x1]	61090076	1			T1	10352		T12	202413		T13	204832
transitions[0x0=>0x1]	36600567	1			T1	5991		T12	120774		T13	122564
transitions[0x1=>0x0]	36600421	1			T1	5990		T12	120774		T13	122564

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3126819	1			T1	479		T11	1		T12	10110
all_pins[0]	values[0x1]	1908298	1			T1	360		T12	6468		T13	63795
all_pins[0]	transitions[0x0=>0x1]	1178497	1			T1	228		T12	3961		T13	39468
all_pins[0]	transitions[0x1=>0x0]	1181574	1			T1	186		T12	3772		T13	39740
all_pins[1]	values[0x0]	3127288	1			T1	513		T11	1		T12	10206
all_pins[1]	values[0x1]	1907829	1			T1	326		T12	6372		T13	64370
all_pins[1]	transitions[0x0=>0x1]	1139116	1			T1	164		T12	3731		T13	38790
all_pins[1]	transitions[0x1=>0x0]	1139585	1			T1	198		T12	3827		T13	38215
all_pins[2]	values[0x0]	3130976	1			T1	537		T11	1		T12	10542
all_pins[2]	values[0x1]	1904141	1			T1	302		T12	6036		T13	63646
all_pins[2]	transitions[0x0=>0x1]	1139579	1			T1	178		T12	3541		T13	37827
all_pins[2]	transitions[0x1=>0x0]	1143267	1			T1	202		T12	3877		T13	38551
all_pins[3]	values[0x0]	3120348	1			T1	427		T11	1		T12	10298
all_pins[3]	values[0x1]	1914769	1			T1	412		T12	6280		T13	62712
all_pins[3]	transitions[0x0=>0x1]	1148142	1			T1	248		T12	3835		T13	37273
all_pins[3]	transitions[0x1=>0x0]	1137514	1			T1	138		T12	3591		T13	38207
all_pins[4]	values[0x0]	3122270	1			T1	519		T11	1		T12	9889
all_pins[4]	values[0x1]	1912847	1			T1	320		T12	6689		T13	65407
all_pins[4]	transitions[0x0=>0x1]	1143999	1			T1	134		T12	4080		T13	39577
all_pins[4]	transitions[0x1=>0x0]	1145921	1			T1	226		T12	3671		T13	36882
all_pins[5]	values[0x0]	3131505	1			T1	595		T11	1		T12	10289
all_pins[5]	values[0x1]	1903612	1			T1	244		T12	6289		T13	64814
all_pins[5]	transitions[0x0=>0x1]	1137122	1			T1	130		T12	3791		T13	37862
all_pins[5]	transitions[0x1=>0x0]	1146357	1			T1	206		T12	4191		T13	38455
all_pins[6]	values[0x0]	3126209	1			T1	551		T11	1		T12	10223
all_pins[6]	values[0x1]	1908908	1			T1	288		T12	6355		T13	62974
all_pins[6]	transitions[0x0=>0x1]	1146491	1			T1	218		T12	3737		T13	37382
all_pins[6]	transitions[0x1=>0x0]	1141195	1			T1	174		T12	3671		T13	39222
all_pins[7]	values[0x0]	3127057	1			T1	501		T11	1		T12	10121
all_pins[7]	values[0x1]	1908060	1			T1	338		T12	6457		T13	63480
all_pins[7]	transitions[0x0=>0x1]	1141904	1			T1	225		T12	3748		T13	38254
all_pins[7]	transitions[0x1=>0x0]	1142752	1			T1	175		T12	3646		T13	37748
all_pins[8]	values[0x0]	3125585	1			T1	527		T11	1		T12	9920
all_pins[8]	values[0x1]	1909532	1			T1	312		T12	6658		T13	63822
all_pins[8]	transitions[0x0=>0x1]	1142758	1			T1	144		T12	3916		T13	38510
all_pins[8]	transitions[0x1=>0x0]	1141286	1			T1	170		T12	3715		T13	38168
all_pins[9]	values[0x0]	3128552	1			T1	481		T11	1		T12	10145
all_pins[9]	values[0x1]	1906565	1			T1	358		T12	6433		T13	64922
all_pins[9]	transitions[0x0=>0x1]	1138669	1			T1	202		T12	3752		T13	39268
all_pins[9]	transitions[0x1=>0x0]	1141636	1			T1	156		T12	3977		T13	38168
all_pins[10]	values[0x0]	3132654	1			T1	501		T11	1		T12	10095
all_pins[10]	values[0x1]	1902463	1			T1	338		T12	6483		T13	65021
all_pins[10]	transitions[0x0=>0x1]	1139200	1			T1	191		T12	3856		T13	38290
all_pins[10]	transitions[0x1=>0x0]	1143302	1			T1	211		T12	3806		T13	38191
all_pins[11]	values[0x0]	3122471	1			T1	454		T11	1		T12	10390
all_pins[11]	values[0x1]	1912646	1			T1	385		T12	6188		T13	62404
all_pins[11]	transitions[0x0=>0x1]	1147267	1			T1	230		T12	3620		T13	37061
all_pins[11]	transitions[0x1=>0x0]	1137084	1			T1	183		T12	3915		T13	39678
all_pins[12]	values[0x0]	3122999	1			T1	538		T11	1		T12	10062
all_pins[12]	values[0x1]	1912118	1			T1	301		T12	6516		T13	65097
all_pins[12]	transitions[0x0=>0x1]	1147215	1			T1	148		T12	3911		T13	39862
all_pins[12]	transitions[0x1=>0x0]	1147743	1			T1	232		T12	3583		T13	37169
all_pins[13]	values[0x0]	3128599	1			T1	532		T11	1		T12	10315
all_pins[13]	values[0x1]	1906518	1			T1	307		T12	6263		T13	63656
all_pins[13]	transitions[0x0=>0x1]	1141306	1			T1	181		T12	3704		T13	37818
all_pins[13]	transitions[0x1=>0x0]	1146906	1			T1	175		T12	3957		T13	39259
all_pins[14]	values[0x0]	3128876	1			T1	513		T11	1		T12	10468
all_pins[14]	values[0x1]	1906241	1			T1	326		T12	6110		T13	64180
all_pins[14]	transitions[0x0=>0x1]	1141381	1			T1	206		T12	3809		T13	38228
all_pins[14]	transitions[0x1=>0x0]	1141658	1			T1	187		T12	3962		T13	37704
all_pins[15]	values[0x0]	3129220	1			T1	499		T11	1		T12	10292
all_pins[15]	values[0x1]	1905897	1			T1	340		T12	6286		T13	63572
all_pins[15]	transitions[0x0=>0x1]	1141515	1			T1	201		T12	3883		T13	37928
all_pins[15]	transitions[0x1=>0x0]	1141859	1			T1	187		T12	3707		T13	38536
all_pins[16]	values[0x0]	3130262	1			T1	533		T11	1		T12	10174
all_pins[16]	values[0x1]	1904855	1			T1	306		T12	6404		T13	63570
all_pins[16]	transitions[0x0=>0x1]	1139914	1			T1	161		T12	3788		T13	37742
all_pins[16]	transitions[0x1=>0x0]	1140956	1			T1	195		T12	3670		T13	37744
all_pins[17]	values[0x0]	3126275	1			T1	550		T11	1		T12	10444
all_pins[17]	values[0x1]	1908842	1			T1	289		T12	6134		T13	64318
all_pins[17]	transitions[0x0=>0x1]	1144587	1			T1	175		T12	3628		T13	38647
all_pins[17]	transitions[0x1=>0x0]	1140600	1			T1	192		T12	3898		T13	37899
all_pins[18]	values[0x0]	3125327	1			T1	544		T11	1		T12	10302
all_pins[18]	values[0x1]	1909790	1			T1	295		T12	6276		T13	63746
all_pins[18]	transitions[0x0=>0x1]	1141179	1			T1	133		T12	3844		T13	37950
all_pins[18]	transitions[0x1=>0x0]	1140231	1			T1	127		T12	3702		T13	38522
all_pins[19]	values[0x0]	3122938	1			T1	473		T11	1		T12	10234
all_pins[19]	values[0x1]	1912179	1			T1	366		T12	6344		T13	63423
all_pins[19]	transitions[0x0=>0x1]	1145624	1			T1	232		T12	3761		T13	38202
all_pins[19]	transitions[0x1=>0x0]	1143235	1			T1	161		T12	3693		T13	38525
all_pins[20]	values[0x0]	3117038	1			T1	520		T11	1		T12	10585
all_pins[20]	values[0x1]	1918079	1			T1	319		T12	5993		T13	64794
all_pins[20]	transitions[0x0=>0x1]	1146030	1			T1	182		T12	3644		T13	38961
all_pins[20]	transitions[0x1=>0x0]	1140130	1			T1	229		T12	3995		T13	37590
all_pins[21]	values[0x0]	3124603	1			T1	566		T11	1		T12	10269
all_pins[21]	values[0x1]	1910514	1			T1	273		T12	6309		T13	63486
all_pins[21]	transitions[0x0=>0x1]	1140176	1			T1	140		T12	3872		T13	37465
all_pins[21]	transitions[0x1=>0x0]	1147741	1			T1	186		T12	3556		T13	38773
all_pins[22]	values[0x0]	3126568	1			T1	602		T11	1		T12	10115
all_pins[22]	values[0x1]	1908549	1			T1	237		T12	6463		T13	64142
all_pins[22]	transitions[0x0=>0x1]	1142388	1			T1	161		T12	3962		T13	38274
all_pins[22]	transitions[0x1=>0x0]	1144353	1			T1	197		T12	3808		T13	37618
all_pins[23]	values[0x0]	3123215	1			T1	505		T11	1		T12	10411
all_pins[23]	values[0x1]	1911902	1			T1	334		T12	6167		T13	65123
all_pins[23]	transitions[0x0=>0x1]	1145108	1			T1	211		T12	3575		T13	39124
all_pins[23]	transitions[0x1=>0x0]	1141755	1			T1	114		T12	3871		T13	38143
all_pins[24]	values[0x0]	3124273	1			T1	536		T11	1		T12	9957
all_pins[24]	values[0x1]	1910844	1			T1	303		T12	6621		T13	64596
all_pins[24]	transitions[0x0=>0x1]	1140170	1			T1	184		T12	3874		T13	38152
all_pins[24]	transitions[0x1=>0x0]	1141228	1			T1	215		T12	3420		T13	38679
all_pins[25]	values[0x0]	3124132	1			T1	496		T11	1		T12	10611
all_pins[25]	values[0x1]	1910985	1			T1	343		T12	5967		T13	64069
all_pins[25]	transitions[0x0=>0x1]	1143093	1			T1	214		T12	3351		T13	37667
all_pins[25]	transitions[0x1=>0x0]	1142952	1			T1	174		T12	4005		T13	38194
all_pins[26]	values[0x0]	3124426	1			T1	592		T11	1		T12	10187
all_pins[26]	values[0x1]	1910691	1			T1	247		T12	6391		T13	63830
all_pins[26]	transitions[0x0=>0x1]	1143934	1			T1	146		T12	3983		T13	38220
all_pins[26]	transitions[0x1=>0x0]	1144228	1			T1	242		T12	3559		T13	38459
all_pins[27]	values[0x0]	3124118	1			T1	488		T11	1		T12	10381
all_pins[27]	values[0x1]	1910999	1			T1	351		T12	6197		T13	63281
all_pins[27]	transitions[0x0=>0x1]	1143310	1			T1	256		T12	3649		T13	37885
all_pins[27]	transitions[0x1=>0x0]	1143002	1			T1	152		T12	3843		T13	38434
all_pins[28]	values[0x0]	3126468	1			T1	492		T11	1		T12	10052
all_pins[28]	values[0x1]	1908649	1			T1	347		T12	6526		T13	65091
all_pins[28]	transitions[0x0=>0x1]	1145241	1			T1	190		T12	3898		T13	39032
all_pins[28]	transitions[0x1=>0x0]	1147591	1			T1	194		T12	3569		T13	37222
all_pins[29]	values[0x0]	3127864	1			T1	458		T11	1		T12	10556
all_pins[29]	values[0x1]	1907253	1			T1	381		T12	6022		T13	63687
all_pins[29]	transitions[0x0=>0x1]	1140747	1			T1	226		T12	3533		T13	38269
all_pins[29]	transitions[0x1=>0x0]	1142143	1			T1	192		T12	4037		T13	39673
all_pins[30]	values[0x0]	3131137	1			T1	454		T11	1		T12	10141
all_pins[30]	values[0x1]	1903980	1			T1	385		T12	6437		T13	63231
all_pins[30]	transitions[0x0=>0x1]	1139694	1			T1	202		T12	3865		T13	37995
all_pins[30]	transitions[0x1=>0x0]	1142967	1			T1	198		T12	3450		T13	38451
all_pins[31]	values[0x0]	3123596	1			T1	520		T11	1		T12	10299
all_pins[31]	values[0x1]	1911521	1			T1	319		T12	6279		T13	64067
all_pins[31]	transitions[0x0=>0x1]	1145211	1			T1	150		T12	3672		T13	38665
all_pins[31]	transitions[0x1=>0x0]	1137670	1			T1	216		T12	3830		T13	37829