Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16250129	1			T1	2410		T11	421		T12	51123
all_values[1]	16250129	1			T1	2410		T11	421		T12	51123
all_values[2]	16250129	1			T1	2410		T11	421		T12	51123
all_values[3]	16250129	1			T1	2410		T11	421		T12	51123
all_values[4]	16250129	1			T1	2410		T11	421		T12	51123
all_values[5]	16250129	1			T1	2410		T11	421		T12	51123
all_values[6]	16250129	1			T1	2410		T11	421		T12	51123
all_values[7]	16250129	1			T1	2410		T11	421		T12	51123
all_values[8]	16250129	1			T1	2410		T11	421		T12	51123
all_values[9]	16250129	1			T1	2410		T11	421		T12	51123
all_values[10]	16250129	1			T1	2410		T11	421		T12	51123
all_values[11]	16250129	1			T1	2410		T11	421		T12	51123
all_values[12]	16250129	1			T1	2410		T11	421		T12	51123
all_values[13]	16250129	1			T1	2410		T11	421		T12	51123
all_values[14]	16250129	1			T1	2410		T11	421		T12	51123
all_values[15]	16250129	1			T1	2410		T11	421		T12	51123
all_values[16]	16250129	1			T1	2410		T11	421		T12	51123
all_values[17]	16250129	1			T1	2410		T11	421		T12	51123
all_values[18]	16250129	1			T1	2410		T11	421		T12	51123
all_values[19]	16250129	1			T1	2410		T11	421		T12	51123
all_values[20]	16250129	1			T1	2410		T11	421		T12	51123
all_values[21]	16250129	1			T1	2410		T11	421		T12	51123
all_values[22]	16250129	1			T1	2410		T11	421		T12	51123
all_values[23]	16250129	1			T1	2410		T11	421		T12	51123
all_values[24]	16250129	1			T1	2410		T11	421		T12	51123
all_values[25]	16250129	1			T1	2410		T11	421		T12	51123
all_values[26]	16250129	1			T1	2410		T11	421		T12	51123
all_values[27]	16250129	1			T1	2410		T11	421		T12	51123
all_values[28]	16250129	1			T1	2410		T11	421		T12	51123
all_values[29]	16250129	1			T1	2410		T11	421		T12	51123
all_values[30]	16250129	1			T1	2410		T11	421		T12	51123
all_values[31]	16250129	1			T1	2410		T11	421		T12	51123

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289774764

1

T1

38001

T11

13472

T12

901549

auto[1]

230229364

1

T1

39119

T12

734387

T13

772983

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103141118

1

T1

8361

T11

13472

T12

303920

auto[1]

416863010

1

T1

68759

T12

133201

T13

139630

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

514115889

1

T1

73931

T11

13472

T12

162231

auto[1]

5888239

1

T1

3189

T12

13622

T13

184485

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2529563	1			T1	114		T11	421		T12	7286
all_values[0]	auto[0]	auto[0]	auto[1]	6397593	1			T1	1078		T12	19671		T13	218429
all_values[0]	auto[0]	auto[1]	auto[0]	692686	1			T1	68		T12	2585		T13	22389
all_values[0]	auto[0]	auto[1]	auto[1]	6446449	1			T1	1057		T12	21148		T13	213344
all_values[0]	auto[1]	auto[0]	auto[1]	92610	1			T1	53		T12	223		T13	2890
all_values[0]	auto[1]	auto[1]	auto[1]	91228	1			T1	40		T12	210		T13	2872
all_values[1]	auto[0]	auto[0]	auto[0]	2538058	1			T1	120		T11	421		T12	7180
all_values[1]	auto[0]	auto[0]	auto[1]	6432445	1			T1	912		T12	20779		T13	214447
all_values[1]	auto[0]	auto[1]	auto[0]	691383	1			T1	166		T12	2049		T13	21546
all_values[1]	auto[0]	auto[1]	auto[1]	6403675	1			T1	1106		T12	20701		T13	216414
all_values[1]	auto[1]	auto[0]	auto[1]	92062	1			T1	52		T12	221		T13	2932
all_values[1]	auto[1]	auto[1]	auto[1]	92506	1			T1	54		T12	193		T13	2914
all_values[2]	auto[0]	auto[0]	auto[0]	2537045	1			T1	59		T11	421		T12	7520
all_values[2]	auto[0]	auto[0]	auto[1]	6482980	1			T1	1203		T12	21755		T13	214180
all_values[2]	auto[0]	auto[1]	auto[0]	686588	1			T1	98		T12	2000		T13	22540
all_values[2]	auto[0]	auto[1]	auto[1]	6359484	1			T1	941		T12	19415		T13	216921
all_values[2]	auto[1]	auto[0]	auto[1]	92343	1			T1	61		T12	219		T13	2858
all_values[2]	auto[1]	auto[1]	auto[1]	91689	1			T1	48		T12	214		T13	2872
all_values[3]	auto[0]	auto[0]	auto[0]	2530264	1			T1	78		T11	421		T12	7363
all_values[3]	auto[0]	auto[0]	auto[1]	6412515	1			T1	783		T12	21286		T13	224232
all_values[3]	auto[0]	auto[1]	auto[0]	690235	1			T1	121		T12	2106		T13	21595
all_values[3]	auto[0]	auto[1]	auto[1]	6432881	1			T1	1325		T12	19953		T13	209062
all_values[3]	auto[1]	auto[0]	auto[1]	92079	1			T1	35		T12	204		T13	2892
all_values[3]	auto[1]	auto[1]	auto[1]	92155	1			T1	68		T12	211		T13	2844
all_values[4]	auto[0]	auto[0]	auto[0]	2522039	1			T1	90		T11	421		T12	6995
all_values[4]	auto[0]	auto[0]	auto[1]	6464697	1			T1	1058		T12	19586		T13	216617
all_values[4]	auto[0]	auto[1]	auto[0]	685286	1			T1	135		T12	2355		T13	21474
all_values[4]	auto[0]	auto[1]	auto[1]	6394849	1			T1	1032		T12	21748		T13	216832
all_values[4]	auto[1]	auto[0]	auto[1]	91494	1			T1	45		T12	205		T13	2793
all_values[4]	auto[1]	auto[1]	auto[1]	91764	1			T1	50		T12	234		T13	2995
all_values[5]	auto[0]	auto[0]	auto[0]	2534333	1			T1	263		T11	421		T12	7248
all_values[5]	auto[0]	auto[0]	auto[1]	6439217	1			T1	1105		T12	21020		T13	215383
all_values[5]	auto[0]	auto[1]	auto[0]	698421	1			T1	82		T12	2128		T13	25785
all_values[5]	auto[0]	auto[1]	auto[1]	6394205	1			T1	857		T12	20287		T13	213491
all_values[5]	auto[1]	auto[0]	auto[1]	92471	1			T1	58		T12	202		T13	2856
all_values[5]	auto[1]	auto[1]	auto[1]	91482	1			T1	45		T12	238		T13	2929
all_values[6]	auto[0]	auto[0]	auto[0]	2530842	1			T1	165		T11	421		T12	7112
all_values[6]	auto[0]	auto[0]	auto[1]	6435097	1			T1	1050		T12	20640		T13	220899
all_values[6]	auto[0]	auto[1]	auto[0]	695867	1			T1	100		T12	2313		T13	23307
all_values[6]	auto[0]	auto[1]	auto[1]	6404185	1			T1	1016		T12	20655		T13	207606
all_values[6]	auto[1]	auto[0]	auto[1]	91826	1			T1	46		T12	197		T13	2938
all_values[6]	auto[1]	auto[1]	auto[1]	92312	1			T1	33		T12	206		T13	2863
all_values[7]	auto[0]	auto[0]	auto[0]	2537920	1			T1	175		T11	421		T12	7223
all_values[7]	auto[0]	auto[0]	auto[1]	6433862	1			T1	1045		T12	19317		T13	207356
all_values[7]	auto[0]	auto[1]	auto[0]	681631	1			T1	70		T12	2378		T13	22119
all_values[7]	auto[0]	auto[1]	auto[1]	6412616	1			T1	1013		T12	21766		T13	224263
all_values[7]	auto[1]	auto[0]	auto[1]	92275	1			T1	56		T12	220		T13	2836
all_values[7]	auto[1]	auto[1]	auto[1]	91825	1			T1	51		T12	219		T13	2897
all_values[8]	auto[0]	auto[0]	auto[0]	2534136	1			T1	145		T11	421		T12	7157
all_values[8]	auto[0]	auto[0]	auto[1]	6427255	1			T1	1091		T12	19885		T13	219538
all_values[8]	auto[0]	auto[1]	auto[0]	682944	1			T1	121		T12	2208		T13	20776
all_values[8]	auto[0]	auto[1]	auto[1]	6421360	1			T1	949		T12	21417		T13	213946
all_values[8]	auto[1]	auto[0]	auto[1]	92625	1			T1	48		T12	205		T13	2907
all_values[8]	auto[1]	auto[1]	auto[1]	91809	1			T1	56		T12	251		T13	2899
all_values[9]	auto[0]	auto[0]	auto[0]	2539350	1			T1	143		T11	421		T12	7374
all_values[9]	auto[0]	auto[0]	auto[1]	6446911	1			T1	953		T12	20448		T13	217086
all_values[9]	auto[0]	auto[1]	auto[0]	693970	1			T1	102		T12	2303		T13	24555
all_values[9]	auto[0]	auto[1]	auto[1]	6385630	1			T1	1121		T12	20587		T13	212645
all_values[9]	auto[1]	auto[0]	auto[1]	92604	1			T1	31		T12	193		T13	2872
all_values[9]	auto[1]	auto[1]	auto[1]	91664	1			T1	60		T12	218		T13	2921
all_values[10]	auto[0]	auto[0]	auto[0]	2535516	1			T1	165		T11	421		T12	7258
all_values[10]	auto[0]	auto[0]	auto[1]	6466541	1			T1	816		T12	20230		T13	219455
all_values[10]	auto[0]	auto[1]	auto[0]	697524	1			T1	182		T12	2291		T13	22255
all_values[10]	auto[0]	auto[1]	auto[1]	6366973	1			T1	1144		T12	20910		T13	211130
all_values[10]	auto[1]	auto[0]	auto[1]	92498	1			T1	44		T12	201		T13	2865
all_values[10]	auto[1]	auto[1]	auto[1]	91077	1			T1	59		T12	233		T13	2890
all_values[11]	auto[0]	auto[0]	auto[0]	2527521	1			T1	102		T11	421		T12	7397
all_values[11]	auto[0]	auto[0]	auto[1]	6434587	1			T1	810		T12	21366		T13	216430
all_values[11]	auto[0]	auto[1]	auto[0]	688700	1			T1	132		T12	2102		T13	22611
all_values[11]	auto[0]	auto[1]	auto[1]	6415102	1			T1	1267		T12	19848		T13	212876
all_values[11]	auto[1]	auto[0]	auto[1]	92140	1			T1	44		T12	199		T13	2909
all_values[11]	auto[1]	auto[1]	auto[1]	92079	1			T1	55		T12	211		T13	2903
all_values[12]	auto[0]	auto[0]	auto[0]	2531956	1			T1	206		T11	421		T12	6861
all_values[12]	auto[0]	auto[0]	auto[1]	6423943	1			T1	931		T12	20745		T13	209170
all_values[12]	auto[0]	auto[1]	auto[0]	687266	1			T1	126		T12	2454		T13	24127
all_values[12]	auto[0]	auto[1]	auto[1]	6423222	1			T1	1058		T12	20651		T13	219814
all_values[12]	auto[1]	auto[0]	auto[1]	91695	1			T1	37		T12	196		T13	2730
all_values[12]	auto[1]	auto[1]	auto[1]	92047	1			T1	52		T12	216		T13	2967
all_values[13]	auto[0]	auto[0]	auto[0]	2526690	1			T1	154		T11	421		T12	7222
all_values[13]	auto[0]	auto[0]	auto[1]	6455152	1			T1	1188		T12	20262		T13	206318
all_values[13]	auto[0]	auto[1]	auto[0]	687974	1			T1	87		T12	2175		T13	22930
all_values[13]	auto[0]	auto[1]	auto[1]	6396409	1			T1	883		T12	21043		T13	224755
all_values[13]	auto[1]	auto[0]	auto[1]	92320	1			T1	63		T12	233		T13	2874
all_values[13]	auto[1]	auto[1]	auto[1]	91584	1			T1	35		T12	188		T13	2851
all_values[14]	auto[0]	auto[0]	auto[0]	2530360	1			T1	143		T11	421		T12	7484
all_values[14]	auto[0]	auto[0]	auto[1]	6454417	1			T1	983		T12	20687		T13	222183
all_values[14]	auto[0]	auto[1]	auto[0]	697692	1			T1	146		T12	2256		T13	23556
all_values[14]	auto[0]	auto[1]	auto[1]	6382756	1			T1	1030		T12	20289		T13	206764
all_values[14]	auto[1]	auto[0]	auto[1]	93166	1			T1	61		T12	200		T13	2893
all_values[14]	auto[1]	auto[1]	auto[1]	91738	1			T1	47		T12	207		T13	2904
all_values[15]	auto[0]	auto[0]	auto[0]	2531309	1			T1	133		T11	421		T12	7108
all_values[15]	auto[0]	auto[0]	auto[1]	6401438	1			T1	962		T12	20128		T13	217172
all_values[15]	auto[0]	auto[1]	auto[0]	701286	1			T1	112		T12	2571		T13	22131
all_values[15]	auto[0]	auto[1]	auto[1]	6432484	1			T1	1085		T12	20904		T13	215426
all_values[15]	auto[1]	auto[0]	auto[1]	91893	1			T1	46		T12	196		T13	2840
all_values[15]	auto[1]	auto[1]	auto[1]	91719	1			T1	72		T12	216		T13	2885
all_values[16]	auto[0]	auto[0]	auto[0]	2528081	1			T1	126		T11	421		T12	7288
all_values[16]	auto[0]	auto[0]	auto[1]	6434408	1			T1	1008		T12	21234		T13	224160
all_values[16]	auto[0]	auto[1]	auto[0]	691194	1			T1	154		T12	2184		T13	22025
all_values[16]	auto[0]	auto[1]	auto[1]	6412687	1			T1	1035		T12	19990		T13	207808
all_values[16]	auto[1]	auto[0]	auto[1]	91974	1			T1	38		T12	245		T13	2834
all_values[16]	auto[1]	auto[1]	auto[1]	91785	1			T1	49		T12	182		T13	2895
all_values[17]	auto[0]	auto[0]	auto[0]	2534017	1			T1	165		T11	421		T12	7487
all_values[17]	auto[0]	auto[0]	auto[1]	6431398	1			T1	993		T12	21646		T13	210999
all_values[17]	auto[0]	auto[1]	auto[0]	691767	1			T1	163		T12	1811		T13	22905
all_values[17]	auto[0]	auto[1]	auto[1]	6409227	1			T1	997		T12	19764		T13	219739
all_values[17]	auto[1]	auto[0]	auto[1]	92004	1			T1	40		T12	222		T13	2865
all_values[17]	auto[1]	auto[1]	auto[1]	91716	1			T1	52		T12	193		T13	2942
all_values[18]	auto[0]	auto[0]	auto[0]	2527796	1			T1	173		T11	421		T12	7453
all_values[18]	auto[0]	auto[0]	auto[1]	6416849	1			T1	1033		T12	21370		T13	218087
all_values[18]	auto[0]	auto[1]	auto[0]	692768	1			T1	110		T12	1958		T13	22135
all_values[18]	auto[0]	auto[1]	auto[1]	6428506	1			T1	1003		T12	19914		T13	214500
all_values[18]	auto[1]	auto[0]	auto[1]	92265	1			T1	44		T12	212		T13	2981
all_values[18]	auto[1]	auto[1]	auto[1]	91945	1			T1	47		T12	216		T13	2864
all_values[19]	auto[0]	auto[0]	auto[0]	2519310	1			T1	59		T11	421		T12	7212
all_values[19]	auto[0]	auto[0]	auto[1]	6437174	1			T1	983		T12	20534		T13	215791
all_values[19]	auto[0]	auto[1]	auto[0]	695347	1			T1	139		T12	2338		T13	26240
all_values[19]	auto[0]	auto[1]	auto[1]	6414842	1			T1	1124		T12	20619		T13	213150
all_values[19]	auto[1]	auto[0]	auto[1]	91938	1			T1	48		T12	186		T13	2813
all_values[19]	auto[1]	auto[1]	auto[1]	91518	1			T1	57		T12	234		T13	2912
all_values[20]	auto[0]	auto[0]	auto[0]	2524772	1			T1	100		T11	421		T12	7396
all_values[20]	auto[0]	auto[0]	auto[1]	6417071	1			T1	1070		T12	22204		T13	214673
all_values[20]	auto[0]	auto[1]	auto[0]	695274	1			T1	127		T12	2237		T13	22401
all_values[20]	auto[0]	auto[1]	auto[1]	6429233	1			T1	1006		T12	18862		T13	217890
all_values[20]	auto[1]	auto[0]	auto[1]	91488	1			T1	47		T12	220		T13	2805
all_values[20]	auto[1]	auto[1]	auto[1]	92291	1			T1	60		T12	204		T13	2884
all_values[21]	auto[0]	auto[0]	auto[0]	2529961	1			T1	179		T11	421		T12	7413
all_values[21]	auto[0]	auto[0]	auto[1]	6412274	1			T1	1084		T12	20247		T13	210165
all_values[21]	auto[0]	auto[1]	auto[0]	693313	1			T1	144		T12	2080		T13	22099
all_values[21]	auto[0]	auto[1]	auto[1]	6430089	1			T1	910		T12	20924		T13	221142
all_values[21]	auto[1]	auto[0]	auto[1]	92316	1			T1	42		T12	218		T13	2969
all_values[21]	auto[1]	auto[1]	auto[1]	92176	1			T1	51		T12	241		T13	2822
all_values[22]	auto[0]	auto[0]	auto[0]	2539935	1			T1	186		T11	421		T12	7334
all_values[22]	auto[0]	auto[0]	auto[1]	6423590	1			T1	992		T12	19518		T13	214948
all_values[22]	auto[0]	auto[1]	auto[0]	687304	1			T1	230		T12	2155		T13	24101
all_values[22]	auto[0]	auto[1]	auto[1]	6415694	1			T1	912		T12	21693		T13	214025
all_values[22]	auto[1]	auto[0]	auto[1]	91457	1			T1	45		T12	177		T13	2887
all_values[22]	auto[1]	auto[1]	auto[1]	92149	1			T1	45		T12	246		T13	2888
all_values[23]	auto[0]	auto[0]	auto[0]	2531654	1			T1	141		T11	421		T12	7408
all_values[23]	auto[0]	auto[0]	auto[1]	6410485	1			T1	1038		T12	20572		T13	211509
all_values[23]	auto[0]	auto[1]	auto[0]	692218	1			T1	83		T12	2347		T13	23849
all_values[23]	auto[0]	auto[1]	auto[1]	6432003	1			T1	1040		T12	20386		T13	219385
all_values[23]	auto[1]	auto[0]	auto[1]	91858	1			T1	58		T12	201		T13	2829
all_values[23]	auto[1]	auto[1]	auto[1]	91911	1			T1	50		T12	209		T13	2891
all_values[24]	auto[0]	auto[0]	auto[0]	2528557	1			T1	169		T11	421		T12	7133
all_values[24]	auto[0]	auto[0]	auto[1]	6437829	1			T1	840		T12	20425		T13	214188
all_values[24]	auto[0]	auto[1]	auto[0]	687249	1			T1	210		T12	2158		T13	24760
all_values[24]	auto[0]	auto[1]	auto[1]	6411697	1			T1	1103		T12	20988		T13	214615
all_values[24]	auto[1]	auto[0]	auto[1]	93098	1			T1	33		T12	207		T13	2896
all_values[24]	auto[1]	auto[1]	auto[1]	91699	1			T1	55		T12	212		T13	2911
all_values[25]	auto[0]	auto[0]	auto[0]	2532464	1			T1	126		T11	421		T12	7209
all_values[25]	auto[0]	auto[0]	auto[1]	6436718	1			T1	1066		T12	21710		T13	210802
all_values[25]	auto[0]	auto[1]	auto[0]	692156	1			T1	96		T12	2236		T13	23949
all_values[25]	auto[0]	auto[1]	auto[1]	6405116	1			T1	1007		T12	19534		T13	218372
all_values[25]	auto[1]	auto[0]	auto[1]	91950	1			T1	55		T12	175		T13	2925
all_values[25]	auto[1]	auto[1]	auto[1]	91725	1			T1	60		T12	259		T13	2821
all_values[26]	auto[0]	auto[0]	auto[0]	2524802	1			T1	115		T11	421		T12	7358
all_values[26]	auto[0]	auto[0]	auto[1]	6418874	1			T1	1211		T12	20723		T13	210177
all_values[26]	auto[0]	auto[1]	auto[0]	693897	1			T1	196		T12	1963		T13	21799
all_values[26]	auto[0]	auto[1]	auto[1]	6428645	1			T1	782		T12	20660		T13	221502
all_values[26]	auto[1]	auto[0]	auto[1]	92223	1			T1	67		T12	230		T13	2889
all_values[26]	auto[1]	auto[1]	auto[1]	91688	1			T1	39		T12	189		T13	2840
all_values[27]	auto[0]	auto[0]	auto[0]	2535814	1			T1	88		T11	421		T12	7062
all_values[27]	auto[0]	auto[0]	auto[1]	6428336	1			T1	1027		T12	21830		T13	209237
all_values[27]	auto[0]	auto[1]	auto[0]	687425	1			T1	77		T12	1949		T13	23971
all_values[27]	auto[0]	auto[1]	auto[1]	6414444	1			T1	1112		T12	19837		T13	216206
all_values[27]	auto[1]	auto[0]	auto[1]	92403	1			T1	46		T12	225		T13	2991
all_values[27]	auto[1]	auto[1]	auto[1]	91707	1			T1	60		T12	220		T13	2857
all_values[28]	auto[0]	auto[0]	auto[0]	2522878	1			T1	121		T11	421		T12	7325
all_values[28]	auto[0]	auto[0]	auto[1]	6430646	1			T1	902		T12	20437		T13	210469
all_values[28]	auto[0]	auto[1]	auto[0]	695779	1			T1	150		T12	2080		T13	22814
all_values[28]	auto[0]	auto[1]	auto[1]	6416566	1			T1	1144		T12	20865		T13	219892
all_values[28]	auto[1]	auto[0]	auto[1]	91799	1			T1	37		T12	221		T13	2824
all_values[28]	auto[1]	auto[1]	auto[1]	92461	1			T1	56		T12	195		T13	2897
all_values[29]	auto[0]	auto[0]	auto[0]	2534430	1			T1	103		T11	421		T12	7420
all_values[29]	auto[0]	auto[0]	auto[1]	6444739	1			T1	887		T12	21304		T13	210543
all_values[29]	auto[0]	auto[1]	auto[0]	692446	1			T1	141		T12	2273		T13	23366
all_values[29]	auto[0]	auto[1]	auto[1]	6394679	1			T1	1181		T12	19701		T13	219533
all_values[29]	auto[1]	auto[0]	auto[1]	91669	1			T1	34		T12	208		T13	2897
all_values[29]	auto[1]	auto[1]	auto[1]	92166	1			T1	64		T12	217		T13	2888
all_values[30]	auto[0]	auto[0]	auto[0]	2542554	1			T1	86		T11	421		T12	7504
all_values[30]	auto[0]	auto[0]	auto[1]	6397714	1			T1	988		T12	19899		T13	219465
all_values[30]	auto[0]	auto[1]	auto[0]	702723	1			T1	76		T12	2355		T13	24516
all_values[30]	auto[0]	auto[1]	auto[1]	6423047	1			T1	1154		T12	20947		T13	209034
all_values[30]	auto[1]	auto[0]	auto[1]	91989	1			T1	50		T12	205		T13	2950
all_values[30]	auto[1]	auto[1]	auto[1]	92102	1			T1	56		T12	213		T13	2842
all_values[31]	auto[0]	auto[0]	auto[0]	2533188	1			T1	125		T11	421		T12	7422
all_values[31]	auto[0]	auto[0]	auto[1]	6432232	1			T1	1076		T12	20158		T13	214907
all_values[31]	auto[0]	auto[1]	auto[0]	683690	1			T1	100		T12	2310		T13	23311
all_values[31]	auto[0]	auto[1]	auto[1]	6417029	1			T1	1010		T12	20772		T13	217461
all_values[31]	auto[1]	auto[0]	auto[1]	92130	1			T1	54		T12	255		T13	2886
all_values[31]	auto[1]	auto[1]	auto[1]	91860	1			T1	45		T12	206		T13	2799

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal