Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[1]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[2]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[3]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[4]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[5]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[6]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[7]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[8]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[9]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[10]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[11]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[12]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[13]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[14]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[15]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[16]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[17]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[18]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[19]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[20]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[21]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[22]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[23]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[24]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[25]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[26]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[27]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[28]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[29]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[30]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[31]	16008512	1			T1	2251		T11	813		T12	47700

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313724819

1

T1

55532

T11

6732

T12

956103

auto[1]

198547565

1

T1

16500

T11

19284

T12

570297

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406791585

1

T1

41877

T11

13562

T12

127019

auto[1]

105480799

1

T1

30155

T11

12454

T12

256208

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

376228763

1

T1

35487

T11

13523

T12

117341

auto[1]

136043621

1

T1

36545

T11

12493

T12

352990

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5947407	1			T1	719		T11	13		T12	19113
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4142986	1			T1	25		T11	226		T12	13332
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1657371	1			T1	452		T11	190		T12	4120
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2189677	1			T1	560		T12	6516		T13	77841
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	425849	1			T1	16		T11	226		T12	579
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1645222	1			T1	479		T11	158		T12	4040
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5951709	1			T1	584		T11	15		T12	19608
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4145175	1			T1	28		T11	219		T12	13318
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1655671	1			T1	514		T11	172		T12	4179
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2183984	1			T1	666		T12	6188		T13	77135
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	425319	1			T1	9		T11	199		T12	521
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1646654	1			T1	450		T11	208		T12	3886
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5953594	1			T1	532		T11	14		T12	19382
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4145278	1			T1	22		T11	204		T12	13296
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1658042	1			T1	429		T11	156		T12	4158
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2187953	1			T1	684		T12	6210		T13	76218
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	421874	1			T1	14		T11	194		T12	567
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1641771	1			T1	570		T11	245		T12	4087
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5956534	1			T1	642		T11	13		T12	19472
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4142046	1			T1	18		T11	177		T12	13240
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1661010	1			T1	483		T11	220		T12	3857
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2186432	1			T1	584		T12	6484		T13	78023
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	424886	1			T1	18		T11	191		T12	571
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1637604	1			T1	506		T11	212		T12	4076
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5952389	1			T1	657		T11	12		T12	19006
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4139154	1			T1	25		T11	272		T12	13325
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1662060	1			T1	516		T11	193		T12	4053
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2187807	1			T1	618		T12	6454		T13	77136
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	423922	1			T1	16		T11	164		T12	591
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1643180	1			T1	419		T11	172		T12	4271
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5960781	1			T1	541		T11	12		T12	19211
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4132806	1			T1	12		T11	237		T12	13266
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1656953	1			T1	453		T11	204		T12	3991
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2185983	1			T1	688		T12	6745		T13	78141
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	423001	1			T1	22		T11	188		T12	647
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1648988	1			T1	535		T11	172		T12	3840
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5960260	1			T1	754		T11	8		T12	18983
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4137128	1			T1	24		T11	208		T12	13310
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1659097	1			T1	543		T11	174		T12	3916
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2184594	1			T1	508		T12	6562		T13	77753
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	424241	1			T1	17		T11	256		T12	626
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1643192	1			T1	405		T11	167		T12	4303
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5955536	1			T1	492		T11	15		T12	19269
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4134854	1			T1	26		T11	213		T12	13088
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1653994	1			T1	459		T11	210		T12	3811
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2185676	1			T1	700		T12	6688		T13	77975
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	424145	1			T1	19		T11	189		T12	639
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1654307	1			T1	555		T11	186		T12	4205
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5954880	1			T1	535		T11	17		T12	19433
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4140244	1			T1	16		T11	229		T12	13298
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1658126	1			T1	402		T11	196		T12	4068
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2187544	1			T1	768		T12	6423		T13	76616
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	424400	1			T1	26		T11	191		T12	544
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1643318	1			T1	504		T11	180		T12	3934
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5952128	1			T1	726		T11	14		T12	19753
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4138674	1			T1	20		T11	214		T12	13384
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1657805	1			T1	469		T11	198		T12	3880
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2190642	1			T1	587		T12	6401		T13	77956
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	423935	1			T1	26		T11	176		T12	573
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1645328	1			T1	423		T11	211		T12	3709
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5960897	1			T1	550		T11	12		T12	19549
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4142788	1			T1	20		T11	207		T12	13297
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1661878	1			T1	431		T11	178		T12	4141
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2180565	1			T1	730		T12	6369		T13	77396
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	420954	1			T1	17		T11	226		T12	530
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1641430	1			T1	503		T11	190		T12	3814
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5954277	1			T1	634		T11	14		T12	19322
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4140967	1			T1	17		T11	202		T12	13213
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1655870	1			T1	483		T11	190		T12	4098
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2190609	1			T1	644		T12	6507		T13	78298
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	424937	1			T1	20		T11	188		T12	599
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1641852	1			T1	453		T11	219		T12	3961
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5955716	1			T1	612		T11	19		T12	19711
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4138694	1			T1	20		T11	255		T12	13179
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1660242	1			T1	472		T11	168		T12	3993
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2180567	1			T1	645		T12	6376		T13	76481
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	424551	1			T1	23		T11	182		T12	577
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1648742	1			T1	479		T11	189		T12	3864
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5957885	1			T1	629		T11	16		T12	19215
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4147386	1			T1	28		T11	218		T12	13187
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1665625	1			T1	408		T11	168		T12	4113
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2178735	1			T1	695		T12	6504		T13	76580
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	421689	1			T1	12		T11	187		T12	613
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1637192	1			T1	479		T11	224		T12	4068
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5964579	1			T1	627		T11	13		T12	19848
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4133458	1			T1	17		T11	197		T12	13092
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1664785	1			T1	537		T11	192		T12	3983
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2177834	1			T1	547		T12	6321		T13	77655
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	423015	1			T1	20		T11	242		T12	547
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1644841	1			T1	503		T11	169		T12	3909
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5970337	1			T1	659		T11	14		T12	19308
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4135994	1			T1	20		T11	208		T12	13214
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1661303	1			T1	306		T11	183		T12	4181
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2175855	1			T1	850		T12	6457		T13	77312
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	421755	1			T1	22		T11	218		T12	607
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1643268	1			T1	394		T11	190		T12	3933
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5973956	1			T1	754		T11	12		T12	19331
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4138513	1			T1	20		T11	240		T12	13431
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1651237	1			T1	419		T11	181		T12	4073
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2184320	1			T1	604		T12	6418		T13	75482
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	424644	1			T1	15		T11	224		T12	544
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1635842	1			T1	439		T11	156		T12	3903
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5966187	1			T1	713		T11	17		T12	19325
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4137009	1			T1	23		T11	201		T12	13198
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1658317	1			T1	516		T11	196		T12	4395
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2186865	1			T1	611		T12	6260		T13	75950
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	423131	1			T1	22		T11	219		T12	609
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1637003	1			T1	366		T11	180		T12	3913
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5958288	1			T1	583		T11	13		T12	19280
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4144853	1			T1	25		T11	216		T12	13307
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1651606	1			T1	557		T11	212		T12	3877
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2191213	1			T1	651		T12	6869		T13	76749
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	424458	1			T1	20		T11	180		T12	550
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1638094	1			T1	415		T11	192		T12	3817
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5960134	1			T1	541		T11	18		T12	20029
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4143236	1			T1	3		T11	194		T12	13221
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1655622	1			T1	456		T11	222		T12	3862
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2190237	1			T1	721		T12	5997		T13	77386
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	425122	1			T1	28		T11	176		T12	517
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1634161	1			T1	502		T11	203		T12	4074
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5959407	1			T1	582		T11	9		T12	19270
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4142127	1			T1	19		T11	189		T12	13249
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1653089	1			T1	545		T11	244		T12	4161
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2190351	1			T1	600		T12	6433		T13	78184
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	425522	1			T1	19		T11	174		T12	622
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1638016	1			T1	486		T11	197		T12	3965
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5966622	1			T1	585		T11	17		T12	19744
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4138977	1			T1	7		T11	221		T12	13280
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1653602	1			T1	484		T11	192		T12	4279
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2188499	1			T1	607		T12	6228		T13	76814
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	424668	1			T1	27		T11	214		T12	535
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1636144	1			T1	541		T11	169		T12	3634
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5965403	1			T1	665		T11	13		T12	19519
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4137232	1			T1	23		T11	205		T12	13369
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1652711	1			T1	485		T11	224		T12	3861
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2188408	1			T1	598		T12	6544		T13	75706
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	425062	1			T1	16		T11	166		T12	535
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1639696	1			T1	464		T11	205		T12	3872
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5961107	1			T1	557		T11	13		T12	19239
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4147236	1			T1	12		T11	203		T12	13143
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1651804	1			T1	558		T11	225		T12	3546
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2188369	1			T1	566		T12	7100		T13	77623
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	423273	1			T1	24		T11	176		T12	670
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1636723	1			T1	534		T11	196		T12	4002
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5962298	1			T1	666		T11	14		T12	19536
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4143599	1			T1	25		T11	216		T12	13390
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1647106	1			T1	467		T11	215		T12	3855
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2190176	1			T1	611		T12	6473		T13	77890
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	422025	1			T1	13		T11	174		T12	523
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1643308	1			T1	469		T11	194		T12	3923
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5985332	1			T1	493		T11	11		T12	19177
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4124595	1			T1	20		T11	233		T12	13090
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1654363	1			T1	451		T11	178		T12	3855
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2187931	1			T1	701		T12	6840		T13	77778
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	426168	1			T1	16		T11	185		T12	658
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1630123	1			T1	570		T11	206		T12	4080
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5959992	1			T1	651		T11	13		T12	19774
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4143699	1			T1	14		T11	181		T12	13272
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1650735	1			T1	445		T11	196		T12	3771
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2189941	1			T1	640		T12	6319		T13	77264
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	424177	1			T1	34		T11	214		T12	544
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1639968	1			T1	467		T11	209		T12	4020
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5969865	1			T1	597		T11	15		T12	19113
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4132023	1			T1	16		T11	185		T12	13203
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1645885	1			T1	409		T11	170		T12	4086
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2197075	1			T1	718		T12	6512		T13	76396
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	424352	1			T1	31		T11	248		T12	579
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1639312	1			T1	480		T11	195		T12	4207
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5973209	1			T1	671		T11	11		T12	19140
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4132621	1			T1	30		T11	213		T12	13165
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1652696	1			T1	441		T11	202		T12	4274
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2189921	1			T1	618		T12	6402		T13	76756
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	425437	1			T1	15		T11	180		T12	598
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1634628	1			T1	476		T11	207		T12	4121
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5980780	1			T1	737		T11	16		T12	19166
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4136504	1			T1	18		T11	192		T12	13257
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1648034	1			T1	439		T11	190		T12	4314
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2185034	1			T1	574		T12	6329		T13	77078
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	425510	1			T1	17		T11	217		T12	616
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1632650	1			T1	466		T11	198		T12	4018
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5958435	1			T1	568		T11	16		T12	19169
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4147047	1			T1	30		T11	196		T12	13305
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1648276	1			T1	444		T11	218		T12	4205
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2192151	1			T1	699		T12	6281		T13	77537
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	423356	1			T1	13		T11	193		T12	555
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1639247	1			T1	497		T11	190		T12	4185
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5961140	1			T1	664		T11	18		T12	19520
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4150425	1			T1	21		T11	220		T12	13277
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1655456	1			T1	450		T11	228		T12	3743
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2178436	1			T1	696		T12	6679		T13	76846
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	424431	1			T1	17		T11	167		T12	606
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1638624	1			T1	403		T11	180		T12	3875

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal