Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[1]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[2]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[3]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[4]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[5]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[6]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[7]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[8]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[9]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[10]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[11]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[12]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[13]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[14]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[15]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[16]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[17]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[18]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[19]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[20]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[21]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[22]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[23]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[24]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[25]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[26]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[27]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[28]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[29]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[30]	16008512	1			T1	2251		T11	813		T12	47700
bins_for_gpio_bits[31]	16008512	1			T1	2251		T11	813		T12	47700

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313724819

1

T1

55532

T11

6732

T12

956103

auto[1]

198547565

1

T1

16500

T11

19284

T12

570297

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313715857

1

T1

55525

T11

6737

T12

955982

auto[1]

198556527

1

T1

16507

T11

19279

T12

570418

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9498861	1			T1	1660		T11	157		T12	29022
bins_for_gpio_bits[0]	auto[0]	auto[1]	295305	1			T1	70		T11	46		T12	720
bins_for_gpio_bits[0]	auto[1]	auto[0]	295594	1			T1	71		T11	46		T12	727
bins_for_gpio_bits[0]	auto[1]	auto[1]	5918752	1			T1	450		T11	564		T12	17231
bins_for_gpio_bits[1]	auto[0]	auto[0]	9495631	1			T1	1702		T11	140		T12	29272
bins_for_gpio_bits[1]	auto[0]	auto[1]	295417	1			T1	62		T11	47		T12	698
bins_for_gpio_bits[1]	auto[1]	auto[0]	295733	1			T1	62		T11	47		T12	703
bins_for_gpio_bits[1]	auto[1]	auto[1]	5921731	1			T1	425		T11	579		T12	17027
bins_for_gpio_bits[2]	auto[0]	auto[0]	9504283	1			T1	1577		T11	122		T12	29027
bins_for_gpio_bits[2]	auto[0]	auto[1]	295057	1			T1	68		T11	48		T12	720
bins_for_gpio_bits[2]	auto[1]	auto[0]	295306	1			T1	68		T11	48		T12	723
bins_for_gpio_bits[2]	auto[1]	auto[1]	5913866	1			T1	538		T11	595		T12	17230
bins_for_gpio_bits[3]	auto[0]	auto[0]	9508541	1			T1	1631		T11	185		T12	29107
bins_for_gpio_bits[3]	auto[0]	auto[1]	295167	1			T1	78		T11	48		T12	703
bins_for_gpio_bits[3]	auto[1]	auto[0]	295435	1			T1	78		T11	48		T12	706
bins_for_gpio_bits[3]	auto[1]	auto[1]	5909369	1			T1	464		T11	532		T12	17184
bins_for_gpio_bits[4]	auto[0]	auto[0]	9506072	1			T1	1729		T11	154		T12	28768
bins_for_gpio_bits[4]	auto[0]	auto[1]	295903	1			T1	61		T11	52		T12	739
bins_for_gpio_bits[4]	auto[1]	auto[0]	296184	1			T1	62		T11	51		T12	745
bins_for_gpio_bits[4]	auto[1]	auto[1]	5910353	1			T1	399		T11	556		T12	17448
bins_for_gpio_bits[5]	auto[0]	auto[0]	9507777	1			T1	1602		T11	170		T12	29226
bins_for_gpio_bits[5]	auto[0]	auto[1]	295709	1			T1	79		T11	46		T12	720
bins_for_gpio_bits[5]	auto[1]	auto[0]	295940	1			T1	80		T11	46		T12	721
bins_for_gpio_bits[5]	auto[1]	auto[1]	5909086	1			T1	490		T11	551		T12	17033
bins_for_gpio_bits[6]	auto[0]	auto[0]	9508172	1			T1	1739		T11	134		T12	28715
bins_for_gpio_bits[6]	auto[0]	auto[1]	295515	1			T1	66		T11	48		T12	742
bins_for_gpio_bits[6]	auto[1]	auto[0]	295779	1			T1	66		T11	48		T12	746
bins_for_gpio_bits[6]	auto[1]	auto[1]	5909046	1			T1	380		T11	583		T12	17497
bins_for_gpio_bits[7]	auto[0]	auto[0]	9499202	1			T1	1574		T11	179		T12	29048
bins_for_gpio_bits[7]	auto[0]	auto[1]	295705	1			T1	77		T11	46		T12	717
bins_for_gpio_bits[7]	auto[1]	auto[0]	296004	1			T1	77		T11	46		T12	720
bins_for_gpio_bits[7]	auto[1]	auto[1]	5917601	1			T1	523		T11	542		T12	17215
bins_for_gpio_bits[8]	auto[0]	auto[0]	9504676	1			T1	1636		T11	162		T12	29235
bins_for_gpio_bits[8]	auto[0]	auto[1]	295566	1			T1	69		T11	51		T12	683
bins_for_gpio_bits[8]	auto[1]	auto[0]	295874	1			T1	69		T11	51		T12	689
bins_for_gpio_bits[8]	auto[1]	auto[1]	5912396	1			T1	477		T11	549		T12	17093
bins_for_gpio_bits[9]	auto[0]	auto[0]	9504128	1			T1	1715		T11	155		T12	29339
bins_for_gpio_bits[9]	auto[0]	auto[1]	296132	1			T1	66		T11	57		T12	694
bins_for_gpio_bits[9]	auto[1]	auto[0]	296447	1			T1	67		T11	57		T12	695
bins_for_gpio_bits[9]	auto[1]	auto[1]	5911805	1			T1	403		T11	544		T12	16972
bins_for_gpio_bits[10]	auto[0]	auto[0]	9507921	1			T1	1633		T11	141		T12	29396
bins_for_gpio_bits[10]	auto[0]	auto[1]	295132	1			T1	78		T11	49		T12	662
bins_for_gpio_bits[10]	auto[1]	auto[0]	295419	1			T1	78		T11	49		T12	663
bins_for_gpio_bits[10]	auto[1]	auto[1]	5910040	1			T1	462		T11	574		T12	16979
bins_for_gpio_bits[11]	auto[0]	auto[0]	9505025	1			T1	1693		T11	156		T12	29206
bins_for_gpio_bits[11]	auto[0]	auto[1]	295459	1			T1	68		T11	48		T12	717
bins_for_gpio_bits[11]	auto[1]	auto[0]	295731	1			T1	68		T11	48		T12	721
bins_for_gpio_bits[11]	auto[1]	auto[1]	5912297	1			T1	422		T11	561		T12	17056
bins_for_gpio_bits[12]	auto[0]	auto[0]	9500678	1			T1	1667		T11	137		T12	29355
bins_for_gpio_bits[12]	auto[0]	auto[1]	295568	1			T1	62		T11	50		T12	722
bins_for_gpio_bits[12]	auto[1]	auto[0]	295847	1			T1	62		T11	50		T12	725
bins_for_gpio_bits[12]	auto[1]	auto[1]	5916419	1			T1	460		T11	576		T12	16898
bins_for_gpio_bits[13]	auto[0]	auto[0]	9506691	1			T1	1669		T11	140		T12	29114
bins_for_gpio_bits[13]	auto[0]	auto[1]	295236	1			T1	63		T11	44		T12	714
bins_for_gpio_bits[13]	auto[1]	auto[0]	295554	1			T1	63		T11	44		T12	718
bins_for_gpio_bits[13]	auto[1]	auto[1]	5911031	1			T1	456		T11	585		T12	17154
bins_for_gpio_bits[14]	auto[0]	auto[0]	9511891	1			T1	1637		T11	157		T12	29457
bins_for_gpio_bits[14]	auto[0]	auto[1]	295035	1			T1	73		T11	48		T12	693
bins_for_gpio_bits[14]	auto[1]	auto[0]	295307	1			T1	74		T11	48		T12	695
bins_for_gpio_bits[14]	auto[1]	auto[1]	5906279	1			T1	467		T11	560		T12	16855
bins_for_gpio_bits[15]	auto[0]	auto[0]	9512042	1			T1	1756		T11	149		T12	29231
bins_for_gpio_bits[15]	auto[0]	auto[1]	295188	1			T1	59		T11	49		T12	709
bins_for_gpio_bits[15]	auto[1]	auto[0]	295453	1			T1	59		T11	48		T12	715
bins_for_gpio_bits[15]	auto[1]	auto[1]	5905829	1			T1	377		T11	567		T12	17045
bins_for_gpio_bits[16]	auto[0]	auto[0]	9514400	1			T1	1716		T11	145		T12	29127
bins_for_gpio_bits[16]	auto[0]	auto[1]	294801	1			T1	61		T11	49		T12	692
bins_for_gpio_bits[16]	auto[1]	auto[0]	295113	1			T1	61		T11	48		T12	695
bins_for_gpio_bits[16]	auto[1]	auto[1]	5904198	1			T1	413		T11	571		T12	17186
bins_for_gpio_bits[17]	auto[0]	auto[0]	9515612	1			T1	1792		T11	165		T12	29247
bins_for_gpio_bits[17]	auto[0]	auto[1]	295459	1			T1	48		T11	48		T12	728
bins_for_gpio_bits[17]	auto[1]	auto[0]	295757	1			T1	48		T11	48		T12	733
bins_for_gpio_bits[17]	auto[1]	auto[1]	5901684	1			T1	363		T11	552		T12	16992
bins_for_gpio_bits[18]	auto[0]	auto[0]	9505652	1			T1	1732		T11	178		T12	29308
bins_for_gpio_bits[18]	auto[0]	auto[1]	295196	1			T1	59		T11	47		T12	715
bins_for_gpio_bits[18]	auto[1]	auto[0]	295455	1			T1	59		T11	47		T12	718
bins_for_gpio_bits[18]	auto[1]	auto[1]	5912209	1			T1	401		T11	541		T12	16959
bins_for_gpio_bits[19]	auto[0]	auto[0]	9510491	1			T1	1656		T11	191		T12	29196
bins_for_gpio_bits[19]	auto[0]	auto[1]	295226	1			T1	62		T11	49		T12	686
bins_for_gpio_bits[19]	auto[1]	auto[0]	295502	1			T1	62		T11	49		T12	692
bins_for_gpio_bits[19]	auto[1]	auto[1]	5907293	1			T1	471		T11	524		T12	17126
bins_for_gpio_bits[20]	auto[0]	auto[0]	9506876	1			T1	1658		T11	204		T12	29125
bins_for_gpio_bits[20]	auto[0]	auto[1]	295697	1			T1	69		T11	49		T12	735
bins_for_gpio_bits[20]	auto[1]	auto[0]	295971	1			T1	69		T11	49		T12	739
bins_for_gpio_bits[20]	auto[1]	auto[1]	5909968	1			T1	455		T11	511		T12	17101
bins_for_gpio_bits[21]	auto[0]	auto[0]	9513500	1			T1	1606		T11	163		T12	29556
bins_for_gpio_bits[21]	auto[0]	auto[1]	294999	1			T1	70		T11	46		T12	693
bins_for_gpio_bits[21]	auto[1]	auto[0]	295223	1			T1	70		T11	46		T12	695
bins_for_gpio_bits[21]	auto[1]	auto[1]	5904790	1			T1	505		T11	558		T12	16756
bins_for_gpio_bits[22]	auto[0]	auto[0]	9509811	1			T1	1681		T11	185		T12	29226
bins_for_gpio_bits[22]	auto[0]	auto[1]	296411	1			T1	66		T11	52		T12	696
bins_for_gpio_bits[22]	auto[1]	auto[0]	296711	1			T1	67		T11	52		T12	698
bins_for_gpio_bits[22]	auto[1]	auto[1]	5905579	1			T1	437		T11	524		T12	17080
bins_for_gpio_bits[23]	auto[0]	auto[0]	9505815	1			T1	1604		T11	184		T12	29165
bins_for_gpio_bits[23]	auto[0]	auto[1]	295217	1			T1	77		T11	55		T12	715
bins_for_gpio_bits[23]	auto[1]	auto[0]	295465	1			T1	77		T11	54		T12	720
bins_for_gpio_bits[23]	auto[1]	auto[1]	5912015	1			T1	493		T11	520		T12	17100
bins_for_gpio_bits[24]	auto[0]	auto[0]	9503860	1			T1	1682		T11	177		T12	29149
bins_for_gpio_bits[24]	auto[0]	auto[1]	295406	1			T1	62		T11	53		T12	713
bins_for_gpio_bits[24]	auto[1]	auto[0]	295720	1			T1	62		T11	52		T12	715
bins_for_gpio_bits[24]	auto[1]	auto[1]	5913526	1			T1	445		T11	531		T12	17123
bins_for_gpio_bits[25]	auto[0]	auto[0]	9533130	1			T1	1570		T11	142		T12	29150
bins_for_gpio_bits[25]	auto[0]	auto[1]	294233	1			T1	74		T11	47		T12	716
bins_for_gpio_bits[25]	auto[1]	auto[0]	294496	1			T1	75		T11	47		T12	722
bins_for_gpio_bits[25]	auto[1]	auto[1]	5886653	1			T1	532		T11	577		T12	17112
bins_for_gpio_bits[26]	auto[0]	auto[0]	9504393	1			T1	1674		T11	158		T12	29152
bins_for_gpio_bits[26]	auto[0]	auto[1]	295994	1			T1	62		T11	51		T12	707
bins_for_gpio_bits[26]	auto[1]	auto[0]	296275	1			T1	62		T11	51		T12	712
bins_for_gpio_bits[26]	auto[1]	auto[1]	5911850	1			T1	453		T11	553		T12	17129
bins_for_gpio_bits[27]	auto[0]	auto[0]	9516904	1			T1	1651		T11	136		T12	28960
bins_for_gpio_bits[27]	auto[0]	auto[1]	295672	1			T1	73		T11	49		T12	748
bins_for_gpio_bits[27]	auto[1]	auto[0]	295921	1			T1	73		T11	49		T12	751
bins_for_gpio_bits[27]	auto[1]	auto[1]	5900015	1			T1	454		T11	579		T12	17241
bins_for_gpio_bits[28]	auto[0]	auto[0]	9519598	1			T1	1670		T11	162		T12	29093
bins_for_gpio_bits[28]	auto[0]	auto[1]	295916	1			T1	60		T11	51		T12	720
bins_for_gpio_bits[28]	auto[1]	auto[0]	296228	1			T1	60		T11	51		T12	723
bins_for_gpio_bits[28]	auto[1]	auto[1]	5896770	1			T1	461		T11	549		T12	17164
bins_for_gpio_bits[29]	auto[0]	auto[0]	9519032	1			T1	1699		T11	157		T12	29076
bins_for_gpio_bits[29]	auto[0]	auto[1]	294553	1			T1	51		T11	49		T12	727
bins_for_gpio_bits[29]	auto[1]	auto[0]	294816	1			T1	51		T11	49		T12	733
bins_for_gpio_bits[29]	auto[1]	auto[1]	5900111	1			T1	450		T11	558		T12	17164
bins_for_gpio_bits[30]	auto[0]	auto[0]	9503328	1			T1	1647		T11	187		T12	28907
bins_for_gpio_bits[30]	auto[0]	auto[1]	295231	1			T1	64		T11	47		T12	746
bins_for_gpio_bits[30]	auto[1]	auto[0]	295534	1			T1	64		T11	47		T12	748
bins_for_gpio_bits[30]	auto[1]	auto[1]	5914419	1			T1	476		T11	532		T12	17299
bins_for_gpio_bits[31]	auto[0]	auto[0]	9499751	1			T1	1749		T11	192		T12	29257
bins_for_gpio_bits[31]	auto[0]	auto[1]	295008	1			T1	61		T11	54		T12	680
bins_for_gpio_bits[31]	auto[1]	auto[0]	295281	1			T1	61		T11	54		T12	685
bins_for_gpio_bits[31]	auto[1]	auto[1]	5918472	1			T1	380		T11	513		T12	17078