Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9019766 |
1 |
|
|
T1 |
1245 |
|
T11 |
421 |
|
T12 |
27180 |
| auto[1] |
7230363 |
1 |
|
|
T1 |
1165 |
|
T12 |
23943 |
|
T13 |
238605 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15325544 |
1 |
|
|
T1 |
2367 |
|
T11 |
421 |
|
T12 |
48157 |
| auto[1] |
924585 |
1 |
|
|
T1 |
43 |
|
T12 |
2966 |
|
T13 |
31595 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9050640 |
1 |
|
|
T1 |
1263 |
|
T11 |
421 |
|
T12 |
29808 |
| auto[1] |
7199489 |
1 |
|
|
T1 |
1147 |
|
T12 |
21315 |
|
T13 |
241732 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3126525 |
1 |
|
|
T1 |
534 |
|
T12 |
8764 |
|
T13 |
104715 |
| auto[1] |
auto[0] |
auto[1] |
459979 |
1 |
|
|
T1 |
21 |
|
T12 |
1407 |
|
T13 |
15700 |
| auto[1] |
auto[1] |
auto[0] |
3148379 |
1 |
|
|
T1 |
570 |
|
T12 |
9585 |
|
T13 |
105422 |
| auto[1] |
auto[1] |
auto[1] |
464606 |
1 |
|
|
T1 |
22 |
|
T12 |
1559 |
|
T13 |
15895 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9062565 |
1 |
|
|
T1 |
1084 |
|
T11 |
421 |
|
T12 |
28180 |
| auto[1] |
7187564 |
1 |
|
|
T1 |
1326 |
|
T12 |
22943 |
|
T13 |
240874 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15322814 |
1 |
|
|
T1 |
2374 |
|
T11 |
421 |
|
T12 |
47809 |
| auto[1] |
927315 |
1 |
|
|
T1 |
36 |
|
T12 |
3314 |
|
T13 |
32007 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9047855 |
1 |
|
|
T1 |
1223 |
|
T11 |
421 |
|
T12 |
27771 |
| auto[1] |
7202274 |
1 |
|
|
T1 |
1187 |
|
T12 |
23352 |
|
T13 |
242974 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3140696 |
1 |
|
|
T1 |
511 |
|
T12 |
10332 |
|
T13 |
104475 |
| auto[1] |
auto[0] |
auto[1] |
464631 |
1 |
|
|
T1 |
16 |
|
T12 |
1748 |
|
T13 |
15783 |
| auto[1] |
auto[1] |
auto[0] |
3134263 |
1 |
|
|
T1 |
640 |
|
T12 |
9706 |
|
T13 |
106492 |
| auto[1] |
auto[1] |
auto[1] |
462684 |
1 |
|
|
T1 |
20 |
|
T12 |
1566 |
|
T13 |
16224 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9094555 |
1 |
|
|
T1 |
1025 |
|
T11 |
421 |
|
T12 |
27689 |
| auto[1] |
7155574 |
1 |
|
|
T1 |
1385 |
|
T12 |
23434 |
|
T13 |
236275 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15321802 |
1 |
|
|
T1 |
2345 |
|
T11 |
421 |
|
T12 |
47785 |
| auto[1] |
928327 |
1 |
|
|
T1 |
65 |
|
T12 |
3338 |
|
T13 |
30202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9036299 |
1 |
|
|
T1 |
1035 |
|
T11 |
421 |
|
T12 |
28175 |
| auto[1] |
7213830 |
1 |
|
|
T1 |
1375 |
|
T12 |
22948 |
|
T13 |
233351 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3181421 |
1 |
|
|
T1 |
652 |
|
T12 |
9811 |
|
T13 |
104430 |
| auto[1] |
auto[0] |
auto[1] |
470709 |
1 |
|
|
T1 |
33 |
|
T12 |
1669 |
|
T13 |
15494 |
| auto[1] |
auto[1] |
auto[0] |
3104082 |
1 |
|
|
T1 |
658 |
|
T12 |
9799 |
|
T13 |
98719 |
| auto[1] |
auto[1] |
auto[1] |
457618 |
1 |
|
|
T1 |
32 |
|
T12 |
1669 |
|
T13 |
14708 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054248 |
1 |
|
|
T1 |
956 |
|
T11 |
421 |
|
T12 |
28962 |
| auto[1] |
7195881 |
1 |
|
|
T1 |
1454 |
|
T12 |
22161 |
|
T13 |
238390 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15327494 |
1 |
|
|
T1 |
2369 |
|
T11 |
421 |
|
T12 |
47607 |
| auto[1] |
922635 |
1 |
|
|
T1 |
41 |
|
T12 |
3516 |
|
T13 |
31611 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9074177 |
1 |
|
|
T1 |
1359 |
|
T11 |
421 |
|
T12 |
26762 |
| auto[1] |
7175952 |
1 |
|
|
T1 |
1051 |
|
T12 |
24361 |
|
T13 |
239476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3133045 |
1 |
|
|
T1 |
377 |
|
T12 |
11314 |
|
T13 |
103177 |
| auto[1] |
auto[0] |
auto[1] |
462436 |
1 |
|
|
T1 |
17 |
|
T12 |
1948 |
|
T13 |
15787 |
| auto[1] |
auto[1] |
auto[0] |
3120272 |
1 |
|
|
T1 |
633 |
|
T12 |
9531 |
|
T13 |
104688 |
| auto[1] |
auto[1] |
auto[1] |
460199 |
1 |
|
|
T1 |
24 |
|
T12 |
1568 |
|
T13 |
15824 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9047594 |
1 |
|
|
T1 |
1174 |
|
T11 |
421 |
|
T12 |
27802 |
| auto[1] |
7202535 |
1 |
|
|
T1 |
1236 |
|
T12 |
23321 |
|
T13 |
246908 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15331086 |
1 |
|
|
T1 |
2368 |
|
T11 |
421 |
|
T12 |
47750 |
| auto[1] |
919043 |
1 |
|
|
T1 |
42 |
|
T12 |
3373 |
|
T13 |
30926 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095733 |
1 |
|
|
T1 |
1258 |
|
T11 |
421 |
|
T12 |
28148 |
| auto[1] |
7154396 |
1 |
|
|
T1 |
1152 |
|
T12 |
22975 |
|
T13 |
236755 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3114993 |
1 |
|
|
T1 |
501 |
|
T12 |
9525 |
|
T13 |
100079 |
| auto[1] |
auto[0] |
auto[1] |
459964 |
1 |
|
|
T1 |
17 |
|
T12 |
1672 |
|
T13 |
15087 |
| auto[1] |
auto[1] |
auto[0] |
3120360 |
1 |
|
|
T1 |
609 |
|
T12 |
10077 |
|
T13 |
105750 |
| auto[1] |
auto[1] |
auto[1] |
459079 |
1 |
|
|
T1 |
25 |
|
T12 |
1701 |
|
T13 |
15839 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9074162 |
1 |
|
|
T1 |
1405 |
|
T11 |
421 |
|
T12 |
27717 |
| auto[1] |
7175967 |
1 |
|
|
T1 |
1005 |
|
T12 |
23406 |
|
T13 |
250536 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15325891 |
1 |
|
|
T1 |
2365 |
|
T11 |
421 |
|
T12 |
47830 |
| auto[1] |
924238 |
1 |
|
|
T1 |
45 |
|
T12 |
3293 |
|
T13 |
32421 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9057964 |
1 |
|
|
T1 |
1134 |
|
T11 |
421 |
|
T12 |
27766 |
| auto[1] |
7192165 |
1 |
|
|
T1 |
1276 |
|
T12 |
23357 |
|
T13 |
245804 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3137043 |
1 |
|
|
T1 |
637 |
|
T12 |
9558 |
|
T13 |
100568 |
| auto[1] |
auto[0] |
auto[1] |
461816 |
1 |
|
|
T1 |
24 |
|
T12 |
1535 |
|
T13 |
15039 |
| auto[1] |
auto[1] |
auto[0] |
3130884 |
1 |
|
|
T1 |
594 |
|
T12 |
10506 |
|
T13 |
112815 |
| auto[1] |
auto[1] |
auto[1] |
462422 |
1 |
|
|
T1 |
21 |
|
T12 |
1758 |
|
T13 |
17382 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9077943 |
1 |
|
|
T1 |
1187 |
|
T11 |
421 |
|
T12 |
28371 |
| auto[1] |
7172186 |
1 |
|
|
T1 |
1223 |
|
T12 |
22752 |
|
T13 |
233224 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15327264 |
1 |
|
|
T1 |
2364 |
|
T11 |
421 |
|
T12 |
47743 |
| auto[1] |
922865 |
1 |
|
|
T1 |
46 |
|
T12 |
3380 |
|
T13 |
31863 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9058462 |
1 |
|
|
T1 |
1340 |
|
T11 |
421 |
|
T12 |
28016 |
| auto[1] |
7191667 |
1 |
|
|
T1 |
1070 |
|
T12 |
23107 |
|
T13 |
243564 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3156884 |
1 |
|
|
T1 |
501 |
|
T12 |
10080 |
|
T13 |
111330 |
| auto[1] |
auto[0] |
auto[1] |
465229 |
1 |
|
|
T1 |
25 |
|
T12 |
1775 |
|
T13 |
16898 |
| auto[1] |
auto[1] |
auto[0] |
3111918 |
1 |
|
|
T1 |
523 |
|
T12 |
9647 |
|
T13 |
100371 |
| auto[1] |
auto[1] |
auto[1] |
457636 |
1 |
|
|
T1 |
21 |
|
T12 |
1605 |
|
T13 |
14965 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9024640 |
1 |
|
|
T1 |
1141 |
|
T11 |
421 |
|
T12 |
27432 |
| auto[1] |
7225489 |
1 |
|
|
T1 |
1269 |
|
T12 |
23691 |
|
T13 |
240442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15333968 |
1 |
|
|
T1 |
2367 |
|
T11 |
421 |
|
T12 |
47938 |
| auto[1] |
916161 |
1 |
|
|
T1 |
43 |
|
T12 |
3185 |
|
T13 |
31890 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9109085 |
1 |
|
|
T1 |
1013 |
|
T11 |
421 |
|
T12 |
28559 |
| auto[1] |
7141044 |
1 |
|
|
T1 |
1397 |
|
T12 |
22564 |
|
T13 |
241721 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3113630 |
1 |
|
|
T1 |
628 |
|
T12 |
9661 |
|
T13 |
108298 |
| auto[1] |
auto[0] |
auto[1] |
458276 |
1 |
|
|
T1 |
20 |
|
T12 |
1587 |
|
T13 |
16729 |
| auto[1] |
auto[1] |
auto[0] |
3111253 |
1 |
|
|
T1 |
726 |
|
T12 |
9718 |
|
T13 |
101533 |
| auto[1] |
auto[1] |
auto[1] |
457885 |
1 |
|
|
T1 |
23 |
|
T12 |
1598 |
|
T13 |
15161 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054463 |
1 |
|
|
T1 |
1172 |
|
T11 |
421 |
|
T12 |
28767 |
| auto[1] |
7195666 |
1 |
|
|
T1 |
1238 |
|
T12 |
22356 |
|
T13 |
232728 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15321273 |
1 |
|
|
T1 |
2360 |
|
T11 |
421 |
|
T12 |
48020 |
| auto[1] |
928856 |
1 |
|
|
T1 |
50 |
|
T12 |
3103 |
|
T13 |
31730 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9034010 |
1 |
|
|
T1 |
1168 |
|
T11 |
421 |
|
T12 |
29342 |
| auto[1] |
7216119 |
1 |
|
|
T1 |
1242 |
|
T12 |
21781 |
|
T13 |
241360 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3158189 |
1 |
|
|
T1 |
595 |
|
T12 |
9509 |
|
T13 |
110561 |
| auto[1] |
auto[0] |
auto[1] |
466380 |
1 |
|
|
T1 |
23 |
|
T12 |
1546 |
|
T13 |
16929 |
| auto[1] |
auto[1] |
auto[0] |
3129074 |
1 |
|
|
T1 |
597 |
|
T12 |
9169 |
|
T13 |
99069 |
| auto[1] |
auto[1] |
auto[1] |
462476 |
1 |
|
|
T1 |
27 |
|
T12 |
1557 |
|
T13 |
14801 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9057419 |
1 |
|
|
T1 |
1198 |
|
T11 |
421 |
|
T12 |
29355 |
| auto[1] |
7192710 |
1 |
|
|
T1 |
1212 |
|
T12 |
21768 |
|
T13 |
245586 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15326339 |
1 |
|
|
T1 |
2374 |
|
T11 |
421 |
|
T12 |
47815 |
| auto[1] |
923790 |
1 |
|
|
T1 |
36 |
|
T12 |
3308 |
|
T13 |
30584 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9069585 |
1 |
|
|
T1 |
1096 |
|
T11 |
421 |
|
T12 |
27906 |
| auto[1] |
7180544 |
1 |
|
|
T1 |
1314 |
|
T12 |
23217 |
|
T13 |
234015 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3128060 |
1 |
|
|
T1 |
690 |
|
T12 |
10314 |
|
T13 |
99651 |
| auto[1] |
auto[0] |
auto[1] |
462291 |
1 |
|
|
T1 |
19 |
|
T12 |
1649 |
|
T13 |
14835 |
| auto[1] |
auto[1] |
auto[0] |
3128694 |
1 |
|
|
T1 |
588 |
|
T12 |
9595 |
|
T13 |
103780 |
| auto[1] |
auto[1] |
auto[1] |
461499 |
1 |
|
|
T1 |
17 |
|
T12 |
1659 |
|
T13 |
15749 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9036910 |
1 |
|
|
T1 |
1250 |
|
T11 |
421 |
|
T12 |
29035 |
| auto[1] |
7213219 |
1 |
|
|
T1 |
1160 |
|
T12 |
22088 |
|
T13 |
239499 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15319162 |
1 |
|
|
T1 |
2373 |
|
T11 |
421 |
|
T12 |
47939 |
| auto[1] |
930967 |
1 |
|
|
T1 |
37 |
|
T12 |
3184 |
|
T13 |
31777 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9018346 |
1 |
|
|
T1 |
1386 |
|
T11 |
421 |
|
T12 |
28976 |
| auto[1] |
7231783 |
1 |
|
|
T1 |
1024 |
|
T12 |
22147 |
|
T13 |
241032 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3150011 |
1 |
|
|
T1 |
528 |
|
T12 |
9799 |
|
T13 |
104150 |
| auto[1] |
auto[0] |
auto[1] |
464505 |
1 |
|
|
T1 |
16 |
|
T12 |
1624 |
|
T13 |
15684 |
| auto[1] |
auto[1] |
auto[0] |
3150805 |
1 |
|
|
T1 |
459 |
|
T12 |
9164 |
|
T13 |
105105 |
| auto[1] |
auto[1] |
auto[1] |
466462 |
1 |
|
|
T1 |
21 |
|
T12 |
1560 |
|
T13 |
16093 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9048422 |
1 |
|
|
T1 |
1090 |
|
T11 |
421 |
|
T12 |
27932 |
| auto[1] |
7201707 |
1 |
|
|
T1 |
1320 |
|
T12 |
23191 |
|
T13 |
242302 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15320892 |
1 |
|
|
T1 |
2373 |
|
T11 |
421 |
|
T12 |
47649 |
| auto[1] |
929237 |
1 |
|
|
T1 |
37 |
|
T12 |
3474 |
|
T13 |
29966 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9045243 |
1 |
|
|
T1 |
1168 |
|
T11 |
421 |
|
T12 |
26687 |
| auto[1] |
7204886 |
1 |
|
|
T1 |
1242 |
|
T12 |
24436 |
|
T13 |
231206 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3150017 |
1 |
|
|
T1 |
488 |
|
T12 |
10748 |
|
T13 |
101768 |
| auto[1] |
auto[0] |
auto[1] |
467145 |
1 |
|
|
T1 |
16 |
|
T12 |
1878 |
|
T13 |
15308 |
| auto[1] |
auto[1] |
auto[0] |
3125632 |
1 |
|
|
T1 |
717 |
|
T12 |
10214 |
|
T13 |
99472 |
| auto[1] |
auto[1] |
auto[1] |
462092 |
1 |
|
|
T1 |
21 |
|
T12 |
1596 |
|
T13 |
14658 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9112368 |
1 |
|
|
T1 |
1323 |
|
T11 |
421 |
|
T12 |
29494 |
| auto[1] |
7137761 |
1 |
|
|
T1 |
1087 |
|
T12 |
21629 |
|
T13 |
242333 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15319831 |
1 |
|
|
T1 |
2356 |
|
T11 |
421 |
|
T12 |
47684 |
| auto[1] |
930298 |
1 |
|
|
T1 |
54 |
|
T12 |
3439 |
|
T13 |
32160 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9029872 |
1 |
|
|
T1 |
1138 |
|
T11 |
421 |
|
T12 |
27613 |
| auto[1] |
7220257 |
1 |
|
|
T1 |
1272 |
|
T12 |
23510 |
|
T13 |
244912 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3167481 |
1 |
|
|
T1 |
624 |
|
T12 |
10763 |
|
T13 |
106732 |
| auto[1] |
auto[0] |
auto[1] |
468516 |
1 |
|
|
T1 |
32 |
|
T12 |
1877 |
|
T13 |
16251 |
| auto[1] |
auto[1] |
auto[0] |
3122478 |
1 |
|
|
T1 |
594 |
|
T12 |
9308 |
|
T13 |
106020 |
| auto[1] |
auto[1] |
auto[1] |
461782 |
1 |
|
|
T1 |
22 |
|
T12 |
1562 |
|
T13 |
15909 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9033331 |
1 |
|
|
T1 |
1217 |
|
T11 |
421 |
|
T12 |
29820 |
| auto[1] |
7216798 |
1 |
|
|
T1 |
1193 |
|
T12 |
21303 |
|
T13 |
243175 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15325658 |
1 |
|
|
T1 |
2367 |
|
T11 |
421 |
|
T12 |
47812 |
| auto[1] |
924471 |
1 |
|
|
T1 |
43 |
|
T12 |
3311 |
|
T13 |
31424 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9056218 |
1 |
|
|
T1 |
1211 |
|
T11 |
421 |
|
T12 |
28192 |
| auto[1] |
7193911 |
1 |
|
|
T1 |
1199 |
|
T12 |
22931 |
|
T13 |
241660 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3117470 |
1 |
|
|
T1 |
567 |
|
T12 |
10053 |
|
T13 |
102873 |
| auto[1] |
auto[0] |
auto[1] |
458468 |
1 |
|
|
T1 |
17 |
|
T12 |
1712 |
|
T13 |
15208 |
| auto[1] |
auto[1] |
auto[0] |
3151970 |
1 |
|
|
T1 |
589 |
|
T12 |
9567 |
|
T13 |
107363 |
| auto[1] |
auto[1] |
auto[1] |
466003 |
1 |
|
|
T1 |
26 |
|
T12 |
1599 |
|
T13 |
16216 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9034551 |
1 |
|
|
T1 |
1305 |
|
T11 |
421 |
|
T12 |
27878 |
| auto[1] |
7215578 |
1 |
|
|
T1 |
1105 |
|
T12 |
23245 |
|
T13 |
246063 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15327897 |
1 |
|
|
T1 |
2355 |
|
T11 |
421 |
|
T12 |
48096 |
| auto[1] |
922232 |
1 |
|
|
T1 |
55 |
|
T12 |
3027 |
|
T13 |
30996 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9061042 |
1 |
|
|
T1 |
976 |
|
T11 |
421 |
|
T12 |
28918 |
| auto[1] |
7189087 |
1 |
|
|
T1 |
1434 |
|
T12 |
22205 |
|
T13 |
237428 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3133361 |
1 |
|
|
T1 |
701 |
|
T12 |
9016 |
|
T13 |
101079 |
| auto[1] |
auto[0] |
auto[1] |
461767 |
1 |
|
|
T1 |
29 |
|
T12 |
1506 |
|
T13 |
15021 |
| auto[1] |
auto[1] |
auto[0] |
3133494 |
1 |
|
|
T1 |
678 |
|
T12 |
10162 |
|
T13 |
105353 |
| auto[1] |
auto[1] |
auto[1] |
460465 |
1 |
|
|
T1 |
26 |
|
T12 |
1521 |
|
T13 |
15975 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054982 |
1 |
|
|
T1 |
1223 |
|
T11 |
421 |
|
T12 |
27029 |
| auto[1] |
7195147 |
1 |
|
|
T1 |
1187 |
|
T12 |
24094 |
|
T13 |
241014 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15321175 |
1 |
|
|
T1 |
2366 |
|
T11 |
421 |
|
T12 |
47811 |
| auto[1] |
928954 |
1 |
|
|
T1 |
44 |
|
T12 |
3312 |
|
T13 |
31751 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9039632 |
1 |
|
|
T1 |
1358 |
|
T11 |
421 |
|
T12 |
27821 |
| auto[1] |
7210497 |
1 |
|
|
T1 |
1052 |
|
T12 |
23302 |
|
T13 |
241847 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3150260 |
1 |
|
|
T1 |
516 |
|
T12 |
9598 |
|
T13 |
106894 |
| auto[1] |
auto[0] |
auto[1] |
466422 |
1 |
|
|
T1 |
25 |
|
T12 |
1565 |
|
T13 |
16167 |
| auto[1] |
auto[1] |
auto[0] |
3131283 |
1 |
|
|
T1 |
492 |
|
T12 |
10392 |
|
T13 |
103202 |
| auto[1] |
auto[1] |
auto[1] |
462532 |
1 |
|
|
T1 |
19 |
|
T12 |
1747 |
|
T13 |
15584 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9033997 |
1 |
|
|
T1 |
1237 |
|
T11 |
421 |
|
T12 |
28181 |
| auto[1] |
7216132 |
1 |
|
|
T1 |
1173 |
|
T12 |
22942 |
|
T13 |
246125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15323332 |
1 |
|
|
T1 |
2366 |
|
T11 |
421 |
|
T12 |
47750 |
| auto[1] |
926797 |
1 |
|
|
T1 |
44 |
|
T12 |
3373 |
|
T13 |
33135 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9040770 |
1 |
|
|
T1 |
1339 |
|
T11 |
421 |
|
T12 |
27215 |
| auto[1] |
7209359 |
1 |
|
|
T1 |
1071 |
|
T12 |
23908 |
|
T13 |
251987 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3164210 |
1 |
|
|
T1 |
507 |
|
T12 |
10351 |
|
T13 |
107404 |
| auto[1] |
auto[0] |
auto[1] |
467713 |
1 |
|
|
T1 |
18 |
|
T12 |
1635 |
|
T13 |
16013 |
| auto[1] |
auto[1] |
auto[0] |
3118352 |
1 |
|
|
T1 |
520 |
|
T12 |
10184 |
|
T13 |
111448 |
| auto[1] |
auto[1] |
auto[1] |
459084 |
1 |
|
|
T1 |
26 |
|
T12 |
1738 |
|
T13 |
17122 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9059484 |
1 |
|
|
T1 |
1042 |
|
T11 |
421 |
|
T12 |
27765 |
| auto[1] |
7190645 |
1 |
|
|
T1 |
1368 |
|
T12 |
23358 |
|
T13 |
242286 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15324029 |
1 |
|
|
T1 |
2381 |
|
T11 |
421 |
|
T12 |
48155 |
| auto[1] |
926100 |
1 |
|
|
T1 |
29 |
|
T12 |
2968 |
|
T13 |
30441 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9047332 |
1 |
|
|
T1 |
1359 |
|
T11 |
421 |
|
T12 |
30666 |
| auto[1] |
7202797 |
1 |
|
|
T1 |
1051 |
|
T12 |
20457 |
|
T13 |
234992 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3153951 |
1 |
|
|
T1 |
491 |
|
T12 |
8902 |
|
T13 |
103895 |
| auto[1] |
auto[0] |
auto[1] |
465630 |
1 |
|
|
T1 |
17 |
|
T12 |
1529 |
|
T13 |
15501 |
| auto[1] |
auto[1] |
auto[0] |
3122746 |
1 |
|
|
T1 |
531 |
|
T12 |
8587 |
|
T13 |
100656 |
| auto[1] |
auto[1] |
auto[1] |
460470 |
1 |
|
|
T1 |
12 |
|
T12 |
1439 |
|
T13 |
14940 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9061132 |
1 |
|
|
T1 |
1247 |
|
T11 |
421 |
|
T12 |
29094 |
| auto[1] |
7188997 |
1 |
|
|
T1 |
1163 |
|
T12 |
22029 |
|
T13 |
245142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15325445 |
1 |
|
|
T1 |
2362 |
|
T11 |
421 |
|
T12 |
47823 |
| auto[1] |
924684 |
1 |
|
|
T1 |
48 |
|
T12 |
3300 |
|
T13 |
31692 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9056817 |
1 |
|
|
T1 |
1265 |
|
T11 |
421 |
|
T12 |
28444 |
| auto[1] |
7193312 |
1 |
|
|
T1 |
1145 |
|
T12 |
22679 |
|
T13 |
242261 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3137943 |
1 |
|
|
T1 |
500 |
|
T12 |
10158 |
|
T13 |
105749 |
| auto[1] |
auto[0] |
auto[1] |
461529 |
1 |
|
|
T1 |
22 |
|
T12 |
1834 |
|
T13 |
15690 |
| auto[1] |
auto[1] |
auto[0] |
3130685 |
1 |
|
|
T1 |
597 |
|
T12 |
9221 |
|
T13 |
104820 |
| auto[1] |
auto[1] |
auto[1] |
463155 |
1 |
|
|
T1 |
26 |
|
T12 |
1466 |
|
T13 |
16002 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |