Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9057765 |
1 |
|
|
T1 |
1261 |
|
T11 |
421 |
|
T12 |
27949 |
| auto[1] |
7192364 |
1 |
|
|
T1 |
1149 |
|
T12 |
23174 |
|
T13 |
233776 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15321459 |
1 |
|
|
T1 |
2366 |
|
T11 |
421 |
|
T12 |
47715 |
| auto[1] |
928670 |
1 |
|
|
T1 |
44 |
|
T12 |
3408 |
|
T13 |
31254 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9032350 |
1 |
|
|
T1 |
1221 |
|
T11 |
421 |
|
T12 |
27526 |
| auto[1] |
7217779 |
1 |
|
|
T1 |
1189 |
|
T12 |
23597 |
|
T13 |
236993 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3146133 |
1 |
|
|
T1 |
697 |
|
T12 |
10197 |
|
T13 |
106428 |
| auto[1] |
auto[0] |
auto[1] |
465648 |
1 |
|
|
T1 |
22 |
|
T12 |
1680 |
|
T13 |
16153 |
| auto[1] |
auto[1] |
auto[0] |
3142976 |
1 |
|
|
T1 |
448 |
|
T12 |
9992 |
|
T13 |
99311 |
| auto[1] |
auto[1] |
auto[1] |
463022 |
1 |
|
|
T1 |
22 |
|
T12 |
1728 |
|
T13 |
15101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |